KR20070071794A - Liquid crystal display device and method for fabricating the same - Google Patents

Abstract

An LCD(Liquid Crystal Display) and a method of manufacturing the same are provided to efficiently perform a repair operation without vertical line defect by changing a repair structure of a data line. A first substrate faces a second substrate. A plurality of gate lines(101,101d) and data lines(107) intersect each other to define pixel regions in the first substrate. A thin film transistor(TFT) is formed in each of intersections between the gate lines and the data lines. A pixel electrode(111a) is formed in the pixel region. First and second repair lines are symmetrically formed in lower portions of both sides of the data line. Upper and lower portions of the first and second repair lines partially overlap the data lines. The first and second repair lines are formed in the same layer as the gate lines.

Description

Liquid crystal display device and method for manufacturing the same {Liquid Crystal Display Device and method for fabricating the same}

1 is an exploded perspective view showing a conventional liquid crystal display device

2 is a plan view showing a conventional liquid crystal display for a data line repair

3 is a cross-sectional view taken along line II ′ of FIG. 2.

4 is an equivalent circuit diagram illustrating parasitic capacitance between a data line of FIG. 3 and a neighboring pixel electrode and a repair line;

5 is a photograph showing a vertical failure according to the left and right shift of a conventional data line

6 is a plan view illustrating a liquid crystal display according to the present invention for data line repair.

7 is a cross-sectional view taken along line II-II ′ of FIG. 6.

FIG. 8 is an equivalent circuit diagram illustrating parasitic capacitance between the data line of FIG. 7 and neighboring pixel electrodes and a repair line.

9A to 9G are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: first substrate 101, 101d: gate line

102 gate insulating film 103 amorphous silicon layer

103a: active layer 104: n + amorphous silicon layer

104a: ohmic contact layer 105: first metal layer

106: second photoresist pattern 107: data line

107a: source electrode 107b: drain electrode

108: protective film 109: third photoresist pattern

110: first contact hole 111: transparent conductive film

111a: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display and a method of manufacturing the same, which can prevent a vertical band defect from occurring by changing a repair structure of a data line.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is currently being used most frequently as a substitute for CRT (Cathode Ray Tube) for mobile image display devices because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the mobile use, various developments have been made for televisions and monitors for receiving and displaying broadcast signals.

In order to use such a liquid crystal display as a general screen display device in various parts, it is a matter of how high quality images such as high definition, high brightness and large area can be realized while maintaining the characteristics of light weight, thinness and low power consumption. Can be.

Hereinafter, a liquid crystal display according to the related art will be described with reference to the accompanying drawings.

1 is an exploded perspective view showing a conventional liquid crystal display device.

The conventional liquid crystal display device 10 has the 1st board | substrate 1 and the 2nd board | substrate 2, and the said 1st board | substrate 1 and the 2nd board | substrate 2 which were bonded together with the fixed space as shown in FIG. It consists of the liquid crystal layer 3 injected in between.

In more detail, the first substrate 1 may have a plurality of gate lines 4 in one direction and constant in a direction perpendicular to the gate lines 4 at regular intervals to define the pixel region P. FIG. A plurality of data lines 5 are arranged at intervals. In addition, a pixel electrode 6 is formed in each pixel region P, and a thin film transistor T is formed at a portion where the gate line 4 and the data line 5 cross each other to form the gate line 4. The data signal of the data line 5 is applied to each pixel electrode 6 according to the signal applied to the?

In addition, a black matrix layer 7 is formed on the second substrate 2 to block light in portions other than the pixel region P, and portions R corresponding to the respective pixel regions are formed to express colors. , G, B color filter layers 8 are formed, and a common electrode 9 for realizing an image is formed on the color filter layers 8.

In the liquid crystal display device as described above, the liquid crystal of the liquid crystal layer 3 formed between the first and second substrates 1 and 2 is aligned by an electric field between the pixel electrode 6 and the common electrode 9, The amount of light passing through the liquid crystal layer 3 may be adjusted according to the degree of alignment of the liquid crystal layer 3 to express an image.

Such a liquid crystal display is called a twisted nematic mode liquid crystal display, and in addition to the TN mode liquid crystal display, an in-plane switching (IPS) liquid crystal display using a horizontal electric field has been developed. In the transverse electric field (IPS) mode liquid crystal display, a pixel electrode and a common electrode are formed parallel to each other at a predetermined distance in a pixel area of the first substrate so that a transverse electric field (horizontal electric field) is generated between the pixel electrode and the common electrode. The liquid crystal layer is aligned by the lateral electric field.

Hereinafter, a liquid crystal display according to the related art will be described with reference to the accompanying drawings.

FIG. 2 is a plan view illustrating a conventional liquid crystal display for repairing a data line, FIG. 3 is a cross-sectional view of the structure taken along line II ′ of FIG. 2, and FIG. 4 is a pixel electrode adjacent to the data line of FIG. 3. Equivalent circuit diagram showing parasitic capacitance between repair lines.

FIG. 5 is a photograph showing vertical defects according to a left and right shift of a conventional data line.

2. Description of the Related Art A conventional liquid crystal display for repairing a data line includes a first substrate 20 and a second substrate (not shown) facing each other and a first substrate 20 as shown in FIGS. 2 and 3. A plurality of gate lines 21 and data lines 27 crossing each other to define pixel regions, and a thin film transistor TFT formed at each intersection of the gate lines 21 and data lines 27 and the angles. And a plurality of pixel electrodes 31a formed in the pixel region and overlapping the front gate line 31d by a predetermined portion.

In the thin film transistor, a channel is defined in a region between the source electrode 27a and the drain electrode 27b, and the channel is also defined as a U 'shape along the inside of the shape of the source electrode 27a.

The thin film transistor includes a gate electrode 21a protruding from the gate line 21, a U′-shaped source electrode 27a protruding from the data line 27, and the U′-shaped source electrode ( And a drain electrode 27b spaced apart from the predetermined gap 27a and introduced into the U'-shaped source electrode 27a.

The active layer 23a and the ohmic contact layer 24a are disposed below the data line 27, the source electrode 27a, the drain electrode 27b, and the channel region between the source electrode 27a and the drain electrode 27b. ) Is laminated. The ohmic contact layer 24a is removed in the channel region corresponding to the region between the source electrode 27a and the drain electrode 27b.

The repair line 21b is configured on the left side of the data line 27 so as to overlap the data line 27 at upper and lower portions thereof. At this time, the repair line 21b is formed on the same layer as the gate line 21.

A gate insulating layer 22 is formed between the gate line 21 and the data line 27, and a passivation layer 28 is formed between the data line 27 and the pixel electrode 31a. The first contact hole 30 is formed in the passivation layer 28 so that a predetermined portion of the drain electrode 27b of the thin film transistor is exposed.

As described above, when the data line 27 disposed on one side of a predetermined pixel is opened, the repair line 21b overlapping the data line 27 is welded to the data line 27 and the repair line. Proceed with repair by making 21b) short.

The pixel electrode 31a partially overlaps the adjacent repair line 21a.

In general, an LCD has an overlapping portion between a gate electrode, a source electrode, a gate electrode, and a drain electrode of a thin film transistor, and thus has parasitic capacitances of Cgs and Cgd, respectively. Cgd varies the pixel electrode voltage by ΔVp by the inductive capacitance when the thin film transistor is turned off (where ΔVp represents the data voltage-the pixel electrode voltage), which has a significant effect on image quality. This variation is caused by the same magnitude of variation in the effective voltage of the liquid crystal. ΔVp is approximately expressed by the following equation.

In this case, Cgd represents a parasitic capacitance due to the overlapping portion of the gate electrode and the drain electrode, CLC represents a liquid crystal capacitance, Cstc represents an auxiliary capacitance, and ΔVg represents a gate voltage change applied to the scan line.

In the case of an ideal liquid crystal display device, the voltage across the pixel electrode is equal to the data voltage, so the liquid crystal effective voltage must be the same regardless of whether the applied data signal is a positive field or a negative field. However, as mentioned above, the general liquid crystal display device varies the pixel electrode voltage by ΔVp when the thin film transistor is turned off due to its parasitic capacitance and the data signal is applied.

[Delta] Vp is also represented by a liquid crystal display device having a pixel electrode 31a and a repair line 21b on both sides of a data line 27 having a conventional structure. In this case, [Delta] Vp can be expressed as follows. have.

In the liquid crystal display having the conventional structure, the distribution of parasitic capacitance between the pixel electrode 31a and the repair line 21b adjacent to the data line 27 is shown in FIG. 27, Cdp-Left, Cgp, and Cgd are configured in parallel on the left side, and Cdp-Right is configured on the right side around the data line 27.

Thereby, the capacitance Cdpl on the left side can be represented by the following [Equation 1].

[식1]

[Equation 1]

As described above, the parasitic capacitance when the repair line is on the left side and when the repair line is not provided may be expressed by the following inequality. The left side of the inequality sign has a repair line and the right side has no repair line.

As shown in Equation 1 and inequality, there is a difference in the Cdp with and without the repair line, and the parasitic capacitance is smaller than without the repair line. That is, since there is a repair line 21b only on the left side of the data line 27, there is a limit in reducing ΔVp due to a difference in parasitic capacitances on the left and right sides based on the data line 27.

In addition, when the data line is shifted in the left and right directions, as shown in the left and right pictures of FIG. 5, the amount of change of ΔVp received by the pixel when the repair line is present appears larger (due to the asymmetry of ΔVp). , Vertical band failure occurs.

Due to the above problem, the current repair line is not configured, and repair is not performed even if an open defect occurs in the data line.

The present invention has been made to solve the above problems, and an object of the present invention is to change the repair structure of the data line to minimize ΔVp to prevent the occurrence of vertical band defects and its manufacture To provide a method.

According to an aspect of the present invention, a liquid crystal display device includes: a first substrate and a second substrate facing each other; A plurality of gate lines and data lines crossing each other on the first substrate to define pixel regions; A thin film transistor formed at an intersection of the gate lines and the data lines; A pixel electrode formed in the pixel region; And first and second repair lines formed to be symmetrically formed under both sides of the data line.

The first and second repair lines may be formed to overlap the data lines at upper and lower portions, respectively.

The first and second repair lines may be formed on the same layer as the gate lines.

When the data line is opened, a portion of the upper and lower portions of the first and second repair lines overlapping the data line may be shorted with the data line to form two data signal movement paths.

The pixel electrode is partially overlapped with the adjacent first and second repair lines.

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, the method including: forming a gate line and a gate electrode on a substrate; A second step of forming first and second repair lines symmetrically formed in a direction orthogonal to the gate lines; A data line disposed between the gate line and horizontally to define a pixel area, and the first and second repair lines are symmetrical, a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode; Forming a third step; And forming a pixel electrode in the pixel region.

The first and second repair lines may protrude in a direction in which upper and lower portions thereof face each other, and the protruding portions overlap the data lines.

The first and second repair lines may be formed on the same layer as the gate lines.

The pixel electrode may overlap the first or second repair line formed in an adjacent pixel area.

Hereinafter, a liquid crystal display and a manufacturing method thereof according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described.

FIG. 6 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention for repairing a data line, FIG. 7 is a cross-sectional view taken along line II-II ′ of FIG. 6, and FIG. An equivalent circuit diagram showing parasitic capacitance between a pixel electrode and a repair line.

As illustrated in FIGS. 6 and 7, a liquid crystal display device according to an exemplary embodiment of the present invention includes a first substrate 100 and a second substrate (not shown), in which liquid crystal is filled therebetween to face each other. A thin film formed on a plurality of gate lines 101 and data lines 107 intersecting each other on the first substrate 100 to define pixel regions, and intersecting portions of the gate lines 101 and data lines 107. A transistor TFT and a plurality of pixel electrodes 111a formed in each pixel area and overlapping the front gate line 101d by a predetermined portion are included.

In the thin film transistor, a channel is defined in a region between the source electrode 107a and the drain electrode 107b, and the channel is also defined as a U 'shape along the inside of the shape of the source electrode 107a. The thin film transistor includes a gate electrode 101a protruding from the gate line 101, a U ′ shaped source electrode 107a protruding from the data line 107, and the U ′ shaped source electrode ( A drain electrode 107b spaced apart from the predetermined interval 107a and introduced into the U'-shaped source electrode 107a is formed. The active layer 103a and the ohmic contact layer 104a are disposed below the data line 107, the source electrode 107a, the drain electrode 107b, and the channel region between the source electrode 107a and the drain electrode 107b. ) Is laminated. The ohmic contact layer 104a is removed from the channel region corresponding to the region between the source electrode 107a and the drain electrode 107b.

The active layer 103a is selectively formed only under the source / drain electrodes 107a and 107b and the region therebetween, and the ohmic contact layer 104a includes the source electrode 107a and the drain except for the channel region. It may be formed below the electrode 107b.

Meanwhile, although the shape of the source electrode 107a is U ', the liquid crystal display having the' U'-shaped channel has been described. However, the liquid crystal display of the present invention has a shape of the source electrode 107a. Either way or the shape would be applicable.

6 and 7, the data line 107 overlaps the data line 107 at one portion of the upper and lower portions so that the data lines 107 are symmetrical with both sides of the data line 107 interposed therebetween. The first and second repair lines 101b and 101c are configured. In this case, the first and second repair lines 101b and 101c are formed on the same layer as the gate line 101.

A gate insulating layer 102 is formed between the gate line 101 and the data line 107, and a passivation layer 108 is formed between the data line 107 and the pixel electrode 111a. Here, the first contact hole 110 is formed in the passivation layer 108 so that a predetermined portion of the drain electrode 107b of the thin film transistor is exposed.

In case the data line 107 is opened in a predetermined pixel of the liquid crystal display as described above, the first and second repair lines 101b are symmetrical on both sides of each data line 107 arranged in one pixel. , 101c) is formed. The first and second repair lines 101b and 101c are formed to overlap the data line 107 in one region of the upper and lower regions of the data line 107 corresponding to one pixel.

Although not shown in the drawing, when the data line 107 is opened, the first and second repair lines 101b and 101c overlapped with the data line 107 are welded using a laser to form the data line 107 and the first line. The first and second repair lines 101b and 101c are connected to each other so that the data signal passes through the thin film transistor TFT to the pixel electrode 111a along two paths of the first and second repair lines 101b and 101c. To be delivered.

The pixel electrode 111a partially overlaps the adjacent first and second repair lines 101a and 101b.

In general, an LCD has an overlapping portion between a gate electrode, a source electrode, a gate electrode, and a drain electrode of a thin film transistor, and thus has parasitic capacitances of Cgs and Cgd, respectively. Cgd varies the pixel electrode voltage by ΔVp by the inductive capacitance when the thin film transistor is turned off (where ΔVp represents the data voltage-the pixel electrode voltage), which has a significant effect on image quality. This variation is caused by the same magnitude of variation in the effective voltage of the liquid crystal. ΔVp is approximately expressed by the following equation.

In this case, Cgd represents a parasitic capacitance due to the overlapping portion of the gate electrode and the drain electrode, CLC represents a liquid crystal capacitance, Cstc represents an auxiliary capacitance, and ΔVg represents a gate voltage change applied to the scan line.

In the case of an ideal liquid crystal display device, the voltage across the pixel electrode is equal to the data voltage, so the liquid crystal effective voltage must be the same regardless of whether the applied data signal is a positive field or a negative field. However, as mentioned above, the general liquid crystal display device varies the pixel electrode voltage by ΔVp when the thin film transistor is turned off due to its parasitic capacitance and the data signal is applied.

The above-mentioned? Vp is also shown by a liquid crystal display having a pixel electrode 111a on both sides of the data line 107 and first and second repair lines 101b and 101c. In this case,? Vp is as follows. Can be represented as:

According to the above equation, if Cdpr and Cdpl are the same, ΔVp becomes '0' so that the data signal is transferred to the pixel electrode without change in the pixel electrode voltage, thereby indicating an ideal driving efficiency.

The present invention relates to a configuration capable of minimizing the influence of ΔVp when the data line is open and needs to be repaired as described above.

To this end, in the present invention, the first and second repair lines 101b and 101c are symmetrically formed on both sides of the data line 107 to minimize the influence of ΔVp.

In more detail, the parasitic capacitance distribution form between the pixel electrode 111a and the first and second repair lines 101b and 101c adjacent to the data line 107 in the liquid crystal display having the above configuration. 8, Cdp-Left, Cgp, and Cgd are configured in parallel on the left side of the data line 107, and Cdp-Right and Cgp on the right side of the data line 107. , Cgd is configured in parallel.

Thereby, the capacitance Cdpl on the left side can be represented by the following [Equation 2], and the capacitance Cdpr on the right side can be expressed as below [Equation 3].

[식2]

[Equation 2]

[식3]

[Equation 3]

In the case where Cgp-Left and Cgp-Right are symmetrical, Cdpl and Cdpr are the same, so that ΔVp becomes '0', so that driving can be efficiently performed without being affected by parasitic capacitance.

Further, even if the data line 107 is shaken in any direction on the left or right side, since the first and second repair lines 101b and 101c are formed on both the left and right sides of the data line 107, the repair line is left or right. The data line 107 can be repaired in a state of minimizing [Delta] Vp than when it is configured only. That is, it is possible to minimize the occurrence of spots, such as vertical bands that were a problem of the prior art.

As described above, if the first and second repair lines 101b and 101c having the same size symmetrically to the left and right of the data line 107 are formed, imbalance of Cdp may be minimized.

Next, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention having the above configuration will be described.

9A to 9G are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention.

First, as shown in FIG. 9A, a gate metal layer is formed on the first substrate 100 through a deposition method such as a sputtering method.

Subsequently, the first photoresist pattern (not shown) is formed by a photolithograph process using a first mask, and the gate metal layer is protruded by patterning the gate metal layer by an etching process using the first photoresist pattern. Gate patterns including the gate electrode 101a are formed. '101d' is the previous gate line. The first and second repair lines 101b and 101c are formed to be spaced apart from the gate lines 101 and 101d so as to be symmetrical with each other in a vertical direction. The first and second repair lines 101b and 101c protrude in a direction in which upper and lower portions of the repair lines 101b and 101c face each other. The first and second repair lines 101b and 101c are configured to be symmetrically spaced apart on both sides of a data line 107 (see FIG. 9D) to be formed later.

Subsequently, as illustrated in FIG. 9B, the gate insulating layer 102 may be deposited on the first substrate 100 on which the gate patterns and the first and second repair lines 101b and 101c are formed by a deposition method such as PECVD or sputtering. , An amorphous silicon layer 103, an n + amorphous silicon layer 104, and a first metal layer 105 for forming a source / drain are sequentially formed. In this case, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the gate insulating film 102.

Thereafter, the second photoresist pattern 106 is formed on the first metal layer 105 by a photolithography process using a second mask. In this case, the second mask uses a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor so that the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Subsequently, as illustrated in FIG. 9C, the first metal layer 105 is patterned by a wet etching process using the second photoresist pattern 106, thereby providing the data line 107, the source electrode 107a, and the source electrode 107a. ), Metal patterns 105a are formed to form the drain electrode 107b integrated therewith.

Then, the ohmic contact layer 104a and the active layer 103a are formed by simultaneously patterning the n + amorphous silicon layer 104 and the amorphous silicon layer 103 by a dry etching process using the same second photoresist pattern 106. .

In the region where the data line 107 is to be formed, an amorphous silicon layer 103, an n + amorphous silicon layer 104, and a first metal layer 105 are stacked.

As shown in FIG. 9D, the second photoresist pattern 106 having a relatively low height in the channel portion is removed by an ashing process and then the source / drain electrode forming metal of the channel portion is subjected to a dry etching process. The pattern 105a and the ohmic contact layer 104a are etched. As a result, the active layer 103a of the channel portion is exposed, and the metal pattern 105a is electrically separated from the active layer 103a to form the source electrode 107a and the drain electrode 107b. The data line 107 is formed to define a pixel area orthogonal to the gate line 101. In this case, the data line 107 overlaps one region of the upper and lower portions of the first and second repair lines 101b and 101c (refer to FIG. 6). This area is for welding and repairing when opened.

Subsequently, the second photoresist pattern 106 remaining on the source / drain pattern portion is removed by a stripping process.

By the above process, a thin film transistor (TFT) including a gate electrode 101a, an active layer 103a, a source electrode 107a, and a drain electrode 107b is formed.

Next, as shown in FIG. 9E, a protective film 108 is formed on the entire surface of the first substrate 100 including the thin film transistor (TFT) by a deposition method such as PECVD, and a photoresist is applied on the protective film 108. do.

The photoresist is selectively patterned by an exposure and development process using a third mask to form a third photoresist pattern 109. Thereafter, the protective film 108 is etched using the third photoresist pattern 109 as a mask to form the first contact hole 110 in one region of the drain electrode 107b.

As the material of the protective film 108, an inorganic insulating material such as the gate insulating film 102 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB may be used.

Subsequently, as illustrated in FIG. 9F, a transparent conductive film 111 is deposited on the entire surface of the first substrate 100, a photoresist is applied on the transparent conductive film 111, and then a fourth mask is used. The fourth photoresist pattern 112 is formed so as to remain only in the pixel region.

Thereafter, as illustrated in FIG. 9G, the transparent conductive film 111 is etched using the fourth photoresist pattern 112 as a mask to form the pixel electrode 111a in the pixel region. In this case, the pixel electrode 111a is formed to overlap the first or second repair lines 101b and 101c formed in the adjacent pixel region. The pixel electrode 111a extends to the upper portion of the previous gate line 101d.

The transparent conductive film 111 may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). ) Can be used.

In the above, the active layer 103a is composed of the data line 107, the source and drain electrodes 107a and 107b, and the channel region, and a manufacturing method thereof is illustrated. However, the active layer 103a may be formed only in the channel region. Accordingly, the amorphous silicon layer may be patterned once using a mask without a diffraction exposure mask.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the above embodiments, but should be defined by the claims.

The liquid crystal display according to the present invention as described above and a manufacturing method thereof have the following effects.

By configuring the first and second repair lines to be symmetrical under both sides of the data line, ΔVp can be minimized, and the repair can be efficiently performed without a vertical band defect even if the data line is shifted left and right during the repair process due to the data line open failure. You can proceed.

Claims (9)

A first substrate and a second substrate facing each other; A plurality of gate lines and data lines crossing each other on the first substrate to define pixel regions; A thin film transistor formed at an intersection of the gate lines and the data lines; A pixel electrode formed in the pixel region; And first and second repair lines formed to be symmetrically formed under both sides of the data line. The method of claim 1, And the first and second repair lines are formed to overlap the data lines at upper and lower portions of the first and second repair lines, respectively. The method of claim 1, And the first and second repair lines are formed on the same layer as the gate lines. The method of claim 2, And a portion of an upper portion and a lower portion of the first and second repair lines overlapping the data line is shorted with the data line to form two data signal movement paths when the data line is opened. The method of claim 1, And the pixel electrode partially overlaps the adjacent first and second repair lines. Forming a gate line and a gate electrode on the substrate; A second step of forming first and second repair lines symmetrically formed in a direction orthogonal to the gate lines; A data line disposed between the gate line and horizontally to define a pixel area, and the first and second repair lines are symmetrical, a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode; Forming a third step; And forming a pixel electrode in the pixel region. The method of claim 6, And the first and second repair lines protrude in a direction in which upper and lower portions face each other, and the protruding portions overlap with the data lines. The method of claim 6, And the first and second repair lines are formed on the same layer as the gate lines. The method of claim 6, And the pixel electrode overlaps with the first or second repair line formed in an adjacent pixel region.

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