KR20070069552A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device and a method for manufacturing the same are provided to prevent the damage of a low voltage transistor while applying a negative voltage to a high voltage transistor by surrounding a second well region using an additional deep well region. A substrate(110) having a high voltage transistor region(H) and a low voltage transistor region(L) is prepared. A deep well region(115) is formed in the substrate of the low voltage transistor region. A first well region(120a) is formed in the substrate of the high voltage transistor region. A second well region(120b) is then formed in the deep well region of the low voltage transistor region.

Description

Semiconductor device and its manufacturing method {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a cross-sectional view illustrating a semiconductor device for implementing a high voltage device and a low voltage device having a DDD structure on a single chip according to the related art.

2 is a cross-sectional view illustrating a semiconductor device implementing high voltage transistors and low voltage transistors on a single chip in accordance with an embodiment of the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

110: substrate

111: screen oxide film

112, 116, 118: photoresist pattern

113, 117, 119: ion implantation process

115: deep well area

120a, 120b: N well area

120c, 120d: P well area

121: P ^- drift region

122: field oxide film

123a and 123b: gate oxide film

124: polysilicon film

125a: high voltage gate electrode

125b: low voltage gate electrode

126: spacer

127a and 127b: source / drain regions

128: N ⁺ junction area

H: first region L: second region

P ₁ : first PMOS region P ₂ : second PMOS region

N ₁ : first NMOS region N ₂ : second NMOS region

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device for implementing a high voltage device and a low voltage device on a single chip, and a method of manufacturing the same.

In the semiconductor integrated circuit, a high voltage control element (or a high voltage element) to which a high voltage is directly applied is formed to directly control an external system using a high voltage. Such high voltage devices are also required in circuits that require high breakdown voltage (BV).

CMOS devices with low power consumption are widely used as high voltage devices. The CMOS device is composed of a P-type MOS (PMOS) transistor and an N-type (MOS) transistor, each transistor having a source region and a drain region below the source region and the drain region to obtain a high breakdown voltage. It has the same conductivity type as the drain region and has a double diffusion drain (hereinafter referred to as DDD) structure having a low concentration region.

1 is a cross-sectional view illustrating a semiconductor device for implementing a high voltage device and a low voltage device having a DDD structure in a single chip according to the related art. For convenience of explanation, a high voltage PMOS transistor and a low voltage PMOS transistor controlled by a high voltage of 20V will be described here.

Referring to FIG. 1, a semiconductor device according to the related art includes N wells NWELL in a substrate 10 defined as a first region H in which a high voltage transistor is to be formed and a second region L in which a low voltage transistor is to be formed; 11a and 11b are formed, and a P ⁻ drift region 12 is formed in a portion of the N well 11a of the first region H. On the substrate 10 having the N wells 11a and 11b and the drift region 12, the high voltage gate gate electrode 17a having spacers 18 on both side walls of each region H and L, and The low voltage gate electrode 17b is formed.

On the other hand, in the N wells 11a and 11b exposed to both sides of the high voltage gate electrode 17a and the low voltage gate electrode 17b, the first source / drain region 19a of the high voltage transistor and the second source / of the low voltage transistor, respectively. A drain region 19b is formed, and an N ⁺ junction region 20 to be connected to a body pad for applying a voltage to the N well 11a is further formed in the first region H.

In FIG. 1, reference numeral 13 denotes a field oxide film having a LOCOS structure, '14a' and '14b' represent a high voltage gate oxide film and a low voltage gate oxide film, respectively, and '15' is a polysilicon film. In general, the high voltage gate oxide film 14a and the low voltage gate oxide film 14b have different thicknesses in view of their threshold voltage characteristics. Preferably, the high voltage gate oxide film 14a is thicker than the low voltage gate oxide film 14b.

In the above-described prior art, in order to implement a high voltage transistor and a low voltage transistor on one chip, N wells 11a and 11b are formed in the first and second regions H and L, respectively, through a single well ion implantation process. . However, only a positive high voltage, for example, + 20V can be applied to the input terminal of the high voltage transistor thus formed. If a reverse bias, for example, -20V is applied, isolation from the low voltage transistor is poor, which may cause a large damage to the low voltage transistor.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and in a semiconductor device including a high voltage device, a semiconductor capable of operating stably even when a negative voltage (-) is applied to an input terminal of the high voltage device. An object thereof is to provide a device and a method of manufacturing the same.

According to an aspect of the present invention, a substrate is defined as a first region in which a high voltage transistor is to be formed and a second region in which a low voltage transistor is to be formed, and the first and second regions are electrically isolated from each other. The semiconductor device includes a deep well region formed in the substrate of the second region, a first well region formed in the substrate of the first region, and a second well region formed in the deep well region of the second region. do.

In addition, according to another aspect of the present invention, there is provided a substrate including a first region in which a high voltage transistor is to be formed and a second region in which a low voltage transistor is to be formed, and the substrate in the second region. Forming a deep well region in the deep well region; and forming a first well region in the substrate of the first region and simultaneously forming a second well region in the deep well region.

In one aspect of the invention, the deep well region is formed at a lower concentration than the second well region, it is formed in an N-type. The first and second well regions are formed in the same conductivity type as each other.

That is, according to the present invention described above, in order to electrically isolate the first region where the high voltage transistor is to be formed and the second region where the low voltage transistor is to be formed from each other, the well region at a lower concentration than the well region formed in the substrate of the second region. By forming a deep well region having a structure surrounding the structure, it is possible to prevent damage to the low voltage transistor even when a negative voltage (−) is applied to the high voltage transistor. This is because electrons transferred from the first region to the second region are dispersed in the low concentration deep well region when a negative voltage is applied to the high voltage transistor.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

2 is a cross-sectional view illustrating a semiconductor device in which a high voltage transistor and a low voltage transistor are implemented on one chip according to an embodiment of the present invention. Here, for convenience of description, a semiconductor device in which a high voltage PMOS transistor and a low voltage PMOS transistor controlled by a high voltage of 20V are implemented on one chip will be described as an example. That is, the embodiment of the present invention can also be applied to an NMOS transistor.

Referring to FIG. 2, a semiconductor device according to an embodiment of the present invention may be formed of a substrate formed in a substrate 110 defined as a first region H in which a high voltage transistor is to be formed and a second region L in which a low voltage transistor is to be formed. The second region L to surround the first and second N well regions 120a and 120b and the second N well regions 120b to electrically isolate the first and second N well regions 120a and 120b from each other. Deep well region (DWELL) 115 formed in the substrate 110.

In particular, the deep well region 115 is formed at a lower concentration than the second N well region 120b and is N-shaped. In addition, the substrate 110 may be doped with a P or N type.

As described above, in the exemplary embodiment of the present invention, the first and second N well regions 120a and 120b formed in the substrate 110 of the first and second regions H and L, respectively, in which the high voltage and low voltage transistors are to be formed, are mutually different. By forming the deep well region 115 having a structure surrounding the second N well region 120b at a lower concentration than the second N well region 120b to electrically isolate the second N well region 120b, even when a negative high voltage is applied to the high voltage transistor, The well region 120b may not be affected.

Therefore, even if a negative high voltage, for example, a high voltage of -20V is applied to the high voltage transistor, the low voltage transistor is not damaged. This is because electrons transferred from the first region H to the second region L are dispersed in the low concentration deep well region 115 when a negative high voltage is applied to the high voltage transistor.

In addition, the semiconductor device according to the embodiment of the present invention includes a spacer 126 on both side walls and a high voltage gate electrode 125a and a low voltage formed on the substrate 110 in the first and second regions H and L, respectively. First and second source / drain regions formed in the gate electrode 125b and the first and second N well regions 120a and 120b respectively exposed to both sides of the high voltage gate electrode 125a and the low voltage gate electrode 125b. 127a, 127b is further included.

In particular, the P ⁻ drift region 121 formed to surround the first drain region 127a is present in the first N well region 120a formed to form the high voltage transistor. Thus, a high voltage PMOS transistor having a DDD structure is completed.

The high voltage gate electrode 125a and the low voltage gate electrode 125b have a stacked structure of the gate oxide films 123a and 123b and the polysilicon film 124, respectively, wherein the gate oxide film 123a is a high voltage gate oxide film of the high voltage transistor ( 123a is formed thicker than the low-voltage gate oxide film 123b of the low-voltage transistor. This is because the threshold voltage of the high voltage transistor is higher than the threshold voltage of the low voltage transistor.

In FIG. 2, reference numeral 128 denotes an N ⁺ junction region connected to a body pad to be formed to apply a high voltage in the first N well region 120a of the high voltage transistor.

3A through 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. Here, as an example, a method of manufacturing a CMOS semiconductor device in which high voltage and low voltage transistors are implemented in one chip will be described.

First, as shown in FIG. 3A, a substrate 110 is defined as a first region H in which a high voltage transistor is to be formed and a second region L in which a low voltage transistor is to be formed. Here, the substrate 110 may be doped with a P or N type.

Subsequently, an oxidation process is performed on the substrate 110 to form a screen oxide 111. The screen oxide layer 111 prevents the exposed upper surface of the substrate 110 from being damaged during a diffusion process (or ion implantation process) for forming subsequent well and drift regions. In this case, the screen oxide film 111 is formed of a silicon oxide film (SiO ₂ ) using a wet or dry oxidation process. For example, it is formed by a thermal oxidation process using O ₂ gas.

Subsequently, after the photoresist (not shown) is coated on the screen oxide film 111, an exposure and development process using a photomask (not shown) is performed to form the photoresist pattern 112. Here, the photoresist pattern 112 is used to define the deep well region, and has a structure in which the second region L is opened.

Next, an ion implantation process 113 using the photoresist pattern 112 as a mask is performed to implant impurity ions. For example, impurity ions such as phosphorus (P) or arsenic (As), which are a Group 5 material, are implanted to form an N-type. Here, the ion implantation process 113 is formed at a lower concentration than the well region to be formed in the second region L through a subsequent process.

Subsequently, as illustrated in FIG. 3B, a drive-in process is performed to diffuse the impurity ions to form the deep well region DWELL 115 in the substrate 110 of the second region L. Referring to FIG. .

Subsequently, a strip process is performed to remove the photoresist pattern 112 (see FIG. 3A).

Subsequently, as shown in FIG. 3C, a photomask process is performed to form the photoresist pattern 116 on the screen oxide film 111. Here, the photoresist pattern 116 is to define first and second NMOS regions N ₁ and N ₂ in which NMOS transistors are to be formed in the first and second regions H and L, respectively.

Subsequently, an ion implantation process 117 using the photoresist pattern 116 as a mask is performed to form the substrate 110 of the first NMOS region N ₁ and the deep well region 115 of the second NMOS region N ₂ . Impurity ions are implanted, respectively. For example, impurity ions such as phosphorus (P) or arsenic (As), which are a Group 5 material, are implanted.

Subsequently, as shown in FIG. 3D, a strip process is performed to remove the photoresist pattern 116 (see FIG. 3C).

Next, a photoresist pattern 118 is formed on the screen oxide film 111 by performing a photo mask process. Here, the photoresist pattern 118 is to define first and second PMOS regions P ₁ and P ₂ in which PMOS transistors are to be formed in the first and second regions H and L, respectively.

Subsequently, an ion implantation process 119 using the photoresist pattern 118 as a mask is performed to form the substrate 110 of the first PMOS region N ₁ and the deep well region 115 of the second PMOS region N ₂ . Impurity ions are implanted, respectively. For example, impurity ions such as boron (B), which is a group 3 material, are implanted.

Subsequently, as shown in FIG. 3E, a strip process is performed to remove the photoresist pattern 118 (see FIG. 3D).

Subsequently, a drive-in process is performed to the first and second PMOS regions P ₁ and P ₂ and the first and second NMOS regions N ₁ and N ₂ in the first and second regions H and L. Each implanted impurity ion is diffused. Accordingly, the first and second N wells 120a and 120b and the first and second PMOS regions P ₁ and P ₂ and the first and second NMOS regions N ₁ and N ₂ , respectively. Two P wells 120c and 120d are formed. Preferably, the second P well 120d and the second N well 120b are formed in the deep well region 115.

Subsequently, a wet etching process is performed to remove the screen oxide film 111 (see FIG. 3D). In this case, the screen oxide layer 111 is selectively removed within a range in which the upper surface of the substrate 110 is not damaged by adjusting the process time of the wet etching process.

Subsequently, the gate electrode and the source / drain type success determination are performed according to a method of manufacturing a CMOS semiconductor device in which a typical high voltage transistor and a low voltage transistor are implemented in one chip.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the second well region is enclosed to electrically isolate the first and second well regions formed in the substrate of the first and second regions where the high voltage and low voltage transistors are to be formed, respectively. By forming the deep well region of the structure separately, electrons transferred from the first region to the second region may be dispersed in the deep well region when a negative voltage (−) is applied to the high voltage transistor.

Therefore, even if a negative voltage (-) is applied to the high voltage transistor, the low voltage transistor is not damaged. Through this, it is possible to apply both +/- high voltage to the high voltage transistor, thereby extending the application range of the semiconductor device requiring the high voltage transistor.

Claims (9)

A substrate defined by a first region where a high voltage transistor is to be formed and a second region where a low voltage transistor is to be formed; A deep well region formed in the substrate of the second region to electrically isolate the first and second regions from each other; A first well region formed in the substrate of the first region; And A second well region formed in the deep well region of the second region Semiconductor device comprising a. The method of claim 1, The deep well region is formed at a lower concentration than the second well region. The method of claim 2, The deep well region is a semiconductor device formed in the N-type. The method according to any one of claims 1 to 3, And the first and second well regions are formed in the same conductivity type as each other. The method of claim 4, wherein A high voltage gate electrode and a low voltage gate electrode formed on the substrate in the first and second regions; First and second source / drain regions respectively formed in the first and second well regions exposed to both sides of the high and low voltage gate electrodes; And A drift region formed locally to surround the first source / drain region in the first well region A semiconductor device further comprising. Providing a substrate defined by a first region where a high voltage transistor is to be formed and a second region where a low voltage transistor is to be formed; Forming a deep well region in the substrate of the second region; And Forming a first well region in the substrate of the first region and simultaneously forming a second well region in the deep well region Semiconductor device manufacturing method comprising a. The method of claim 6, And forming the deep well region at a lower concentration than the second well region. The method of claim 7, wherein And forming the first and second well regions in the same conductivity type as each other. The method according to any one of claims 6 to 8, wherein after forming the second well region, Forming a drift region locally in the first well region; Forming a high voltage gate electrode and a low voltage gate electrode on the substrate in the first and second regions, respectively; And A second source / drain region is formed in the first well region and the drift region respectively exposed to both sides of the high voltage gate electrode, and a second source / drain region is formed in the second well region exposed to both sides of the low voltage gate electrode. Forming steps Semiconductor device manufacturing method further comprising.

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