KR20070068802A - Method of fabricating the conductive contact in semiconductor device - Google Patents

Method of fabricating the conductive contact in semiconductor device Download PDF

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KR20070068802A
KR20070068802A KR1020050130806A KR20050130806A KR20070068802A KR 20070068802 A KR20070068802 A KR 20070068802A KR 1020050130806 A KR1020050130806 A KR 1020050130806A KR 20050130806 A KR20050130806 A KR 20050130806A KR 20070068802 A KR20070068802 A KR 20070068802A
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contact hole
film
conductive
contact
forming
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KR1020050130806A
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Korean (ko)
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KR100750801B1 (en
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석가문
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for forming a conductive contact of a semiconductor device is provided to restrain the increase of resistance of the conductive contact by removing polymers from a contact hole using an oxygen plasma treatment. A lower conductive layer(220) and an insulating layer(230) are formed on a semiconductor substrate(200). A contact hole(232) for exposing partially the lower conductive layer to the outside is formed on the resultant structure by removing selectively the insulating layer. An oxygen plasma treatment is performed on the resultant structure in order to remove polymers(300) from the contact hole. A barrier metal is formed along an upper surface of the resultant structure. A conductive contact for filling the contact hole is formed on the barrier metal.

Description

반도체소자의 도전성컨택 형성방법{method of fabricating the conductive contact in semiconductor device}Method of fabricating the conductive contact in semiconductor device

도 1은 종래의 반도체소자의 도전성컨택 형성방법을 설명하기 위하여 나타내 보인 단면도이다.1 is a cross-sectional view illustrating a conventional method for forming a conductive contact of a semiconductor device.

도 2 및 도 3은 본 발명에 따른 반도체소자의 도전성컨택 형성방법을 설명하기 위하여 나타내 보인 단면도들이다.2 and 3 are cross-sectional views illustrating a method of forming a conductive contact of a semiconductor device according to the present invention.

본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 반도체소자의 도전성컨택 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a conductive contact of a semiconductor device.

일반적으로 반도체소자를 제조하는데 있어서, 하부도전막과 상부도전막은 도전성컨택을 통해 전기적으로 연결된다. 이를 위해 층간절연막을 관통하여 하부도전막의 일부표면을 노출시키는 컨택홀(contact hole)을 형성한 후, 컨택홀이 형성된 결과물 전면에 도전막을 적층하여 도전성컨택을 형성한다. 하부금속막과 상부금속막을 전기적으로 연결하기 위해서는 금속간절연막을 관통하여 하부금속막의 일부표면을 노출시키는 비아홀(via hole)을 형성한 후, 비아홀이 형성된 결과물 전면에 도전막을 적층하여 도전성컨택을 형성한다.In general, in manufacturing a semiconductor device, the lower conductive film and the upper conductive film are electrically connected through conductive contacts. To this end, a contact hole is formed through the interlayer insulating film to expose a part of the lower conductive film, and then a conductive film is formed on the entire surface of the resultant contact hole to form a conductive contact. In order to electrically connect the lower metal film and the upper metal film, a via hole is formed through the intermetallic insulating film to expose a portion of the lower metal film, and then a conductive film is formed on the entire surface of the resultant via hole to form a conductive contact. do.

도 1은 종래의 반도체소자의 도전성컨택 형성방법을 설명하기 위하여 나타내 보인 단면도이다.1 is a cross-sectional view illustrating a conventional method for forming a conductive contact of a semiconductor device.

도 1을 참조하면, 반도체기판(100) 위의 하부도전막(120)상에 층간절연막(130)을 형성한다. 반도체기판(100)과 하부도전막(120) 사이에는 절연막(110)이 배치된다. 하부도전막(120)은 금속막일 수 있다. 다음에 층간절연막(130)의 일부를 제거하여 하부도전막(120)의 일부표면을 노출시키는 컨택홀(132)을 형성한다. 하부도전막(120)이 금속막일 경우, 컨택홀(132)을 비아홀이라고 하기도 한다. 다음에 수분제거를 위한 디개스(degas)공정을 진행하고, 도전성물질의 갭필(gap fill)능력을 증대시키기 위하여 아르곤(Ar)과 RF 파워를 이용한 스퍼터 에치(sputter etch)를 수행하여 컨택홀(132)의 상부 면적을 증가시킨다. 다음에 전면에 장벽금속막(140)을, 예컨대 Ti/TiN막으로 형성하고, 이어서 도전성물질로 컨택홀(132)을 채워서 도전성컨택(150)을 형성한다.Referring to FIG. 1, an interlayer insulating layer 130 is formed on the lower conductive layer 120 on the semiconductor substrate 100. An insulating layer 110 is disposed between the semiconductor substrate 100 and the lower conductive layer 120. The lower conductive layer 120 may be a metal layer. Next, a part of the interlayer insulating film 130 is removed to form a contact hole 132 exposing a portion of the lower conductive film 120. When the lower conductive layer 120 is a metal layer, the contact hole 132 may be referred to as a via hole. Next, a degas process for water removal is performed, and a sputter etch using argon (Ar) and RF power is performed to increase the gap fill capability of the conductive material. 132 increases the top area. Next, a barrier metal film 140 is formed on the entire surface, for example, a Ti / TiN film, and then the conductive contact 150 is formed by filling the contact hole 132 with a conductive material.

그런데 이와 같이 도전성컨택(150)을 형성하는데 있어서, 컨택홀(132) 형성을 위한 식각시 발생한 폴리머(polymer)들이 남아 있을 수 있으며, 이 상태에서 도전성물질, 예컨대 텅스텐(W)이 채워지는 경우, 컨택홀(132) 내에 잔존하는 폴리머에 의해 도전성컨택(150)의 단면적이 작아지게 된다. 도전성컨택(150)의 단면적이 작아지게 되면, 저항이 증가하며, 따라서 소자의 성능이 열화 된다.However, in forming the conductive contact 150 as described above, polymers generated during the etching for forming the contact hole 132 may remain, and in this state, when the conductive material, for example, tungsten (W) is filled, The cross-sectional area of the conductive contact 150 is reduced by the polymer remaining in the contact hole 132. As the cross-sectional area of the conductive contact 150 becomes smaller, the resistance increases, thus degrading the performance of the device.

본 발명이 이루고자 하는 기술적 과제는, 컨택홀 내의 폴리머를 제거하여 도 전성컨택의 저항증가가 억제되도록 하는 반도체소자의 도전성컨택 형성방법을 제공하는 것이다.An object of the present invention is to provide a method for forming a conductive contact of a semiconductor device to remove the polymer in the contact hole to suppress the increase in resistance of the conductive contact.

상기 기술적 과제를 달성하기 위하여, 본 발명에 따른 반도체소자의 도전성컨택 형성방법은, 반도체기판 위의 하부도전막 위에 절연막을 형성하는 단계, 상기 절연막의 일부를 제거하여 상기 하부도전막의 일부표면을 노출시키는 컨택홀을 형성하는 단계, 상기 컨택홀이 형성된 결과물에 대한 산소플라즈마 처리를 수행하여 상기 컨택홀 내에 잔존해있는 폴리머를 제거하는 단계, 상기 산소플라즈마 처리가 이루어진 결과물 전면에 장벽금속층을 형성하는 단계 및 상기 장벽금속층 위에 상기 컨택홀이 매립되도록 도전성물질을 증착하여 도전성컨택을 형성하는 단계를 포함한다.In order to achieve the above technical problem, the method for forming a conductive contact of the semiconductor device according to the present invention, forming an insulating film on the lower conductive film on the semiconductor substrate, by removing a portion of the insulating film to expose a portion of the lower conductive film Forming a contact hole to remove the polymer remaining in the contact hole by performing an oxygen plasma treatment on the resultant product on which the contact hole is formed, and forming a barrier metal layer on the entire surface of the resultant product subjected to the oxygen plasma treatment. And depositing a conductive material on the barrier metal layer to form a conductive contact.

상기 하부도전막은 금속막을 포함할 수 있다.The lower conductive layer may include a metal layer.

상기 장벽금속층은 Ti/TiN막을 포함하고, 상기 도전성물질은 텅스텐(W)막을 포함할 수 있다.The barrier metal layer may include a Ti / TiN film, and the conductive material may include a tungsten (W) film.

상기 산소플라즈마 처리는, 상기 컨택홀이 형성된 반도체기판을 챔버에 로딩하는 단계, 상기 반도체기판이 로딩된 챔버 내에 산소 및 아르곤을 공급하는 단계, 상기 챔버에 플라즈마 파워를 인가하여 플라즈마가 형성되도록 하는 단계 및 상기 챔버에 바이어스 파워를 인가하여 산소이온이 상기 컨택홀 내의 폴리머와 반응하도록 하는 단계를 포함할 수 있다.The oxygen plasma treatment may include loading the semiconductor substrate on which the contact hole is formed into a chamber, supplying oxygen and argon into the chamber loaded with the semiconductor substrate, and applying plasma power to the chamber to form a plasma. And applying a bias power to the chamber to allow oxygen ions to react with the polymer in the contact hole.

이 경우, 상기 산소 및 아르곤의 공급량은 10-30sccm이 되도록 하고, 상기 플라즈마 파워 및 바이어스 파워는 150W 이상이 되도록 하는 것이 바람직하다.In this case, it is preferable that the supply amount of oxygen and argon is 10-30 sccm, and the plasma power and the bias power are 150 W or more.

이하 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안된다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

도 2 및 도 3은 본 발명에 따른 반도체소자의 도전성컨택 형성방법을 설명하기 위하여 나타내 보인 단면도들이다.2 and 3 are cross-sectional views illustrating a method of forming a conductive contact of a semiconductor device according to the present invention.

먼저 도 2를 참조하면, 반도체기판(200) 위의 하부도전막(220)상에 층간절연막(230)을 형성한다. 반도체기판(200)과 하부도전막(220) 사이에는 절연막(210)이 배치된다. 비록 도면에 나타내지는 않았지만, 반도체기판(200)에는 다양한 능동 및/또는 수동소자들이 배치될 수 있으며, 이 경우 하부도전막(220)은 불순물영역이나 또는 다른 도전막과 전기적으로 연결된다. 하부도전막(220)은 금속배선막일 수도 있다.First, referring to FIG. 2, an interlayer insulating film 230 is formed on the lower conductive film 220 on the semiconductor substrate 200. An insulating layer 210 is disposed between the semiconductor substrate 200 and the lower conductive layer 220. Although not shown, various active and / or passive devices may be disposed on the semiconductor substrate 200, and in this case, the lower conductive film 220 is electrically connected to an impurity region or another conductive film. The lower conductive film 220 may be a metal wiring film.

층간절연막(230)을 형성한 후, 소정의 마스크막패턴, 예컨대 포토레지스트막패턴을 이용한 식각으로, 층간절연막(230)의 일부를 제거하여 하부도전막(220)의 일부표면을 노출시키는 컨택홀(232)을 형성한다. 본 실시예에서는 컨택홀(232)의 경우를 예를 들었지만, 하부도전막(220)이 금속배선막인 경우 비아홀의 경우에도 동일하게 적용된다는 것은 당연하다. 다음에 식각후의 통상의 세정공정과 웨이퍼 표면에 흡습된 수분을 제거를 위한 디개스(degas)공정을 진행한다. 그리고 도면에서 화살표로 나타낸 바와 같이, 컨택홀(232) 내에 남아있는 폴리머(300)를 제거하 기 위한 산소플라즈마(O2 plasma) 처리를 수행한다.After the interlayer insulating film 230 is formed, a contact hole for exposing a part of the lower conductive film 220 by removing a portion of the interlayer insulating film 230 by etching using a predetermined mask film pattern, for example, a photoresist film pattern. Form 232. In the present embodiment, the case of the contact hole 232 is taken as an example, but it is obvious that the same applies to the case of the via hole when the lower conductive film 220 is a metal wiring film. Next, a normal cleaning process after etching and a degas process for removing moisture absorbed on the wafer surface are performed. And, as shown by the arrow in the figure, the oxygen plasma (O 2 plasma) treatment to remove the polymer 300 remaining in the contact hole 232 is performed.

구체적으로 산소플라즈마 처리를 수행하기 위하여, 먼저 컨택홀(232)이 형성된 반도체기판(200)을 챔버 내에 로딩시킨다. 그리고 챔버 내에 산소(O2)가스 및 아르곤(Ar)가스를 공급한다. 산소(O2)가스의 공급량은 대략 10-30sccm이 되도록 하고, 아르곤(Ar)가스의 공급량도 대략 10-30sccm이 되도록 한다. 다음에 플라즈마 파워를 대략 150W 이상 인가하여 챔버 내에 플라즈마가 발생되도록 한다. 플라즈마가 발생되면 반도체기판(200)이 안착되는 지지대(pedestal)쪽에 대략 150W 이상의 바이어스 파워를 인가하여, 플라즈마 상태의 산소(O2)가스가 컨택홀(232) 내의 폴리머(300)와 반응하여 폴리머(300)가 제거되도록 한다.Specifically, in order to perform the oxygen plasma treatment, first, the semiconductor substrate 200 on which the contact holes 232 are formed is loaded into the chamber. Oxygen (O 2 ) gas and argon (Ar) gas are supplied into the chamber. The supply amount of oxygen (O 2 ) gas is approximately 10-30 sccm, and the supply amount of argon (Ar) gas is approximately 10-30 sccm. Next, approximately 150 W or more of plasma power is applied to generate plasma in the chamber. When the plasma is generated, a bias power of about 150 W or more is applied to the pedestal side on which the semiconductor substrate 200 is seated, so that the oxygen (O 2 ) gas in the plasma state reacts with the polymer 300 in the contact hole 232 to form a polymer. Allow 300 to be removed.

다음에 아르곤(Ar)과 RF 파워를 이용한 스퍼터 에치(sputter etch)를 수행하여 컨택홀(232)의 상부 면적을 증가시킨다. 비록 도면에 나타내지는 않았지만, 스퍼터 에치에 의해 컨택홀(232) 상부 면적이 다소 증가됨에 따라, 후속의 매립공정에서 도전성물질의 갭필(gap fill) 능력이 증대된다. Next, a sputter etch using argon (Ar) and RF power is performed to increase the upper area of the contact hole 232. Although not shown in the drawing, as the upper area of the contact hole 232 is slightly increased by the sputter etch, the gap fill capability of the conductive material is increased in the subsequent filling process.

다음에 도 3을 참조하면, 전면에 장벽금속막(240)을, 예컨대 Ti/TiN막으로 형성한다. 특히 Ti막은 후속의 열처리에 의해 하부도전막(220)과 반응하여 그 경계면에 티타늄실리사이드(TiSix)막이 형성되도록 한다. 그리고 TiN막은 후속의 도전성물질로 텅스텐(W)을 증착할 때, 반응가스인 WF6가스로부터 발생하는 플로린(F)성분에 의한 영향을 받지 않도록 한다. 이와 같은 TiN막은 스퍼터링(sputtering)방법을 사용하여 형성할 수도 있고, 또는 화학기상증착(CVD; Chemical Vapor Deposition)방법을 사용하여 형성할 수도 있다. 장벽금속층(240)을 형성한 후에는, 텅스텐(W)과 같은 도전성물질로 컨택홀(232)을 채워서 도전성컨택(250)을 형성한다.Next, referring to FIG. 3, a barrier metal film 240 is formed on the entire surface, for example, a Ti / TiN film. In particular, the Ti film reacts with the lower conductive film 220 by subsequent heat treatment to form a titanium silicide (TiSi x ) film on its interface. In addition, the TiN film is prevented from being influenced by the fluorine (F) component generated from the reaction gas, WF 6 gas, when depositing tungsten (W) with a subsequent conductive material. Such a TiN film may be formed using a sputtering method, or may be formed using a chemical vapor deposition (CVD) method. After the barrier metal layer 240 is formed, the conductive contact 250 is formed by filling the contact hole 232 with a conductive material such as tungsten (W).

지금까지 설명한 바와 같이, 본 발명에 따른 반도체소자의 도전성컨택 형성방법에 의하면, 컨택홀(비아홀) 형성을 위한 식각 수행 후, 산소플라즈마 처리를 수행하여 컨택홀(비아홀) 내부의 폴리머가 제거되도록 함으로써, 폴리머로 인한 도전성컨택의 단면적 감소현상이 발생하지 않게 되며, 이에 따라 도전성컨택의 저항감소를 방지할 수 있다는 이점이 제공된다.As described above, according to the method for forming a conductive contact of a semiconductor device according to the present invention, after etching to form a contact hole (via hole), an oxygen plasma treatment is performed to remove the polymer inside the contact hole (via hole). In addition, the reduction of the cross-sectional area of the conductive contact due to the polymer does not occur, thereby providing an advantage of preventing the reduction of the resistance of the conductive contact.

이상 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않으며, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능함은 당연하다.Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

Claims (5)

반도체기판 위의 하부도전막 위에 절연막을 형성하는 단계,Forming an insulating film on the lower conductive film on the semiconductor substrate, 상기 절연막의 일부를 제거하여 상기 하부도전막의 일부표면을 노출시키는 컨택홀을 형성하는 단계,Removing a portion of the insulating layer to form a contact hole exposing a portion of the lower conductive layer; 상기 컨택홀이 형성된 결과물에 대한 산소플라즈마 처리를 수행하여 상기 컨택홀 내에 잔존해있는 폴리머를 제거하는 단계,Removing the polymer remaining in the contact hole by performing oxygen plasma treatment on the resultant in which the contact hole is formed; 상기 산소플라즈마 처리가 이루어진 결과물 전면에 장벽금속층을 형성하는 단계 및 Forming a barrier metal layer on the entire surface of the resultant product subjected to the oxygen plasma treatment; 상기 장벽금속층 위에 상기 컨택홀이 매립되도록 도전성물질을 증착하여 도전성컨택을 형성하는 단계를 포함하는 반도체소자의 도전성컨택 형성방법.And forming a conductive contact by depositing a conductive material on the barrier metal layer so as to fill the contact hole. 제1항에서,In claim 1, 상기 하부도전막은 금속막을 포함하는 반도체소자의 도전성컨택 형성방법.The lower conductive film is a conductive contact forming method of a semiconductor device comprising a metal film. 제1항에서,In claim 1, 상기 장벽금속층은 Ti/TiN막을 포함하고, 상기 도전성물질은 텅스텐(W)막을 포함하는 반도체소자의 도전성컨택 형성방법.The barrier metal layer includes a Ti / TiN film, and the conductive material includes a tungsten (W) film. 제1항에서, In claim 1, 상기 산소플라즈마 처리는,The oxygen plasma treatment, 상기 컨택홀이 형성된 반도체기판을 챔버에 로딩하는 단계, Loading the semiconductor substrate on which the contact hole is formed into a chamber; 상기 반도체기판이 로딩된 챔버 내에 산소 및 아르곤을 공급하는 단계,Supplying oxygen and argon into the chamber loaded with the semiconductor substrate, 상기 챔버에 플라즈마 파워를 인가하여 플라즈마가 형성되도록 하는 단계 및Applying plasma power to the chamber to form a plasma; and 상기 챔버에 바이어스 파워를 인가하여 산소이온이 상기 컨택홀 내의 폴리머와 반응하도록 하는 단계를 포함하는 반도체소자의 도전성컨택 형성방법.Applying a bias power to the chamber to cause oxygen ions to react with the polymer in the contact hole. 제4항에서,In claim 4, 상기 산소 및 아르곤의 공급량은 10-30sccm이 되도록 하고, 상기 플라즈마 파워 및 바이어스 파워는 150W 이상이 되도록 하는 반도체소자의 도전성컨택 형성방법.And the supply amount of oxygen and argon is 10-30 sccm, and the plasma power and bias power are 150W or more.
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