KR100900226B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR100900226B1 KR100900226B1 KR1020060123515A KR20060123515A KR100900226B1 KR 100900226 B1 KR100900226 B1 KR 100900226B1 KR 1020060123515 A KR1020060123515 A KR 1020060123515A KR 20060123515 A KR20060123515 A KR 20060123515A KR 100900226 B1 KR100900226 B1 KR 100900226B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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Abstract
반도체 소자의 제조방법은, 반도체 기판 상에 카본 성분을 함유한 저유전막을 형성하는 단계; 상기 저유전막을 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀 표면에 발생된 잔류물을 제거하는 단계; 및 상기 콘택홀을 매립하도록 저유전막 상에 금속막을 형성하는 단계;를 포함한다.A method of manufacturing a semiconductor device includes forming a low dielectric film containing a carbon component on a semiconductor substrate; Etching the low dielectric layer to form a contact hole; Removing residues generated on the contact hole surface; And forming a metal film on the low dielectric film to fill the contact hole.
Description
도 1a 내지 도 1f는 본 발명의 일실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.1A to 1F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100 : 반도체 기판 102 : 하부 금속배선100
104 : 저유전막 H : 콘택홀 104: low dielectric film H: contact hole
S : 잔류물 106 : 금속막 S: residue 106: metal film
108 : 상부 금속배선108: upper metal wiring
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 카본 성분을 함유한 저유전막을 적용한 금속배선의 형성시 콘택홀 측벽 및 저면의 잔류물을 완전히 제거하여 금속배선간 저항을 개선할 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to completely remove the residues on the sidewalls and the bottom of the contact hole when forming the metal wiring to which the low-dielectric film containing the carbon component is applied to improve the resistance between metal wirings. It relates to a method for manufacturing a semiconductor device that can be.
일반적으로, 반도체 소자의 제조시 소자와 소자 간, 또는, 배선과 배선 간을 전기적으로 연결하기 위해 금속배선을 사용하고 있다. In general, in the manufacture of semiconductor devices, metal wirings are used to electrically connect the devices with each other or between the wirings and the wirings.
그런데, 최근 반도체 소자의 고집적화가 진행함에 따라 금속배선의 폭 및 콘택 면적이 감소하여 콘택저항을 비롯한 금속배선의 저항이 점차 증가하게 되었다. 또한, 상기 금속배선 및 콘택플러그 간의 간격이 좁아짐에 따라 금속배선을 절연시키는 절연막으로 인해 유발되는 기생 캐패시턴스가 증가하게 되었으며, 아울러, 금속배선 간 공간의 매립 공정이 어려워지게 되었다.However, as the integration of semiconductor devices in recent years has progressed, the width and contact area of metal wirings have decreased, and the resistance of metal wirings including contact resistances has gradually increased. In addition, as the gap between the metal wiring and the contact plug is narrowed, parasitic capacitance caused by the insulating film for insulating the metal wiring is increased, and the process of filling the space between the metal wiring becomes difficult.
이에, 상기 금속배선의 저항을 낮추고 기생 캐패시턴스를 감소시키기 위한 다양한 공정 기술들이 연구되고 있으며, 그 일환으로서, 상기 금속배선 간 공간을 매립하기 위한 절연막 물질로 매립특성이 우수하며 유전상수 값(K)이 낮은 저유전막을 사용하려는 시도가 이루어지고 있다. Therefore, various process technologies for reducing the resistance of the metal wiring and reducing the parasitic capacitance have been studied. As a part of this, an insulating material for filling the space between the metal wirings has excellent embedding characteristics and a dielectric constant value (K). Attempts have been made to use this low low dielectric film.
상기 금속배선의 매립을 위해 저유전막을 형성하면, 기생 캐패시턴스(Parasitic Capacitance)의 형성이 방지되어 반도체 소자의 동작속도가 개선된다는 장점이 있다.When the low dielectric film is formed to fill the metal wiring, parasitic capacitance is prevented from being formed, thereby improving the operation speed of the semiconductor device.
한편, 상기 저유전막으로서 플루오린(Fluorine)이 함유된 실리콘산화막, 또는, 카본(Carbon)이 함유된 실리콘산화막을 사용하는 방법이 제안되고 있다. Meanwhile, a method of using a silicon oxide film containing fluorine or a silicon oxide film containing carbon as the low dielectric film has been proposed.
여기서, 상기 플루오린이 함유된 실리콘산화막은 유전상수 값이 3.5∼3.7 정도로 비교적 높은 편이기 때문에 커플링(Coupling)을 감소시키는 효과가 적으므로, 상기 저유전막으로서 2.5∼3.0 정도의 낮은 유전상수 값을 갖는 카본이 함유된 실리콘산화막(이하, SiOC막)이 두루 적용되고 있다. Here, since the silicon oxide film containing fluorine has a relatively high dielectric constant value of 3.5 to 3.7, there is little effect of reducing coupling, and thus the low dielectric film has a low dielectric constant value of about 2.5 to 3.0. Silicon oxide films (hereinafter, referred to as SiOC films) containing carbons are applied throughout.
이하에서는, 저유전막으로서 상기 SiOC막을 적용한 종래의 금속배선 공정을 개략적으로 설명하도록 한다.Hereinafter, a conventional metallization process in which the SiOC film is applied as the low dielectric film will be described schematically.
우선, 하부 금속배선이 형성된 반도체 기판 상에 SiOC막으로 저유전막을 형성한 후, 상기 저유전막 상에 공지의 포토리소그라피 공정을 통해 마스크 패턴을 형성한다. 그런 다음, 상기 마스크 패턴에 의해 노출된 저유전막 부분을 식각하여 콘택홀을 형성함과 아울러 마스크 패턴을 제거한다.First, a low dielectric film is formed of an SiOC film on a semiconductor substrate on which a lower metal wiring is formed, and then a mask pattern is formed on the low dielectric film through a known photolithography process. Then, the low dielectric film portion exposed by the mask pattern is etched to form a contact hole and to remove the mask pattern.
계속해서, 상기 콘택홀을 완전 매립하도록 금속막, 예컨데, 텅스텐막이나 구리막을 증착하고 나서, 이를 CMP(Chemical Mechanical Polishing)한 후, 상기 CMP된 금속막을 포함한 기판 결과물 상에 상부 금속배선을 형성한다.Subsequently, a metal film, for example, a tungsten film or a copper film is deposited so as to completely fill the contact hole, followed by CMP (Chemical Mechanical Polishing), and then an upper metal wiring is formed on the substrate product including the CMP metal film. .
그러나, 카본 성분을 함유한 저유전막이 적용된 종래 기술의 경우에는, 상기 카본 성분을 함유한 저유전막의 식각 공정시 아웃개싱(Outgassing)현상이 심화되면서, 식각 공정 후에 상기 콘택홀 측벽 및 저면에 잔류물이 존재하여, 상기 콘택 사이즈가 작을수록 상, 하부 금속배선간 저항이 증가된다. However, in the prior art to which the low dielectric film containing the carbon component is applied, the outgassing phenomenon in the etching process of the low dielectric film containing the carbon component is intensified and remains on the sidewalls and the bottom of the contact hole after the etching process. Since water is present, the smaller the contact size is, the higher the resistance between the upper and lower metal interconnections is.
따라서, 본 발명은 카본 성분 함유 저유전막을 적용한 금속배선의 형성시, 콘택홀 측벽 및 저면의 잔류물을 완전히 제거할 수 있는 반도체 소자의 제조방법을 제공한다.Accordingly, the present invention provides a method of manufacturing a semiconductor device capable of completely removing the residues on the sidewalls and the bottom of the contact hole when forming the metal wiring to which the carbon component-containing low dielectric film is applied.
또한, 본 발명은 콘택홀 측벽 및 저면의 잔류물을 완전히 제거하여 금속배선간 저항을 개선시킬 수 있는 반도체 소자의 제조방법을 제공한다.In addition, the present invention provides a method of manufacturing a semiconductor device capable of completely removing the residues on the sidewalls and bottoms of the contact holes to improve the resistance between metal lines.
일실시예에 있어서, 반도체 소자의 제조방법은, 반도체 기판 상에 카본 성분을 함유한 저유전막을 형성하는 단계; 상기 저유전막을 식각하여 콘택홀을 형성하 는 단계; 상기 콘택홀 표면에 발생된 잔류물을 제거하는 단계; 및 상기 콘택홀을 매립하도록 저유전막 상에 금속막을 형성하는 단계;를 포함한다.In one embodiment, a method of manufacturing a semiconductor device includes forming a low dielectric film containing a carbon component on a semiconductor substrate; Etching the low dielectric layer to form a contact hole; Removing residues generated on the contact hole surface; And forming a metal film on the low dielectric film to fill the contact hole.
상기 콘택홀 표면에 발생된 잔류물은 C, H 및 O 중 적어도 어느 하나 이상의 결합물질이다.The residue generated on the contact hole surface is a binder of at least one of C, H and O.
상기 콘택홀 표면에 발생된 잔류물을 제거하는 단계는, 상기 콘택홀이 형성된 기판 결과물에 대해 플라즈마 처리하는 단계; 상기 플라즈마 처리된 기판 결과물에 자외선을 조사하는 단계; 및 상기 자외선 조사가 이루어진 기판 결과물을 열처리하는 단계;로 구성된다.The removing of the residue generated on the contact hole surface may include: performing a plasma treatment on a resultant substrate on which the contact hole is formed; Irradiating ultraviolet light to the plasma-treated substrate resultant; And heat-treating the substrate resulting from the ultraviolet irradiation.
상기 콘택홀 표면에 발생된 잔류물을 제거하는 단계는, 상기 콘택홀이 형성된 기판 결과물을 열처리하면서, 플라즈마 처리하는 단계; 및 상기 플라즈마 처리된 기판 결과물을 열처리하면서, 자외선을 조사하는 단계;로 구성된다.The removing of the residue generated on the contact hole surface may include: performing a plasma treatment while heat-treating the resultant substrate on which the contact hole is formed; And irradiating ultraviolet rays while heat-treating the plasma-treated substrate resultant.
상기 콘택홀 표면에 발생된 잔류물을 제거하는 단계;는, 상기 콘택홀이 형성된 기판 결과물을 열처리하면서, 플라즈마 처리함과 아울러 자외선을 조사하여 수행한다.Removing the residue generated on the surface of the contact hole; performing the plasma treatment and irradiated with ultraviolet rays while heat-treating the resultant substrate on which the contact hole is formed.
상기 플라즈마 처리는 H2 및 NH3 중 어느 하나를 사용하여 300∼700W의 에너지로 100∼200초 동안 수행한다.The plasma treatment is performed for 100 to 200 seconds using an energy of 300 to 700 W using any one of H 2 and NH 3 .
상기 자외선 조사는 300∼350㎚의 파장을 갖는 자외선을 사용하여 10∼30㎽/㎝2의 강도로 100∼300초 동안 수행한다.The ultraviolet irradiation is performed for 100 to 300 seconds at an intensity of 10 to 30 mW / cm 2 using ultraviolet rays having a wavelength of 300 to 350 nm.
상기 열처리는 200∼300℃의 온도로 수행한다.The heat treatment is carried out at a temperature of 200 ~ 300 ℃.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명은 카본 성분을 함유한 저유전막을 식각하여 금속배선용 콘택홀을 형성한 다음, H2 플라즈마 처리와 자외선 조사 및 열처리를 차례로 수행하여 상기 콘택홀의 측벽 및 저면에 존재하는 잔류물을 완전히 제거하고, 그리고 나서, 상기 콘택홀을 매립하도록 금속막을 형성한다.According to the present invention, a low dielectric film containing a carbon component is etched to form a contact hole for metal wiring, and then H 2 plasma treatment, ultraviolet irradiation, and heat treatment are performed in order to completely remove residues on the sidewalls and bottom of the contact hole. Then, a metal film is formed to fill the contact hole.
이렇게 하면, 상기 콘택홀의 측벽 및 저면에 존재하는 C, H 및 O의 결합물 형태의 잔류물이 상기 플라즈마 처리를 통해 CH, H2 및 H2O의 결합물로 변화되고, 상기 CH, H2 및 H2O의 결합물은 자외선 조사를 통해 CH, H2 및 H2O로 각각 분리되며, 상기 CH, H2 및 H2O은 열처리를 통해 아웃개싱(Outgassing)되므로, 상기 콘택홀 측벽 및 저면의 잔류물을 완전히 제거할 수 있다.In this way, residues in the form of a combination of C, H, and O present on the sidewalls and bottom of the contact hole are converted into a combination of CH, H 2 and H 2 O through the plasma treatment, and the CH, H 2 and, the contact hole sidewall and so the combination of H 2 O are each separated by a CH, H 2 and H 2 O through the ultraviolet irradiation, the CH, H 2 and H 2 O is outgassing (outgassing) through heat treatment The residue on the bottom can be completely removed.
따라서, 본 발명은 상기 콘택홀의 측벽 및 저면에 존재하는 잔류물을 완전히 제거함으로써, 금속배선의 저항을 개선할 수 있다.Therefore, the present invention can improve the resistance of the metal wiring by completely removing the residues present on the sidewalls and bottom of the contact hole.
도 1a 내지 도 1f는 본 발명의 일실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도이다.1A to 1F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 하부 금속배선(102)이 형성된 반도체 기판(100) 상에 카본 성분을 함유한 저유전막(104)을 형성한다. 여기서, 상기 저유전막(104)은 매립특성이 우수하며 유전상수 값(K)이 낮은 SiOC막으로 형성한다.Referring to FIG. 1A, a low
도 1b를 참조하면, 상기 저유전막(104) 상에 콘택홀 형성 영역을 노출시키는 마스크 패턴(도시안됨)을 형성한 다음, 상기 마스크 패턴에 의해 노출된 저유전막(104) 부분을 식각하여 금속배선용 콘택홀(H)을 형성함과 아울러 상기 마스크 패턴을 제거한다. Referring to FIG. 1B, a mask pattern (not shown) for exposing a contact hole forming region is formed on the low
이때, 상기 저유전막(104)의 식각 공정시 아웃개싱 현상이 심화되면서, 식각 공정 후에 상기 콘택홀(H) 측벽 및 저면에 잔류물(S)이 남게 된다. 통상, 상기 잔류물은 C, H 및 O의 결합물 형태로 잔류된다.At this time, the outgassing phenomenon in the etching process of the low
도 1c를 참조하면, 상기 콘택홀(H)이 형성된 기판(100) 결과물에 대해 플라즈마 처리해서 C, H 및 O의 결합물 형태의 잔류물(S)을 CH, H2 및 H2O의 결합물로 변화시킨다. 상기 플라즈마 처리는 H2 및 NH3 중 어느 하나를 사용하여 300∼700W 정도의 에너지로 100∼200초 정도 동안 수행한다.Referring to FIG. 1C, the resultant of the
도 1d를 참조하면, 상기 플라즈마 처리된 기판(100) 결과물에 자외선을 조사해서 상기 CH, H2 및 H2O의 결합물 형태로 존재하는 잔류물(S)을 CH, H2 및 H2O로 각각 분리시킨다. 이때, 상기 자외선 조사는 300∼350㎚ 정도의 파장을 갖는 자외선을 사용하여 10∼30㎽/㎝2 정도의 강도로 100∼300초 정도 동안 수행한다.Referring to Figure 1d, and irradiated with ultraviolet rays in the plasma processing of the
여기서, 상기 콘택홀(H)의 측벽 및 저면에 C, H 및 O의 결합물 형태로 존재하는 잔류물(S)은 결합에너지가 4eV 이하로 낮기 때문에, 300∼400㎚ 정도의 파장, 바람직하게는, 300∼350㎚ 정도의 파장을 갖는 자외선을 조사함으로써 상기 결합물의 결합을 깰 수 있다.Here, the residue S present in the form of a combination of C, H and O on the sidewall and the bottom of the contact hole H has a low binding energy of 4 eV or less, and thus has a wavelength of about 300 to 400 nm, preferably Can break the bond of the binder by irradiating ultraviolet rays having a wavelength of about 300 to 350 nm.
도 1e를 참조하면, 상기 자외선 조사가 이루어진 기판(100) 결과물을 열처리해서 분리된 CH, H2 및 H2O를 아웃개싱(Outgassing)시킴으로써, 상기 콘택홀(H) 내의 잔류물을 완전히 제거한다. 이때, 상기 열처리는 200∼300℃ 정도의 온도로 수행한다.Referring to FIG. 1E, a residue of the contact hole H is completely removed by outgassing the separated CH, H 2 and H 2 O by heat-treating the
여기서, 본 발명은 자외선을 조사하기 전에 H2 혹은 NH3 플라즈마 처리를 수행하여 H가 콘택홀(H) 내의 잔류물과 일차적인 반응을 일으킴으로써, 열처리에 의한 아웃개싱 현상을 촉진할 수 있으며, 이를 통해, 상기 콘택홀(H) 내의 잔류물 제거가 더욱 효과적으로 이루어진다.Here, in the present invention, by performing H 2 or NH 3 plasma treatment before irradiating ultraviolet rays, H reacts primarily with residues in the contact hole H, thereby facilitating outgassing by heat treatment. As a result, residues in the contact hole H are more effectively removed.
도 1f를 참조하면, 상기 잔류물이 완전히 제거된 기판(100) 전면 상에 상기 콘택홀(H)을 매립하도록 금속막(106), 예컨데, 텅스텐막이나 구리막을 증착한다. 그 다음, 상기 금속막(106)을 CMP(Chemical Mechanical Polishing)한 후, 상기 금속막(106)을 포함한 기판(100) 결과물 상에 상부 금속배선(108)을 형성한다.Referring to FIG. 1F, a
이후, 도시하지는 않았지만 공지된 일련의 후속 공정들을 차례로 수행하여 본 발명의 실시예에 따른 반도체 소자를 완성한다.Subsequently, although not shown, a series of subsequent known processes are sequentially performed to complete the semiconductor device according to the embodiment of the present invention.
여기서, 본 발명은 카본 성분을 함유한 저유전막을 적용한 금속배선의 형성시, 상기 저유전막을 식각하여 콘택홀을 형성한 다음 자외선을 조사하여 상기 콘택홀 측벽 및 저면에 존재하는 잔류물을 완전히 제거하고, 그리고 나서, 금속막으로 상기 콘택홀을 매립하여 금속배선을 형성한다.In the present invention, when forming a metal wiring to which a low dielectric film containing a carbon component is applied, the low dielectric film is etched to form a contact hole and then irradiated with UV light to completely remove residues on the sidewalls and the bottom of the contact hole. Then, the contact hole is filled with a metal film to form metal wiring.
자세하게, 상기 잔류물의 주성분인 -C-, -H- ,-O-등의 결합물을 제거하는 방 법으로 H2 혹은 NH3 플라즈마 처리를 실시하여 CH, H2 및 H2O의 결합물로 변화시킨 다음, 자외선을 조사하여 상기 CH, H2 및 H2O의 결합물을 CH, H2 및 H2O로 각각 분리시키고 상기 분리된 CH, H2 및 H2O를 아웃개싱(Outgassing)시킴으로써 상기 콘택홀 내의 잔류물을 제거할 수 있다.In detail, H 2 or NH 3 plasma treatment is performed to remove the complexes of -C-, -H-, -O- and the like, which are the main components of the residue, to form a combination of CH, H 2 and H 2 O. change was then irradiated with ultraviolet rays the CH, respectively, separate the combination of H 2 and H 2 O in CH, H 2 and H 2 O and the detached CH, H 2 and H 2 O outgassing (outgassing) By doing so, the residue in the contact hole can be removed.
따라서, 본 발명은 상기 콘택홀 내에 존재하는 잔류물을 완전히 제거함으로써 상, 하부 금속배선간 저항을 개선할 수 있으며, 이를 통해, 반도체 소자의 신뢰성을 향상시킬 수 있다. Therefore, the present invention can improve the resistance between the upper and lower metal wires by completely removing the residues present in the contact hole, thereby improving the reliability of the semiconductor device.
한편, 전술한 본 발명의 일실시예의 경우에는 상기 플라즈마 처리와 자외선 조사 및 열처리를 차례로 수행함으로써 콘택홀 내의 잔류물을 완전히 제거하였으나, 본 발명의 다른 실시예로서 열처리를 수행하면서 상기 플라즈마 처리와 자외선 조사를 차례로 수행함으로써 상기 콘택홀 내의 잔류물을 완전히 제거할 수 있다.Meanwhile, in the above-described embodiment of the present invention, residues in the contact holes are completely removed by sequentially performing the plasma treatment, ultraviolet irradiation, and heat treatment. However, as another embodiment of the present invention, the plasma treatment and ultraviolet ray are performed while performing the heat treatment. Irradiation may be performed in sequence to completely remove residues in the contact hole.
또한, 본 발명의 또 다른 실시예로서, 열처리를 수행하면서 상기 플라즈마 처리와 자외선 조사를 동시에 수행함으로써 상기 콘택홀 내의 잔류물을 완전히 제거할 수 있다.In addition, as another embodiment of the present invention, the residue in the contact hole may be completely removed by simultaneously performing the plasma treatment and ultraviolet irradiation while performing the heat treatment.
이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.
이상에서와 같이, 본 발명은 카본 성분을 함유한 저유전막 내에 콘택홀이 형성된 기판 결과물에 대해 플라즈마 처리와 자외선 조사 및 열처리를 수행함으로써 상기 콘택홀 내의 잔류물을 완전히 제거할 수 있으며, 이를 통해, 금속배선의 저항을 개선시킬 수 있다.As described above, the present invention can completely remove the residue in the contact hole by performing plasma treatment, ultraviolet irradiation, and heat treatment on the substrate product in which the contact hole is formed in the low dielectric film containing the carbon component. The resistance of the metal wiring can be improved.
Claims (8)
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| KR20030049901A (en) * | 2001-12-17 | 2003-06-25 | 주식회사 하이닉스반도체 | A fabricating method of semiconductor devices |
| KR20040016697A (en) * | 2002-08-19 | 2004-02-25 | 삼성전자주식회사 | Method of manufacturing semiconductor device |
| US20040072440A1 (en) * | 2001-07-02 | 2004-04-15 | Yong-Bae Kim | Process for removal of photoresist mask used for making vias in low K carbon-doped silicon oxide dielectric material, and for removal of etch residues from formation of vias and removal of photoresist mask |
| KR20070068802A (en) * | 2005-12-27 | 2007-07-02 | 동부일렉트로닉스 주식회사 | Method of fabricating the conductive contact in semiconductor device |
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| US20040072440A1 (en) * | 2001-07-02 | 2004-04-15 | Yong-Bae Kim | Process for removal of photoresist mask used for making vias in low K carbon-doped silicon oxide dielectric material, and for removal of etch residues from formation of vias and removal of photoresist mask |
| KR20030049901A (en) * | 2001-12-17 | 2003-06-25 | 주식회사 하이닉스반도체 | A fabricating method of semiconductor devices |
| KR20040016697A (en) * | 2002-08-19 | 2004-02-25 | 삼성전자주식회사 | Method of manufacturing semiconductor device |
| KR20070068802A (en) * | 2005-12-27 | 2007-07-02 | 동부일렉트로닉스 주식회사 | Method of fabricating the conductive contact in semiconductor device |
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