KR20070060846A - Apparatus for burst access for rotating image in semiconducrot memory - Google Patents

Abstract

A burst access device for rotating an image of a semiconductor memory is provided to improve an image processing speed in a DRAM by processing 90° or 270°rotation of image data in a burst mode not a single mode, and improve performance with low power consumption design by using a low clock, as a memory bandwidth is reduced by reading the image in the burst mode. A rotation burst part(410) reads the inputted image data in the burst mode while increasing the image data in a burst length unit. A storing part(420) stores the data received from the rotation burst part in a row direction. A controller(430) reads the data stored in the storing part by a column direction and transfers the read data to an image processor(440). The rotation burst part reads the image data of all addresses by reading the image data from a left lower part of the address to an upper direction in the burst length unit, performing shifting to a right side in the burst length unit if all rows of the burst length are read, and reading the image data from the shifted left lower part to the upper direction in the burst length unit.

Description

Apparatus for burst access for rotating image in semiconducrot memory

1 is an exemplary view showing an in-permit structure of a general DRAM;

2A is an image input for image processing,

2B is an exemplary diagram for explaining an order of addresses processed in conventional image processing;

2C is an output image obtained by image processing of FIG. 2A;

3A is an image input for image processing,

3B is an exemplary diagram for explaining the order of addresses processed when rotating an image in conventional image processing;

3C is an output image obtained by image processing of FIG. 3A;

4 is a structural diagram of an embodiment of a burst access device for rotating an image of a semiconductor memory according to the present invention;

5A is an exemplary diagram for indicating an address of data when an image is applied;

5B is an exemplary view for explaining how the rotation burst unit of FIG. 4 reads an address and stores the address;

FIG. 5C is an exemplary diagram for describing a method in which the controller of FIG. 4 reads data stored in a storage unit; FIG.

FIG. 5D is an exemplary diagram for describing an address of image data processed by the image processing unit of FIG. 4. FIG.

6A illustrates an example of image data input to the rotation burst unit 410 of FIG. 4.

6B is an exemplary view illustrating image data stored in a storage unit of FIG. 4;

FIG. 6C is an exemplary view of image data output from the image processing unit of FIG. 4. FIG.

<Description of the symbols for the main parts of the drawings>

410: rotation burst unit 420: storage unit

430: control unit 440: image processing unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst access device for rotating images of a semiconductor memory, and more particularly, to rotating an image by 90 ° or 270 ° in a dynamic random access memory (hereinafter, simply referred to as 'DRAM'). A burst access device for rotating an image of a semiconductor memory for use in the case.

In general, there is a case where an image needs to be rotated during image processing. In this case, if the memory used is DRAM, the access type proceeds as a single due to the 'non-sequence address', so the process speed is reduced by at least six times compared to the non-rotating image ratio. The problem arises, and the bandwidth occupancy is increased while accessing the DRAM, so that the overall system is slowed down.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and provides a burst access device for image rotation of a semiconductor memory for advancing the image rotation in bursts to improve the speed of the image process. There is a purpose.

In order to achieve the above object, according to a preferred embodiment of the present invention, in the burst access device for image rotation of the semiconductor memory having an image processing unit for performing the image processing, the applied image data burst length A rotating burst unit for reading in bursts while increasing in units; A storage unit for storing data received from the rotation burst unit in a column direction; And a controller configured to read data stored in the storage unit in a row direction and transmit the read data in a row direction to the image processing unit.

In this case, the rotation burst unit reads upward in the burst length unit from the bottom left of the address of the image data, and when reading of all the rows of the burst length is completed, the rotation burst unit moves to the right in the burst length unit. Read from the bottom left to the burst length unit to read data from all addresses in burst length unit.

In addition, the storage unit is preferably an internal line memory, and also preferably a static memory device (SRAM). In this case, the size of the storage unit may be determined according to the width and burst length of the image.

The controller may be a cache or a double buffer controller.

First, prior to the description of the present invention, data access for a conventional image process will be described.

In general, static random access memory (hereinafter, simply referred to as 'SRAM') is faster to access than DRAM. However, because such SRAMs are expensive, memory such as caches use SRAM, but portions of the memory that require large memory such as image processing use DRAM. The interface structure of the DRAM is shown in FIG.

1 is an exemplary view showing an in-peritate structure of a general DRAM.

In terms of the address of the DRAM as shown in the figure, the sequence address is arranged by BANK, row address strobe (RAS), and column address strobe (CAS). These addresses have different bit widths depending on the memory size, but for convenience, the following example will be given.

Assuming DRAMs with 512 bytes as a whole, they consist of BANK [0], RAS [3: 0], and CAS [3: 0].

BANK [0]-sequence address [8]: 1 bit width

RAS [3: 0]-sequence address [7: 4]: 4bit width

CAS [3: 0]-sequence address [3: 0]: 4bit width

In this example, if a unit performing a write to a DRAM memory writes a 16 × 16 16-bit image, it will have an address as shown in Table 1 below.

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262 264 266 268 270 272 274 276 278 280 282 284 286 288 290 292 294 296 298 300 302 304 306 308 310 312 314 316 318 320 322 324 326 328 330 332 334 336 338 340 342 344 346 348 350 352 354 356 358 360 362 364 366 368 370 372 374 376 378 380 382 384 386 388 390 392 394 396 398 400 402 404 406 408 410 412 414 416 418 420 422 424 426 428 430 432 434 436 438 440 442 444 446 448 450 452 454 456 458 460 462 464 466 468 470 472 474 476 478 480 482 484 486 488 490 492 494 496 498 500 502 504 506 508 510

The DRAM of the above example has a total of two BANKs, the RAS consists of 16 rows, and the CAS consists of 16 columns. If you want to access '0', you should give RAS = 0, CAS = 0, '32' gives RAS = 1, CAS = 0, and '34' gives RAS = 1, CAS = 1. .

If the address is read from address '0' to '510' and data is read, the address from '0' to '30' operates as a burst. That is, all rows in the same RAS can perform a burst operation. In this case, the burst operation refers to an operation of reading / writing data at every clock. At address 30, the burst ends with a BANK precharge command. In order to proceed with the next burst, when the address is '32', the BANK active command is transmitted, the RAS address is updated, and the user can wait again for the CAS latency and then proceed with the burst. This process can be repeated to proceed with a total of 16 bursts 16 (burst16).

Assume that the image in the above example is rotated 90 °. When the image is rotated by 90 °, the memory address is shown in Table 2 below.

480 448 416 384 352 320 288 256 224 192 160 128 96 64 32 0 482 450 418 386 354 322 290 258 226 194 162 130 98 66 34 2 484 452 420 388 356 324 292 260 228 196 164 132 100 68 36 4 486 454 422 390 358 326 294 262 230 198 166 134 102 70 38 6 488 456 424 392 360 328 296 264 232 200 168 136 104 72 40 8 490 458 426 394 362 330 298 266 234 202 170 138 106 74 42 10 492 460 428 396 364 332 300 268 236 204 172 140 108 76 44 12 494 462 430 398 366 334 302 270 238 206 174 142 110 78 46 14 496 464 432 400 368 336 304 272 240 208 176 144 112 80 48 16 498 466 434 402 370 338 306 274 242 210 178 146 114 82 50 18 500 468 436 404 372 340 308 276 244 212 180 148 116 84 52 20 502 470 438 406 374 342 310 278 246 214 182 150 118 86 54 22 504 472 440 408 376 344 312 280 248 216 184 152 120 88 56 24 506 474 442 410 378 346 314 282 250 218 186 154 122 90 58 26 508 476 444 412 380 348 316 284 252 220 188 156 124 92 60 28 510 478 446 414 382 350 318 286 254 222 190 158 126 94 62 30

As explained in the table, the memory of Table 1 itself is rotated 90 degrees.

When reading memory in this manner, 480, 448, 416, 384,... It reads in .. form, which causes DRAM to operate inefficiently. In other words, since the RAS address must be updated continuously when reading data, single operation occurs and burst transmission does not occur.

That is, in the case of the transfer of the burst transfer as shown in Table 1, data can be read / written at 1.2 clocks, but when such a single transfer is repeated, BANK active (1 clock) and RAS load (1). Clock), CAS load (1 clock), CAS delay (2-3 clock), data read / write (1 clock), and BANK precharge (1 clock), so that at least 6 ~ There is a problem that a seven times speed difference occurs.

FIG. 2A illustrates an input image for image processing, FIG. 2B illustrates an example of an order of addresses processed in conventional image processing, and FIG. 2C illustrates an output image obtained by image processing of FIG. 2A. Image processing is performed in the manner as described with reference to 1. 2A to 2C show 100 × 100 bits as an example.

Meanwhile, FIG. 3A illustrates an image input for image processing, and FIG. 3B is an exemplary diagram for describing an order of addresses processed when rotating an image in a conventional image processing, and FIG. 3C illustrates image processing of FIG. 3A. One output image is shown and image processing is performed in the same manner as described with reference to Table 2. 3A to 3C, the image used in Figs. 2A to 2C is used, and thus 100 x 100 bits is described as an example.

Therefore, an object of the present invention is to improve the speed over a single operation by performing a burst approach to DRAM even when the image data is rotated by 90 degrees.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same components have the same number as much as possible even if displayed on different drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a structural diagram of an embodiment of a burst access device for image rotation of a semiconductor memory according to the present invention.

As shown in the figure, the burst access device according to the present invention includes a rotation burst unit 410, a storage unit 420 and the control unit 430, the data output from the control unit 430 is an image processing It is input to the unit 440. Since the image processing unit 440 that performs image processing of the data is already known in the art, a detailed description thereof will be omitted.

Prior to the description of the present invention, since the data that does not rotate at 90 ° and 270 ° (i.e., 180 ° rotation data or non-rotation data) can be read in bursts from the original in memory, the present invention provides a 90 ° and 270 This can only be applied to data rotating in degrees.

First, the rotation burst unit 410 is responsible for reading in bursts while increasing the applied image data in burst length units. That is, when reading the image data, the data rotated in the same manner as in FIG. 3B is not read, but is read in increments in burst units. This will be described with reference to FIG. 5A.

FIG. 5A is an exemplary diagram for illustrating an address of image data when the image of FIG. 3A is applied, and FIG. 5B is an exemplary diagram for describing a method in which the rotation burst unit of FIG. 4 reads an address and stores the address in the storage unit. . In the description of the present invention, a case where 100 x 100 bit image data of FIG. 2A or 3A is input will be described as an example.

According to the conventional method as in FIG. 3B, 9900, 9800, 9700 ,,,,, 100, 0, 9901, 9801 ,,,,,, 101, 1, 9902, 9802 ,,,,, 199,99 order Although the data is read, the rotational burst unit 410 of the present invention assumes that burst 4 is the burst length. , 100, 101, 102, 103, 0, 1, 2, 3, 9904, 9905, 9906, 9907, 9804, 9805, 9806, 9807,... , 96, 97, 98, 99 in order to read in bursts of four units to be stored in the storage unit 420. However, in the description of the present invention, for the sake of convenience, the burst reading in four units has been described as an example. However, the present invention is not limited thereto, and the number may be differently determined according to a system.

In this case, the storage unit 420 serves as an internal line memory, and may be an SRAM. The storage unit 420 is responsible for storing data received from the rotation burst unit 410 in a column direction (ie, a vertical direction).

That is, the rotation burst unit 410 reads the address of FIG. 5A in the upward direction from the left bottom portion (bottom) in four units. When the upper left portion meets the last, the left bottom portion moves to the right in four units again. It reads in bursts of four from the top.

Thereafter, the controller 430 reads the data stored in the storage 420 in the arrow direction (ie, the row direction; the horizontal direction) shown in FIG. 5C to provide the data requested by the image processing unit 440. It is responsible for the function provided to the processing unit 440.

FIG. 5C is an exemplary diagram for describing a method in which the control unit of FIG. 4 reads data stored in a storage unit, and FIG. 5D is an exemplary diagram for explaining an address of image data processed by the image processing unit of FIG. 4. to be.

As shown in the figure, the controller 430 reads the data stored in the storage 420 in the horizontal direction, thereby obtaining a data address as shown in FIG. 5D.

According to the present invention, since all the approaches to the DRAM are performed in bursts, the disadvantages of the speed drop can be compensated for by approaching the existing single.

Meanwhile, the size of the storage unit 420 is determined according to the image width and burst length of the image of the rotation burst unit 410. This expression is expressed as the following equation.

If the rotation burst unit 410 proceeds to 'burst4', the size of the storage unit 420 becomes 'image width × burst4'.

In addition, the controller 430 is preferably a cache, but there is an application that accesses one pixel many times at a time difference such as interpolation in the image processing unit 440, which is the back side thereof. A double buffer controller can also be used.

6A illustrates an example of image data input to the rotation burst unit 410 of FIG. 4, and FIG. 6B illustrates an example of image data stored in the storage unit of FIG. 4. 6C is an exemplary view of image data output from the image processing unit of FIG. 4. The interval A in FIG. 6B represents the burst length.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the present invention allows the DRAM to proceed in a burst rather than single when rotating the image data provided for image processing, so that the memory bandwidth is reduced, and thus a low clock can be used, thereby enabling a low power design. It is effective to improve the performance of the product.

Claims (7)

A burst access device for rotating an image of a semiconductor memory having an image processing unit for performing image processing, the apparatus comprising: A rotation burst unit for reading bursts while increasing applied image data in burst length units; A storage unit for storing data received from the rotation burst unit in a column direction; And And a control unit for reading the data stored in the storage unit in a row direction and transferring the data stored in the row unit to the image processing unit. According to claim 1, wherein the rotation burst unit, in the upper direction from the lower left of the address of the image data to read in the burst length unit, when the reading is completed for all the rows of the burst length, in the burst length unit A burst access device for rotating an image of a semiconductor memory, which reads data of all addresses in burst length units by reading upward from the lower left portion moved to the right. The burst access device of claim 1, wherein the storage unit is an internal line memory. The burst access device of claim 3, wherein the storage unit is a static memory device (SRAM). The apparatus of claim 1, wherein the size of the storage unit is determined according to a width and a burst length of the image. The apparatus of claim 1, wherein the controller is a cache. The apparatus of claim 1, wherein the controller is a double buffer controller.

Images