KR20070052403A - Programming method for nand flash memory - Google Patents

Abstract

The present invention relates to a method of verifying a flash memory device, comprising: applying a read voltage Vread to an unselected word line; And applying a verification read voltage Vver to the selected word line after a predetermined time from when the read voltage Vread is applied to the unselected word line. According to the present invention including the above-described steps, the verification voltage applied to the selected word line is uniformly distributed regardless of the distance from the X-decoder to prevent over-programming and to increase the program speed.

Description

Program method of NAND flash memory {PROGRAMMING METHOD FOR NAND FLASH MEMORY}

1 is a word line voltage waveform diagram showing a program voltage application scheme according to the prior art;

2 is a block diagram of a memory device for implementing the program method of the present invention;

3 is a waveform diagram showing a word line voltage application method according to the present invention;

4A is a view illustrating a selected word line voltage waveform set when the word line voltage of FIG. 1 is applied;

4B is a diagram illustrating a selected word line voltage waveform set when the word line voltage of FIG. 3 is applied.

* Explanation of symbols for main parts of drawings *

10: voltage generator 20: X-decoder

30 cell array 40 page buffer circuit

50: Y-gate 60: pass / fail detection circuit

70: program control unit

The present invention relates to a semiconductor memory device, and more particularly, to a method of programming a NAND flash memory device.

In general, NAND flash memory performs a program / erase operation by storing charges in a floating gate or releasing charges stored in a floating gate to a channel by using a tunneling phenomenon. The program and erase method as described above satisfies the excellent preservation of stored data and is suitable for nonvolatile memory. In addition, flash memory has high integration, low power consumption, and strong durability against external shock, and thus its use is increasing in auxiliary storage devices and other applications of mobile devices. However, despite these advantages, new technologies for flash memory have been constantly emerging. In particular, in the case of NAND flash memory, research has been conducted to control the density distribution of threshold voltages of memory cells to solve problems caused by over-programming. The program operation of the NAND flash memory can be largely divided into a program section for applying a program voltage to a corresponding word line and a verification section for verifying whether a threshold voltage of a cell has moved to a desired distribution due to the application of the program voltage. A program of a general flash memory proceeds according to an incremental step pulse programming (ISPP) scheme in which the program voltage Vpgm is gradually increased, and the program and the verification operation are repeated.

1 is a waveform diagram showing a voltage applied to a word line during one loop in ISPP. In this case, the loop is the minimum unit of a program cycle in which the program voltage Vpgm is applied to the word line and subsequent verification is performed. Referring to FIG. 1, one program loop includes a program execution section PGM.EXE, a verification section VER, and a recovery section RCV in which all word lines therebetween are discharged to the ground level.

The program execution section PGM.EXE includes a pass enable section Vpass.EN for applying a pass voltage Vpass to all word lines, and a program enable section Vpgm. EN). When the program voltage Vpgm is applied to the select word line, electron injection by F-N tunneling may occur into the floating gate of the cell. On the other hand, a pass voltage Vpass is applied to the unselected word line, which causes the memory cells included in the unselected word line to be program disturbed. At the same time, the application of the pass voltage of the unselected word line biases the channel of the memory cell connected to the selected word line to ground voltage for effective F-N tunneling.

The recovery period RCV discharges the word line to which the program voltage Vpgm and the pass voltage Vpass are applied to the ground voltage level. In particular, the select word line to which the program voltage Vpgm is applied is discharged earlier than the unselected word line as shown in the waveform diagram of FIG. Preferably, during the recovery period RCV, the voltages of all word lines are discharged to the ground voltage level so as not to cause a problem due to charge accumulation. However, a word line distributed relatively far from the X-decoder (or word line driver) which discharges the word line to the ground level is not discharged sufficiently in the recovery period (RCV). Therefore, even in the same word line, the voltage is not set to the ground level according to the degree of discharge according to the distance from the X-decoder, and charge is accumulated. In this state, when the verify voltage Vver is applied, the potential of the word line which is relatively far from the X-decoder may transition to the verify voltage Vver or more depending on the charge accumulation effect.

During the verify period Verify, a verify voltage Vver (for example, 1.3 V) is applied to the selected word line, and a read voltage Vread is applied to the unselected word line. However, since the read voltage Vread is a voltage that is relatively higher than the verify voltage Vver, a coupling effect occurs between the selected word line and the adjacent unselected word line. In particular, when the selection word line with a small potential rise and the non-select word line with a relatively large potential rise are adjacent, and at the same time, when the corresponding voltage is applied to each word line, the selection word line is relatively affected by the coupling. You will receive a lot. The voltage of the unselected word line adjacent to the select word line increases from the ground level to the read voltage (Vread, for example 5 V), but the select word line increases from the ground level to the verify voltage (Vver, for example 1.3 V). do. As described above, as voltages of different levels are simultaneously applied, the voltage of the selected word line may increase to an appropriate level (ie, 1.3V) or more due to the coupling.

As described above, inadequate discharge that may occur in the recovery interval RCV of the word line distributed relatively far from the X-decoder 20 and coupling that may occur in the verify interval Verify may cause the following problems. Cause. That is, during the program verify operation, the set voltage of the word line distributed over a long distance from the X-decoder of the selected word line increases. In this case, since the verification operation occurs in a state higher than the specified verify voltage Vver, the number of program loops until the verify pass is increased, which in turn causes over-programming. Over-programming in NAND flash memory is a serious problem because it degrades the read operation of the remaining cells. In addition, an increase in the number of program loops means a decrease in program speed.

 The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a method for setting a word line with a constant verify voltage regardless of the distance to the X-decoder.

According to a method of verifying a flash memory device of the present invention for achieving the above object, the method includes: applying a read voltage Vread to an unselected word line; And applying a verification read voltage Vver to the selected word line after a predetermined time from when the read voltage Vread is applied to the unselected word line.

In a preferred embodiment, the predetermined time is the select word line is discharged below the verify read voltage (Vver).

In a preferred embodiment, the predetermined time is a time taken for the unselected word line to be fixed to the read voltage Vread.

In a preferred embodiment, the predetermined time is a time for minimizing the coupling of the selected word line due to the voltage variation of the unselected word line.

A flash memory device of the present invention for achieving the above object is a memory cell array having a plurality of word lines; A voltage generator for generating a verify read voltage and a read voltage; An X-decoder for supplying the verify read voltage to a selected word line and the read voltage to an unselected word line during a verify operation; And a program controller configured to control the X-decoder to supply the verify read voltage at a predetermined time delay from the read voltage.

In a preferred embodiment, the X-decoder discharges the selected word line and the unselected word line to ground level prior to a verify operation.

In a preferred embodiment, the predetermined time is a time when the selected word line is discharged below the verify read voltage Vver.

In a preferred embodiment, the predetermined time is a time taken for the unselected word line to be fixed to the read voltage Vread.

The program method of the flash memory device of the present invention for achieving the above object comprises the steps of applying a program voltage to the selected word line, a pass voltage to the unselected word line; Discharging the selected word line and the unselected word line; Applying a read voltage (Vread) to the unselected word line; And applying a verify read voltage Vver to the selected word line after a predetermined time from when the read voltage Vread is applied to the unselected word line.

In a preferred embodiment, the predetermined time is a time when the selected word line is discharged below the verify read voltage Vver.

In a preferred embodiment, the predetermined time is a time taken for the unselected word line to be fixed to the read voltage Vread.

In a preferred embodiment, the predetermined time is a time for minimizing the coupling of the selected word line due to the voltage variation of the unselected word line.

According to the above-described program method and apparatus, in the verifying operation, it is possible to apply the verification voltage with a constant distribution irrespective of the distance to the X-decoder of the selected word line, so that insufficient discharge and couple with the unselected word line can be obtained. The over-programming phenomenon caused by the ring can be prevented. The speed of the program can be increased by setting up a fast verify voltage.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 is a block diagram showing a preferred embodiment of the present invention. Referring to FIG. 2, the verify operation according to the present invention controls the application time of the verification voltage Vver of the selected word line differently from the application time of the read voltage Vread of the unselected word line. This can be done by the program controller 60 adjusting the switching timing of the X-decoder 20.

The voltage generator 10 generates voltages supplied to each word line. Here, the program voltage Vpgm applied to the selected word line, the verify voltage Vver, the pass voltage Vpass to be supplied to the unselected word line, and the read voltages Vread are generated in the program operation to generate the X-decoder ( 20). The general operation of the voltage generator 10 and the generated voltage are not limited thereto, but only the features for describing the scheme of the present invention will be described herein.

The X-decoder 20 applies voltages supplied from the voltage generator 10 to each word line of the selected block in response to the row address (not shown) and the program controller 60. It is well known to those skilled in the art that the X-decoder 20 includes a word line driver connected to each word line to apply and discharge voltage to each word line. The time point at which the voltage is applied to each word line is controlled by the program controller 60 which will be described later.

The cell array 30 may be composed of a plurality of blocks, but one block is illustrated for convenience of description. The cell array 30 includes strings connected to each of the plurality of bit lines BL [0] to BL [m-1]. One string is composed of a string select transistor (hereinafter referred to as SST) and a ground select transistor (hereinafter referred to as GST) and a plurality (for example 32) of memory cells connected in series therebetween. The SSTs of each string share the string select line controlled from the X-decoder 20 as the gate voltage. Similarly, the ground select transistors GST of each string share the ground select line GSL controlled by the X-decoder 20 as the gate voltage. This also applies to memory cells of each string. These memory cells shared by one word line are generally referred to as page units. However, memory cells in one page have different distances from the X-decoder 20 in the layout. As the number of bits in the page increases, the physical distance to the cells arranged at a relatively long distance from the X-decoder 20 will increase. This distance is particularly problematic when discharging. When discharged to the ground (for example, 0V) level, a word line at a short distance from the X-decoder 20 will be able to discharge the charge quickly, but a word line potential at a distance from the X-decoder 20 is sufficient to discharge. If time is not guaranteed (or discharge), the potential may not be reduced to ground level. In addition, the adjacent word lines are mutually influenced by the change of potential according to the coupling. Especially when the transition variation of adjacent word lines is large, larger coupling occurs and this leads to unwanted operations. In the present invention, it is possible to solve the instability of the word line voltage resulting from the above two layout problems in the verify operation of the program loop. Detailed description thereof will be described in detail with reference to the waveform diagram of FIG. 3.

The page buffer circuit 40 includes a page buffer (not shown) corresponding to each of the bit lines BL [0] to BL [m-1] of the cell array 30. During a read operation, each page buffer in page buffer circuit 40 senses data from the selected cell. The sensed data is transferred to the outside via the Y-gate 50. On the other hand, the data to be programmed is temporarily stored during the program operation. In particular, the verify operation during the program cycle senses data of the selected cell. That is, the page buffer circuit 40 senses and latches data of the cell array.

The Y-gate 50 selects columns (page buffers) of the page buffer circuit 40 in a predetermined unit in response to the column address. In the case of a program operation, program data bits are stored through the Y-gate 50 in the selected page buffers. In the case of a read operation, data bits of the selected page buffers are output to the outside through the Y-gate 50. For the verify operation, the data bits of the selected registers are passed through the Y-gate 20 to the pass / fail detection circuit 60.

The pass / fail detection circuit 60 detects whether a pass / fail is performed by referring to the data sensed in the page buffer 40 described above in the verify operation of the program cycle. In general, data of cells inhibited in a program cycle is set to '1', and cells to be programmed are loaded into the page buffer as '0'. When the program voltage Vpgm is applied, the program passes when the data of the page buffer loaded with '0' is all loaded with '1'. The path / fail detection circuit 60 determines the path at the time when the latched bit data of the page buffer becomes '1' and outputs a result signal to the program controller 70. In addition, it is well known to those skilled in the art that it can be configured as a wired-OR type pass / fail detection circuit 60.

The program controller 70 controls the voltage applied to the word line with reference to the result signal of the pass / fail detection circuit 60. The program control unit 70 controls the verification voltage application time point, unlike the prior art, in one loop to which the program pulse and the verify pulse of the program cycle are applied. The program controller 70 delays the application of the verification voltage Vver of the selected word line by a predetermined time (tVER1 in FIG. 3) from the time of applying the read voltage Vread of the non-selected word lines, and thus the discharge time of the selected word line. To ensure. This control can also reduce the coupling effects from adjacent unselected word lines. Detailed description of the control operation related to the program disturb performance such as the bit line voltage and the bulk voltage application of the program controller 70 will be omitted herein. The program control unit 70 of the present invention will be described with only the voltage control of the word line.

The program method of the present invention can be implemented through the above-described configuration of the flash memory device. In the verifying operation, the program control unit 70 differs from applying the verify voltage of the selected word line to the application time of the read voltage of the unselected word line, so that the insufficient amount of the word line is distributed at a relatively long distance from the X-decoder 20. The effects of charge and coupling can be reduced. Accordingly, the present invention can reduce the probability of over-programming caused by an increase in the program loop by inducing a verify voltage higher than the applied voltage.

3 is a waveform diagram illustrating a method of applying a word line voltage according to the present invention. Referring to FIG. 3, the program method of the present invention differs between application time of the verify voltage Vver of the selected word line and the read voltage Vread of the unselected word line in the verify period Verify.

The voltage application method of the selected word line and the unselected word line in the program execution section PGM.EXE is the same as in the prior art. The pass voltage Vpass is applied to the unselected word line for channel bias of the cells of the selected word line. When the pass voltage Vpass applied to the unselected word line is stabilized to a fixed value, the program voltage Vpgm is applied to the selected word line. In FIG. 3, one program voltage Vpgm is illustrated. However, in a typical ISPP, as the number of loops increases in a program cycle, the program voltage Vpgm will increase stepwise to a predetermined step voltage level.

In the recovery period RCV, all word lines are discharged to the ground level before the application of the program voltage is completed and the program path is verified. This is a more necessary step when the magnitude of the verification voltage Vver to be applied to the selected word line is relatively low in the subsequent verification period Verify. In the previous program execution section (PGM.EXE), since the high voltage for the program (for example, about 18V) was applied to the selection word line, the non-selection with a relatively low pass voltage (for example, about 10V) was applied. It is desirable to ensure a discharge time longer than the word line. In particular, the select word line portion distributed over a long distance from the X-decoder 20 has a slow discharge speed, and thus a longer time is required. The present invention for remarkable discharge effect will further allocate a discharge time for the selected word line in the conventional verify period (Verify). The section indicated by tVER1 in the figure corresponds to this. This will be described in detail in the description of the verification section (Verify) which will be described later.

Verification period The overall wordline voltage application operation is performed following the recovery period RCV. The voltage application in the verify period Verify of the selected word line and the unselected word line is different from the conventional point in time when the verify voltage Vver and the read voltage Vread are applied. After the read voltage Vread is applied to the unselected word line, the verify voltage Vver is applied to the selected word line after the predetermined delay time tVER1 has elapsed. The above-described delay time tVER1 may be a time point at which the read voltage Vread is applied and stabilized. This is because the coupling effect is maximized when the read voltage Vread of the relatively high voltage unselected word line changes over time. Alternatively, it may be a point in time where the discharge of a word line of a relatively long distance from the X-decoder 20 is sufficiently guaranteed. Preferably, it can be set to the time that both sufficient discharge mentioned above and stabilization of a read voltage are ensured. However, the above-described delay time tVER1 should be performed within a range that does not reduce the program speed.

According to the verification voltage Vver application method as described above, the discharge time of the selected word line distributed at a relatively long distance from the X-decoder 20 is increased, and the coupling with the unselected word line is performed. The potential fluctuation effect is prevented in advance. Therefore, it is possible to uniformly provide the verification voltages of all the cells in the page sharing one word line, and solve the problem of over-program of cells distributed over a long distance from the X-decoder 20. have.

4A is a waveform diagram illustrating a voltage variation of a selected word line when a voltage application method according to the related art is applied. That is, the potential variation of the selected word line when the word line voltage as shown in FIG. 2 is applied is shown. Curve 1 is a voltage waveform of a selected word line distributed close to the X-decoder 20, and curve 2 is a point distributed relatively far from the X-decoder 20 of the selected word line. Voltage waveform. According to the related art, when the verify voltage Vver and the read voltage Vread are applied to the selected word line and the unselected word line at the same time point (a point of 35 microseconds), they are distributed far away as in curve 2 (Curve2). It can be seen that the time t0 must elapse in order for the point of the selected word line to be set-up to the verify voltage. If the verify operation occurs around 40 ms, there is a possibility that the cell that has been passed through the program is identified as a program fail cell.

4B is a waveform diagram illustrating a voltage variation according to a distance from an X-decoder 20 of a selected word line when the program verification method of the present invention is applied. Curve 3 (Curve3) is the voltage waveform of the selected word line point distributed close to the X-decoder 20, curve 4 (Curve4) is the voltage waveform of the selected word line point distributed relatively far from the X-decoder 20 Voltage waveform. When the verify voltage applied to the selected word line is applied at a time delayed from the application of the read voltage Vread of the unselected word line, the verify voltage is preferably increased by increasing the discharge time and decreasing coupling with the unselected word line. This sets up the entire area of the selected word line. 4B shows a selection word line voltage (curve 3) close to the selection word line voltage (curve 4) far from the X-decoder 20 after t1 time has elapsed since the read voltage Vread is applied. It can be seen that. Therefore, the distribution of the verification voltage Vver of the selected word line shared by the cells of the page on which the program is made can be made uniform, and the distribution of cells after the program can be narrowed. Also, as a result, the verification voltage Vver applied to the selected word line is set up more quickly and set to the target voltage, thereby reducing the number of program loops, which means that the program speed is increased. .

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

 As described above, the programming method according to the present invention can apply a constant verify voltage to the entire area of the selected word line regardless of the distance to the X-decoder, thereby reducing the probability of over-programming and increasing the program speed. have.

Claims (12)

In the Verification method of a flash memory device, Applying a read voltage Vread to an unselected word line; And applying a verify read voltage (Vver) to the selected word line after a predetermined time from when the read voltage (Vread) is applied to the unselected word line. The method of claim 1, And wherein the predetermined time is a time for which the selected word line is discharged below the verify read voltage Vver. The method of claim 1, And wherein the predetermined time is a time required for the unselected word line to be fixed to the read voltage Vread. The method of claim 3, wherein And wherein the predetermined time is a time for minimizing coupling of the selected word line due to a voltage variation of the unselected word line. A memory cell array having a plurality of word lines; A voltage generator for generating a verify read voltage and a read voltage; An X-decoder for supplying the verify read voltage to a selected word line and the read voltage to an unselected word line during a verify operation; And a program controller configured to control the X-decoder to supply the verify read voltage at a predetermined time delay from the read voltage. The method of claim 5, And the X-decoder discharges the selected word line and the unselected word line to a ground level prior to a verify operation. The method of claim 5, And the predetermined time is a time at which the selected word line is discharged below the verify read voltage Vver. The method of claim 5, And the predetermined time is a time required for the unselected word line to be fixed to the read voltage Vread. In the program method of the flash memory device, Applying a program voltage to the selected word line and a pass voltage to the unselected word line; Discharging the selected word line and the unselected word line; Applying a read voltage (Vread) to the unselected word line; And applying a verify read voltage (Vver) to the selected word line after a predetermined time from when the read voltage (Vread) is applied to the unselected word line. The method of claim 9, And wherein the predetermined time is a time for which the selected word line is discharged below the verify read voltage Vver. The method of claim 9, And wherein the predetermined time is a time required for the unselected word line to be fixed to the read voltage Vread. The method of claim 11, And wherein the predetermined time is a time for minimizing coupling of the selected word line due to a voltage variation of the unselected word line.

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