KR20080060799A - Multi level cell nand flash memory capable of reducing test time and test method thereof - Google Patents

Abstract

A multi level cell NAND flash memory device capable of reducing test time and a test method thereof are provided to reduce test time by generating a program voltage with an initial level corresponding to each data program, in a test mode. A memory cell array(110) has memory cells arranged at crossing area of word lines and bit lines. A row decoder circuit(130) provides a program voltage to a selected word line. A test mode setting part(160) generates a test pattern command in response to a test mode setting signal inputted from the outside. A controller(170) determines an initial level of the program voltage in response to the test pattern command. A word line voltage generation circuit(180) generates a program voltage corresponding to the determined level. A word line driver(190) provides the program voltage to the row decoder circuit. The test pattern command includes specific data pattern information, and the specific data pattern information is information about the initial level of threshold voltage distribution when test data is programmed in the cell.

Description

MULTI LEVEL CELL NAND FLASH MEMORY CAPABLE OF REDUCING TEST TIME AND TEST METHOD THEREOF}

1 is a block diagram of a typical NAND flash memory device including EEPROM cells;

2 is a diagram showing a change in program voltage of a typical NAND flash memory device programmed according to an incremental step pulse program (ISPP) scheme;

3 shows a distribution diagram of a multi-level cell NAND flash memory;

4 is a block diagram of a multilevel cell NAND flash memory device according to an embodiment of the present invention; And,

5 is a diagram illustrating a change in program voltage of a multilevel cell NAND flash memory device according to an exemplary embodiment of the present invention, which is programmed according to an incremental step pulse program (ISPP) scheme.

<Description of the symbols for the main parts of the drawings>

100: multi-level cell NAND flash memory device 110: memory cell array

120: row decoder circuit 130: page buffer circuit

140: Y-gate circuit 150: column decoder circuit

160: test mode setting unit 170: controller

180: word line voltage generation circuit 190: word line driver

The present invention relates to a flash memory device, and more particularly to a multi-level cell NAND flash memory device capable of reducing test time and a test method thereof.

A flash memory device is a kind of EEPROM in which a plurality of memory areas are erased or programmed in one program operation. The flash memory device is composed of a NOR flash memory device and a NAND flash memory device according to the type of logic gate used for each reservoir. The NAND flash memory is divided into a single level cell NAND flash memory and a multi level cell NAND flash memory.

FIG. 1 is a block diagram illustrating a general NAND flash memory device including EEPROM cells.

Referring to FIG. 1, a flash memory device includes a memory cell array 110, a row decoder circuit 120, and a page buffer circuit 130. Rows of the memory cell array 110 are driven by the row decoder circuit 120, and columns are driven by the page buffer circuit 130.

The memory cell array 110 is composed of a plurality of memory cell blocks. Each memory cell block includes a plurality of memory cell strings (“NAND strings”), and each cell string includes a plurality of floating gate transistors M0-M _n-1 that function as memory cells. Include. The channels of the floating gate transistors M0-M _{n -1} of each string are connected in series between the channel of the string select transistor SST and the channel of the ground select transistor GST.

Each block of the memory cell array 110 includes a string select line (SSL), a ground select line (GSL), a plurality of word lines (WL0-WL _{n -1} ), and a plurality of bits. Lines BL0-BL _{n -1} are provided. The string select line SSL is connected to the gates of the string select transistors SST in common. Each word line WL0-WL _{n -1} is commonly connected to control gates of the plurality of corresponding floating gate transistors M0-M _{n -1} . The ground select line GSL is connected to the gates of the plurality of ground select transistors GST in common. Each bit line BL0, ..., or BL _{n-1 is} connected with a corresponding one cell string. The ground select line GSL, the word lines WL0-WL _{n −1} , and the string select line SSL are corresponding to the select signals GS through corresponding block select transistors BST. , Si0-Si _{n -1} , and SS) are respectively accepted. The block select transistors BST are included in the row decoder circuit 120 and are connected to be commonly controlled by the block select control signal BS.

The row decoder circuit 120 selects one word line among the word lines WL0-WL _{n -1} according to the row address information, and the word line voltage according to each operation mode with the selected word line and unselected word lines. Feed them. For example, the row decoder circuit 120 supplies a program voltage to a selected word line in a program operation mode and a pass voltage to unselected word lines. The row decoder circuit 120 supplies a ground voltage GND to a selected word line in a read operation mode and a read voltage to unselected word lines. For this purpose, the row decoder circuit 120 receives selection signals Si0-Si _{n -1} from a word line driver (not shown). The row decoder circuit 120 provides the input selection signals Si0-Si _{n -1} to corresponding word lines WL0-WL _n-1 . The selection signals Si0-Si _{n -1} have a voltage level corresponding to at least one of a program voltage, a pass voltage, and a read voltage, and word lines to corresponding word lines WL0-WL _{n -1} . It is provided as a voltage.

The bit lines BL0-BL _n-1 arranged on the memory cell array 110 are electrically connected to the page buffer circuit 130. The page buffer circuit 130 may be provided with page buffers corresponding to the bit lines BL0-BL _n-1 , and each page buffer may be implemented to share a pair of bit lines. The page buffer circuit 130 may supply a power supply voltage (or a program-inhibited voltage) or a ground voltage (or a program voltage) to bit lines BL0-BL _n-1 according to data to be programmed in a program operation mode. Supply program voltage respectively. In addition, the page buffer circuit 130 detects data from memory cells of the selected word line through the bit lines BL0-BL _n-1 in the read / verify operation mode. The sensing operation of the page buffer circuit 130 determines whether the memory cell is a programmed cell or an erased cell.

As is well known, memory cells of a NAND flash memory are erased and programmed using Fowler-Nordheim tunneling current. Methods of erasing and programming NAND-type flash EEPROMs are titled "NONVOLATILE SEMICONDUCTOR MEMORY" in US Patent Publication No. 5,473,563, and "NONVOLATILE INTEGRATED CIRCUIT MEMORY DEVICES HAVING ADJUSTABLE ERASE ERASE / PROVITY THIS" Each is published. Meanwhile, the flash memory device is programmed by an incremental step pulse programming (ISPP) scheme in order to accurately control threshold voltage distribution of memory cells. An exemplary program method of a flash memory device using an ISPP method is disclosed in US Patent No. 6,266,270 entitled "NON-VOLATILE SEMICOMDUCTOR MEMORY AND PROGRAMMING METHOD OF THE SAME." An example of a circuit for generating a program voltage according to the ISPP method is described in US Patent No. 5,642,309 " AUTO - PROGRAM. CIRCUIT IN A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE " and Korean Patent Publication No. 2002-39744, entitled" FLASH MEMORY DEVICE DAPABLE OF PREVENTING PROGRAM DISTURB AND METHOD OF PROGRAMMING THE SAME. "

2 is a diagram illustrating a change in program voltage of a general NAND flash memory device programmed according to an incremental step pulse program (ISPP) scheme.

3 is a diagram illustrating a distribution diagram of a multi-level cell NAND flash memory.

When the NAND flash memory shown in FIG. 1 is a multi level cell NAND flash memory and each cell can store 3 bits, the distribution of each data state to be stored in the cell is shown in FIG. 3. As it is. If the data is "0", it indicates that the cell is in the erase state. Each cell may be programmed with data "1" through "7".

1 to 3, in a test mode for testing memory cells, a memory device performs a program, verify, and read operation. To test the memory cells, a test mode entry signal is first given to the flash memory, and an address and a specific data pattern are successively input into the flash memory. The particular data pattern is the test data to be programmed into each cell to test the memory cells.

In general, data to be programmed is sequentially delivered to the page buffer circuit 130 in bytes or words. When all data to be programmed, that is, one page of data, is loaded into the page buffer circuit 130, the data stored in the page buffer circuit 130 is stored in the memory cells of the selected page of the memory cell array 110 according to a program command. It is programmed at the same time. In general, as shown in FIG. 3, a cycle in which data is programmed is composed of a plurality of program loops (N-loops), and each program loop is divided into a program section P and a program verification section V. FIG.

In the program period P, memory cells are programmed under a given bias condition in a well known manner. In the ISPP programming method, the program voltages Vpgm1-VpgmN increase in steps as program loops are repeated. The program voltages Vpgm2-VpgmN increase from the predetermined initial program voltage Vpgm1 by a predetermined increment DELTA Vpgm for every program loop. Each program voltage Vpgm1-VpgmN applied to the selected word lines WL0-WL _n-1 is provided at a constant level for a predetermined time (t) for each program loop. In the program verifying period V, whether the memory cells have been programmed to a desired threshold voltage is verified. The above-described program loops (N-loops) are repeatedly performed until all memory cells are programmed within a predetermined number of times. The program verify operation is substantially the same as the read operation except that the read data is not output to the outside. The memory device outputs the programmed data to an external test device (not shown) through a read operation. The test device uses the read data to determine the cell's program error condition.

The level of the threshold voltage of the programmed cell depends on the data being programmed. As illustrated in FIG. 3, the threshold voltage level of the programmed cell is the highest when data "7" is programmed in the memory cell and the lowest when the data "1" is programmed in the memory cell. The program voltage Vpgm1 is an initial voltage level which is a reference when programming data "1". In general, when programming data "1" to "7", all of a plurality of program loops (N-loops) are applied. When programming data "7" into a cell, a high program voltage is needed to ensure that the cell has a high threshold voltage. However, all program operations perform the ISPP scheme from the initial level of the program voltage Vpgm1, and therefore, when data "7" is programmed into the cell, it takes a long time to reach the level of the voltage to be programmed. In addition, since many programs and verifications are performed to reach the level of the voltage to be programmed, the time for testing the memory cells becomes long. Although the case where the data "7" is stored has been described, the same problem occurs when the data "2" to the data "6" are stored, and thus there is a problem that the test time is long.

Accordingly, an object of the present invention is to provide a multi-level cell NAND flash memory device and a test method thereof that can reduce test time.

According to a feature of the present invention for achieving the above object, a multilevel cell NAND flash memory device comprising: a memory cell array having memory cells arranged in an intersection region of word lines and bit lines; A row decoder circuit for providing a program voltage to a selected word line; A test mode setting unit configured to generate a test pattern command in response to a test mode setting signal received from an external device; A controller that determines an initial level of the program voltage in response to the test pattern command; A word line voltage generation circuit for generating a program voltage corresponding to the determined level; And a word line driver for providing the program voltage to the row decoder circuit, wherein the test pattern command includes specific data pattern information, and the specific data pattern information includes a threshold voltage when test data is programmed into the cell. Information about the initial value level of the distribution of.

In this embodiment, the specific data pattern information is provided from the outside to the test mode setting section.

In this embodiment, the specific data pattern information is stored in advance in the test mode setting section.

In this embodiment, the initial value level is information on a minimum value level in the distribution of threshold voltages when test data is programmed in the cell.

In this embodiment, the controller determines the initial level of the program voltage in response to the information about the initial value level.

A multilevel cell NAND flash memory device comprising a memory cell array having memory cells arranged in an intersection region of word lines and bit lines and a row decoder circuit for providing a program voltage to a selected word line according to another aspect of the present invention. A program voltage generation method comprising: generating a test pattern command in response to a test mode setting signal received from an external device; Determining an initial level of program voltage in response to the test pattern command; Generating a program voltage corresponding to the determined level; And providing the program voltage to the row decoder circuit, wherein the test pattern command includes specific data pattern information, wherein the specific data pattern information is a distribution of threshold voltage when test data is programmed in the cell. It is characterized in that the information on the initial value level of.

In this embodiment, the specific data pattern information is received from the outside.

In this embodiment, the specific data pattern information is previously stored therein.

In this embodiment, the initial value level is information on the level of the minimum value in the distribution of threshold voltages when test data is programmed into the cell.

(Example)

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

4 is a block diagram of a multilevel cell NAND flash memory device according to an embodiment of the present invention.

Referring to FIG. 4, the multilevel cell NAND flash memory device 100 according to the present invention includes a memory cell array 110, a row decoder circuit 120, a page buffer circuit 130, a Y-gate circuit 140, The column decoder circuit 150, a test mode setting unit 160, a controller 170, a word line voltage generation circuit 180, and a word line driver 190 are included. The configuration and function of the memory cell array 110, the row decoder circuit 120, and the page buffer circuit 130 shown in FIG. 4 are the same as those of FIG. 1. Therefore, the same reference numerals as in FIG. 1 have been added to them, and a redundant description will be omitted.

The row decoder circuit 120 selects any one of the memory blocks of the memory cell array 110 according to the row address information (not shown) input from the outside, and provides a word provided from the word line voltage generation circuit 180. Transfer the line voltage to the selected row. In this case, the row decoder circuit 120 receives the word line voltage through the word line driver 190. The word line voltages provided by the word line voltage generation circuit 180 include a program voltage, a pass voltage, and a read voltage.

The page buffer circuit 130 is connected to the memory cell array 110 through a plurality of bit lines. The page buffer circuit 130 includes a plurality of page buffers.

The Y-gate circuit 140 and the column decoder circuit 150 select some of the plurality of buffers included in the page buffer circuit 130 in response to column address information (not shown) input from the outside. The data to be programmed is stored in the selected page buffer. The page buffer circuit 130 receives data to be used for the memory cell array 110 from the outside through the Y-gate circuit 140 during a program operation. The page buffer circuit 130 drives columns corresponding to bit lines with a program voltage (for example, a ground voltage) or a program prohibition voltage (for example, a power supply voltage) according to the received data. In the read operation, data read from the page buffer circuit 130 is output to the outside through the Y-gate circuit 140.

The word line driver 190 receives the program voltage Vpgm and the pass voltage from the word line voltage generation circuit 180 and supplies a plurality of selection signals SS, Si, GS to be provided to the row decoder circuit 120. Outputs The selection signals Si output from the word line voltage driver 190 correspond to word lines voltages applied to the corresponding word lines. The word line voltage includes a program voltage to be provided to the selected word line and a pass voltage to be provided to the unselected word line.

In the test mode for testing the memory cell array 110, the multilevel cell NAND flash memory device 100 performs a program, verify, and read operation. The multilevel cell NAND flash memory device 100 receives a test mode setting signal (TMS signal) from the outside through the test mode setting unit 160 to enter the test mode. The test mode setting unit 160 is activated by a test mode setting signal (TMS signal). The activated test mode setting unit 160 generates a test pattern command and provides the generated test pattern command to the controller 170.

In a program operation, a test pattern command includes specific data pattern information. The specific data pattern information is information for determining an initial level of the program voltage Vpgm. The specific data pattern information is input to the test mode setting unit 160 from the outside or stored in the test mode setting unit 160 in advance. The activated test mode setting unit 160 provides specific data pattern information to the controller 170 when receiving specific data pattern information from the outside. When the activated test mode setting unit 160 stores specific data pattern information therein, the activated test mode setting unit 160 provides the specific data pattern information to the controller 170 in response to a test mode setting signal (TMS signal).

Specific data pattern information will be described below.

Referring to FIG. 3, when each cell of the memory cell array 110 of the multi-level cell NAND flash memory 100 can store 3 bits, a distribution of each data state to be stored in the cell is shown in FIG. 3. As shown. 3 is a distribution diagram of threshold voltages when data is programmed into a cell. If the data is "0", it indicates that the cell is in the erase state. Each cell may be programmed with data "1" through "7". As shown in Fig. 3, the level of the threshold voltage of the programmed cell depends on the data being programmed. The threshold voltage level of the programmed cell is highest when data "7" is programmed in the memory cell and lowest when data "1" is programmed in the memory cell. In the distribution diagram when programming the data "7" shown in Fig. 3, the information corresponding to the initial value initial7 is specific data pattern information. Further, the information initial1 to initial6 corresponding to the initial value of the distribution of each of the data "1" to "6" to be programmed are also specific data pattern information.

The specific data pattern information is provided to the test mode setting unit 160 from the outside or stored in advance in the test mode setting unit 160.

The case where the specific data pattern information is data "7" will be described below.

The controller 170 receives a test pattern command provided by the test mode setting unit 160. The test pattern command cmd includes specific data pattern information corresponding to an initial value initial7 in a distribution chart when data "7" is programmed.

The controller 170 performs a program, verify, and read operation to perform a test mode in response to the input test pattern cmd. At this time, during a program operation, a control signal for determining a program voltage having a level corresponding to the initial value initial7 is generated. The generated control signal is provided to the word line voltage generation circuit 180. The word line voltage generation circuit 180 determines the level of the initial value of the program voltage Vpgm in response to the control signal received from the controller 170. The input control signal is a control signal generated in response to the information corresponding to the initial value initial7. Accordingly, the word line voltage generation circuit 180 generates a program voltage Vpgm having an initial value level corresponding to when programming the data "7".

Therefore, when the multilevel cell NAND flash memory device 100 programs data "7" as test data, the multilevel cell NAND flash memory device 100 sets the corresponding program voltage Vpgm as an initial level to perform the program and verify operation by the ISPP method. do.

Although not described in the embodiment of the present invention, even when programming the data "1" to the data "6", the word line voltage generation circuit 180 corresponds to the initial corresponding to the control signal generated by the controller 170, respectively. Generate the program voltage Vpgm at the value level.

The initial level of the program voltage Vpgm generated by the word line voltage generation circuit 180 is the lowest when programming data "1" and the highest when programming data "7".

5 is a diagram illustrating a change in program voltage of a multilevel cell NAND flash memory device according to an embodiment of the present invention programmed according to an incremental step pulse program (ISPP) scheme.

4 and 5, data to be programmed is sequentially transferred to the page buffer circuit 130 in byte or word units. When all data to be programmed, that is, one page of data, is loaded into the page buffer circuit 130, the data stored in the page buffer circuit 130 is stored in the memory cells of the selected page of the memory cell array 110 according to a program command. It is programmed at the same time. A cycle in which data is programmed is composed of a plurality of program loops, each program loop being divided into a program section P and a program verify section V.

The level of the threshold voltage of the programmed cell depends on the data being programmed. The threshold voltage level of the programmed cell is highest when data "7" is programmed in the memory cell and lowest when data "1" is programmed in the memory cell. The program voltage Vpgm1 is an initial voltage level which is a reference when programming data "1". The program voltage Vpgm "7" is an initial voltage level which is a reference when programming the data "7". Therefore, when data "7" is programmed into the memory cell in the test mode, the controller 170 generates a control signal for determining a level corresponding to the initial value initial7 in response to a test pattern cmd. do. The control signal is a control signal generated in response to the information corresponding to the initial value initial7. Therefore, the word line voltage generation circuit 180 receives a control signal from the controller 170 and generates a program voltage Vpgm "7" in response to the received control signal. The program voltage Vpgm "7" is a level corresponding to the initial value initial7 in the distribution diagram when programming the data "7" shown in FIG.

Thus, as shown in Fig. 5, the program loop for programming data "7" is a program loop (N7-loop) section. In the program section P of the program loop N7-loop section, memory cells are programmed under a given bias condition in a well known manner. As the program loops are repeated by the ISPP programming method, the program voltage Vpgm "7" -VpgmN increases step by step. Therefore, the program voltage increases from the predetermined initial program voltage Vpgm "7" by a predetermined increment DELTA Vpgm for every program loop. Each program voltage Vpgm "7" -VpgmN applied to the selected word lines WL0-WL _n-1 is provided at a constant level (t) for a predetermined time for each program loop. In the program verifying period V, whether the memory cells have been programmed to a desired threshold voltage is verified. The program loops described above are repeatedly performed until all memory cells are programmed within a predetermined number of times. The program verify operation is substantially the same as the read operation except that the read data is not output to the outside. The memory device outputs the programmed data to an external test device (not shown) through a read operation. The test device uses the read data to determine the fault condition of the programmed cell.

Although not shown in FIG. 4, a cell test may be performed using a BIST (Built In Self Test) scheme (not shown) without using a test apparatus. When using the beast system, specific data pattern information is generated in the beast scheme and provided to the test mode setting unit 160.

As described above, in the test mode, the number of program loops is reduced when data "7" is programmed than when data "1" is programmed in the memory cell. Therefore, when the specific data pattern is data "7", the multilevel cell NAND flash memory device 100 may reduce the test time.

Although not shown in FIG. 5, even when data "2" to "6" are programmed, as shown in FIG. 3, levels of different initial values are determined according to the levels of the corresponding threshold voltages, respectively. Therefore, the number of program loops is reduced than when programming data "1". When programming data "2" to "6", since the number of program loops is reduced, the multilevel cell NAND flash memory device 100 may reduce the test time.

As a result, the multi-level cell NAND flash memory device 100 according to the present invention may reduce the test time by generating program voltages corresponding to initial value levels when programming data in the test mode.

As described above, the best embodiment has been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the present invention as described above, the multi-level cell NAND flash memory device can reduce the test time by generating a program voltage having a corresponding initial value level when programming data in the test mode.

Claims (9)

A memory cell array having memory cells arranged in an intersection region of word lines and bit lines; A row decoder circuit for providing a program voltage to a selected word line; A test mode setting unit configured to generate a test pattern command in response to a test mode setting signal received from an external device; A controller that determines an initial level of the program voltage in response to the test pattern command; A word line voltage generation circuit for generating a program voltage corresponding to the determined level; And A wordline driver for providing said program voltage to said row decoder circuitry; The test pattern command includes specific data pattern information, and the specific data pattern information is information on an initial value level of a distribution of threshold voltages when test data is programmed in the cell. Memory device. The method of claim 1, The specific data pattern information is provided from the external to the test mode setting unit. The method of claim 1, The specific data pattern information is pre-stored in the test mode setting unit. The method of claim 1, And the initial value level is information on a minimum value level in a distribution of threshold voltages when test data is programmed in the cell. The method of claim 1, And the controller determines the initial level of the program voltage in response to the information on the initial value level. A method of generating a program voltage in a multilevel cell NAND flash memory device comprising: a memory cell array having memory cells arranged in an intersection region of word lines and bit lines; and a row decoder circuit for providing a program voltage to a selected word line: Generating a test pattern command in response to a test mode setting signal received from an external device; Determining an initial level of program voltage in response to the test pattern command; Generating a program voltage corresponding to the determined level; And Providing the program voltage to the row decoder circuit, The test pattern command includes specific data pattern information, and the specific data pattern information is information on an initial value level of a distribution of threshold voltages when test data is programmed in the cell. Program voltage generation method of a memory device. The method of claim 6, And the specific data pattern information is input from an external source of the program voltage generation method of the multi-level cell NAND flash memory device. The method of claim 6, The specific data pattern information is stored in advance in the program voltage generation method, characterized in that the multi-level cell NAND flash memory device. The method of claim 6, And the initial value level is information on a level of a minimum value in a distribution of threshold voltages when test data is programmed in the cell.

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