KR20070050618A - Apparatus and method for driving of liquid crystal display device - Google Patents

Abstract

The present invention relates to a driving apparatus and a driving method of a liquid crystal display device which minimizes wave noise by synchronizing the driving frequency of the liquid crystal panel with the driving frequency of the backlight unit. A driving device of a liquid crystal display according to the present invention includes a liquid crystal panel for displaying an image by adjusting a light transmittance of a liquid crystal cell formed at an intersection of a plurality of data lines and a plurality of gate lines, and irradiating light to the liquid crystal panel. A backlight unit for driving the liquid crystal panel, a timing controller for generating a control signal for controlling the driving unit according to an input synchronization signal, and generating a burst driving frequency using the control signal; And an inverter for driving the backlight unit according to the burst driving frequency.

The present invention includes a source output enable signal, a gate output enable signal, and a gate shift clock by 2 ⁱ by frequency division by driving the inverter to generate a burst drive frequency the liquid crystal panel by the interference between the bursts the driving frequency and the vertical synchronizing signal by such an arrangement It is possible to minimize wave noise generated in the system.

Burst, Inverter, Wave Noise, Vertical Sync Signal, Division

Description

Driving apparatus and driving method of liquid crystal display device {APPARATUS AND METHOD FOR DRIVING OF LIQUID CRYSTAL DISPLAY DEVICE}

1 is a view schematically showing a driving device of a liquid crystal display according to the prior art.

2 is a schematic view of a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 3 is a block diagram schematically illustrating the timing controller shown in FIG. 2. FIG.

4 is a circuit diagram schematically illustrating a burst driving frequency generator shown in FIG. 3;

FIG. 5 is another circuit diagram schematically illustrating the burst driving frequency generator shown in FIG. 3; FIG.

FIG. 6 is a block diagram schematically illustrating the inverter shown in FIG. 2. FIG.

FIG. 7 is a waveform diagram illustrating a driving waveform of the inverter shown in FIG. 6.

<Explanation of Signs of Major Parts of Drawings>

2, 102 liquid crystal panel 4, 104 data driver

6, 106: gate driver 10, 110: timing controller

16, 116: inverter 18, 118: backlight unit

20, 120: system 200: data processing unit

210: data control signal generator 220: gate control signal generator

230: burst driving frequency generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device and a driving method of a liquid crystal display device, and more particularly, to a driving device and a driving method of a liquid crystal display device capable of minimizing wave noise by synchronizing a driving frequency of a liquid crystal panel with a driving frequency of a backlight unit. It is about.

The liquid crystal display displays an image by adjusting light transmittances of liquid crystal cells according to data signals. The liquid crystal display device is implemented in an active matrix type in which switching elements are formed in each cell, and is applied to display devices such as computer monitors, office equipment, and mobile communication terminals. As a switching element used in an active matrix type liquid crystal display device, a thin film transistor (hereinafter, referred to as TFT) is mainly used.

1 is a block diagram schematically illustrating a driving device of a liquid crystal display according to the related art.

Referring to FIG. 1, a driving device of a liquid crystal display according to the related art includes light of a liquid crystal cell Clc formed at an intersection of m data lines DL1 to DLm and n gate lines GL1 to GLn. A liquid crystal panel 2 for displaying an image by adjusting transmittance, a backlight unit 18 for irradiating light to the liquid crystal panel 2, and data for supplying a data signal to the data lines DL1 to DLm; A driver 4, a gate driver 6 for supplying a scan signal to the gate lines GL1 to GLn, a gamma voltage supply unit 8 for supplying a gamma voltage to the data driver 4, and a system ( The timing controller 10 for controlling the data driver 4 and the gate driver 6 by using the synchronization signal supplied from 20 and the voltage supplied from the power supply 12 to the liquid crystal panel 2. DC / DC to generate supplied voltages And a lesion (hereinafter, "DC / DC converting unit" hereinafter) 14, the inverter 16 for driving the backlight unit (18).

The system 20 supplies the vertical / horizontal synchronization signals Vsync and Hsync, the clock signal DCLK, the data enable signal DE, and the data RGB to the timing controller 10.

The DC / DC converter 14 boosts or reduces the voltage of 3.3V input from the power supply 12 to generate the voltage supplied to the liquid crystal panel 2. The DC / DC converter 14 generates a gamma reference voltage, a gate high voltage VGH, a gate low voltage VGL, a driving power source, a common voltage Vcom, and the like.

The liquid crystal panel 2 includes a plurality of liquid crystal cells Clc disposed at intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. Each TFT formed in the liquid crystal cell Clc supplies a data signal supplied from the data lines DL1 to DLm to the liquid crystal cell Clc in response to a scan signal supplied from the gate line GL. In addition, a storage capacitor Cst is formed in each of the liquid crystal cells Clc. The storage capacitor Cst is formed between the pixel electrode of the liquid crystal cell Clc and the front gate line, or is formed between the pixel electrode of the liquid crystal cell Clc and the common electrode line to maintain a constant voltage of the liquid crystal cell Clc. Let's do it.

The timing controller 10 uses the gate driver 6 and the data driver 4 by using the vertical / horizontal synchronization signals Vsync and Hsync, the data enable signal DE, and the clock signal DCLK input from the system 20. Generate a gate control signal GCS and a data control signal DCS. Here, the gate control signal GCS for controlling the gate driver 6 includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output signal (GOE). Etc. are included. The data control signal DCS for controlling the data driver 4 includes a source start pulse (SSP), a source shift clock (SSC), and a source output signal (SOE). And a polarity signal (POL). The timing controller 10 sorts the data RGB supplied from the system 20 and supplies the data RGB to the data driver 4.

The gamma voltage supply unit 8 subdivides the driving power supplied from the DC / DC converter 14 to generate a plurality of gamma voltages for converting data Data supplied to the data driver 4 into analog data signals. Supply to the data driver 4.

The data driver 4 converts the gamma voltage (data signal) corresponding to the grayscale value of the data Data from the timing controller 10 in response to the data control signal DCS from the timing controller 10. The gamma voltage is supplied to the data lines DL1 to DLm.

The gate driver 6 sequentially supplies a scan pulse, that is, a gate high voltage VGH, to the gate lines GL1 to GLn in response to the gate control signal GCS from the timing controller 10. The horizontal line of the liquid crystal panel 2 is selected.

The inverter 16 supplies the lamp driving power supply Vbl for driving the backlight unit 18 to the backlight unit 18. The backlight unit 18 generates light corresponding to the lamp driving power Vbl supplied from the inverter 16 and supplies the light to the liquid crystal panel 2.

On the other hand, the backlight unit 18 is generally driven in a continuous mode. The backlight unit 18 in the continuous mode has a disadvantage in that the current consumption is high because the lamp is continuously maintained. In order to solve such a problem, the backlight unit 18 of the burst mode has been recently used.

The backlight unit 18 in the burst mode has an advantage of reducing the current consumption by driving the lamp in an on state and an off state of a predetermined period.

To this end, in order to drive the backlight unit 18 in the burst mode, the inverter 16 pulse width modulates the burst driving frequency Bfreq, which is set and supplied from the outside, to the lamp driving power source Vbl which is a pulse width modulation signal. Is supplied to the backlight unit 18.

However, in the driving device of the conventional liquid crystal display, the vertical synchronization signal Vsync and the burst driving frequency Bfreq are designed separately. Accordingly, when interference occurs between the vertical synchronization signal Vsync and the burst driving frequency Bfreq, there is a problem in which a wavy noise such as a horizontal wave occurs in the liquid crystal panel 2. have.

Accordingly, in order to solve the above problems, the present invention is to provide a driving device and a driving method of the liquid crystal display device to minimize the wave noise by synchronizing the driving frequency of the liquid crystal panel and the driving frequency of the backlight unit.

The driving device of the liquid crystal display according to the embodiment of the present invention for achieving the above object is a liquid crystal for displaying an image by adjusting the light transmittance of the liquid crystal cell formed at the intersection of the plurality of data lines and the plurality of gate lines A panel, a backlight unit for irradiating light to the liquid crystal panel, a driver for driving the liquid crystal panel, a control signal for controlling the driver according to an input synchronization signal, and generating the control signal. And a timing controller for generating a burst driving frequency using the inverter, and an inverter for driving the backlight unit according to the burst driving frequency.

The driving unit may include a data driver for supplying a data signal to the data lines according to the control signal, and a gate driver for supplying a scan signal to the gate lines according to the control signal.

The timing controller may include a data processor for arranging input data and supplying the data driver to the data driver, a data control signal generator for generating a data control signal including a source output enable signal for controlling the data driver, and A gate control signal generator for generating a gate control signal including a gate output enable signal and a gate shift clock for controlling a gate driver, the source output enable signal, the gate output enable signal, and the gate shift clock It characterized in that it comprises a burst driving frequency generating unit for generating the burst driving frequency using any one of.

The burst driving frequency generation unit divides any one of the source output enable signal, the gate output enable signal, and the gate shift clock by 2 ⁱ (where i is a positive integer of 2 or more) to generate the burst driving frequency. i flip-flops are provided.

The i flip-flops may be D flip-flops or T flip-flops connected in series.

A driving method of a liquid crystal display according to an exemplary embodiment of the present invention is directed to a liquid crystal display including a liquid crystal panel which displays an image by controlling light transmittance of a liquid crystal cell formed at an intersection of a plurality of data lines and a plurality of gate lines. The control method may further include generating a control signal according to an input synchronization signal and generating a burst driving frequency using the control signal, and supplying a scan signal to the gate lines according to the control signal. Supplying a data signal to the light source, generating a lamp driving power according to the burst driving frequency, and irradiating light to the liquid crystal panel by driving a backlight unit according to the lamp driving power. It features.

The generating of the control signal and the burst driving frequency may include generating a data control signal including a source output enable signal for supplying a data signal to the data lines, and supplying a scan signal to the gate lines. Generating a gate control signal including a gate output enable signal and a gate shift clock to drive the burst using any one of the source output enable signal, the gate output enable signal, and the gate shift clock; Generating a frequency.

Generating the burst driving frequency is connected in series i of using the flip-flop of the source output enable signal and a gate output enable signal and the gate shift any of the 2 ⁱ (stage of the clock, i is 2 or more Positive integer) to generate the burst drive frequency.

The i flip-flops are D flip-flops or T flip-flops.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

FIG. 2 is a view illustrating an optical device of a liquid crystal cell Clc formed at an intersection of m data lines DL1 to DLm and n gate lines GL1 to GLn. A liquid crystal panel 102 for displaying an image by adjusting transmittance, a backlight unit 118 for irradiating light to the liquid crystal panel 102, a driver for driving the liquid crystal panel 102, and a system 120. A timing controller 110 for generating a control signal for controlling the driving unit according to the synchronization signal supplied from the controller and generating a burst driving frequency Bfreq using the control signal, and a burst driving frequency from the timing controller 110. An inverter 116 for driving the backlight unit 118 according to Bfreq is provided.

Also, in the driving apparatus of the liquid crystal display according to the exemplary embodiment of the present invention, the driving unit includes a data driver 104 for supplying data signals to the data lines DL1 to DLm according to a control signal, and a gate line according to the control signal. The gate driver 106 for supplying the scan signal to the GL1 to GLn, the gamma voltage supply unit 108 for supplying the gamma voltage to the data driver 104, and the voltage supplied from the power supply 112. And a DC / DC converter (hereinafter, referred to as a “DC / DC converter”) 114 for generating voltages supplied to the liquid crystal panel 102 by using the same.

The system 120 supplies the vertical / horizontal synchronization signals Vsync and Hsync, the clock signal DCLK, the data enable signal DE, and the data RGB to the timing controller 110.

The DC / DC converter 114 boosts or depressurizes a voltage of 3.3 V input from the power supply 112 to generate a voltage supplied to the liquid crystal panel 102. The DC / DC converter 114 generates a gamma reference voltage, a gate high voltage VGH, a gate low voltage VGL, a driving power source and a common voltage Vcom.

The liquid crystal panel 102 includes a plurality of liquid crystal cells Clc disposed in a matrix at the intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. Each TFT formed in the liquid crystal cell Clc supplies a data signal supplied from the data lines DL1 to DLm to the liquid crystal cell Clc in response to a scan signal supplied from the gate line GL. In addition, a storage capacitor Cst is formed in each of the liquid crystal cells Clc. The storage capacitor Cst is formed between the pixel electrode of the liquid crystal cell Clc and the front gate line, or is formed between the pixel electrode of the liquid crystal cell Clc and the common electrode line to maintain a constant voltage of the liquid crystal cell Clc. Let's do it.

The timing controller 110 uses the gate driver 106 and the data driver 104 by using the vertical / horizontal synchronization signals Vsync and Hsync, the data enable signal DE, and the clock signal DCLK input from the system 120. ) Generates a control signal for controlling), and generates a burst driving frequency Bfreq using the generated control signal. The timing controller 110 arranges the data RGB supplied from the system 120 and supplies the data RGB to the data driver 104.

To this end, the timing controller 110 includes a data processor 200 for arranging data RGB supplied from the system 120 as shown in FIG. 3; Data and gate control for generating data and gate control signals DCS and GCS using the clock signal DCLK, data enable signal DE, and horizontal and vertical synchronization signals Hsync and Vsync from the system 120. Signal generators 210 and 220; The burst driving frequency generator 230 generates a burst driving frequency Bfreq using the data or the gate control signals DCS and GCS.

The data processor 200 aligns the data RGB from the system 120 to be suitable for driving the liquid crystal panel 102, and supplies the aligned data to the data driver 104 through a bus line. .

The data control signal generator 210 uses a clock signal MCLK, a data enable signal DE, horizontal and vertical synchronization signals Hsync and Vsync, and a source start pulse SSP and a source shift clock. A data control signal DCS including a source shift clock SSC, a polarity signal POL, and a source output enable signal SOE is generated and supplied to the data driver 104.

The gate control signal generator 220 uses a data enable signal DE, horizontal and vertical synchronization signals Hsync and Vsync, and includes a gate start pulse GSP and a gate shift clock GSC. ) And a gate control signal GCS including a gate output enable (GOE) is supplied to the gate driver 106.

The burst driving frequency generator 230 may include a source output enable signal SOE from the data control signal generator 210 or a gate output enable signal from the gate control signal generator 220 as shown in FIG. 4. I T flip-flops T1 to Ti are connected in series to divide the GOE or gate shift clock GSC with i (where i is a positive integer of 2 or more).

One of the source output enable signal SOE, the gate output enable signal GOE, and the gate shift clock GSC is input to the trigger terminal T of the first T flip-flop T1, and the output terminal Q is provided. ) Is connected to the trigger terminal T of the second T flip-flop T2. The trigger terminal T of each of the second to i T flip-flops T2 to Ti is connected to the output terminal Q of the previous T flip flops T1 to Ti-1.

Each of the i T flip-flops T1 to Ti divides the input signal by 1/2 and outputs the divided input signals. Accordingly, the burst driving frequency generation unit 230 divides any one of the input source output enable signal SOE, the gate output enable signal GOE, and the gate shift clock GSC by 2 ⁱ to generate a burst driving frequency ( ⁱ ). Bfreq).

Meanwhile, the burst driving frequency generator 230 may be a source output enable signal SOE from the data control signal generator 210 or a gate output in from the gate control signal generator 220 as shown in FIG. 5. I-D flip-flops D1 to Di may be provided in series to divide the enable signal GOE or the gate shift clock GSC with i (where i is a positive integer of 2 or more).

)에 접속된다.One of a source output enable signal SOE, a gate output enable signal GOE, and a gate shift clock GSC is input to the clock terminal C of the first D flip-flop D1, and the output terminal Q is provided. ) Is connected to the clock terminal C of the second D flip-flop D2. In addition, the input terminal D of the first D flip-flop D1 has its inverted output terminal (

) Is connected.

)에 접속된다.The clock terminal T of each of the second to i-th D flip-flops D2 to Di is connected to the output terminal Q of the previous D flip-flops D1 to Di-1, and the input terminal D has its own terminal. Invert output terminal

) Is connected.

Each of the i D flip-flops D1 to Di divides the input signal by two and outputs them. Accordingly, the burst driving frequency generation unit 230 divides any one of the input source output enable signal SOE, the gate output enable signal GOE, and the gate shift clock GSC by 2 ⁱ to generate a burst driving frequency ( ⁱ ). Bfreq).

Accordingly, the burst driving frequency Bfreq may be represented by Equation 1 below according to any one of the source output enable signal SOE, the gate output enable signal GOE, and the gate shift clock GSC and the vertical synchronization signal Vsync. Is generated as:

In Equation 1, the input signal is a source output enable signal (SOE), a gate output enable signal (GOE) and a gate shift clock (GSC) generated when the resolution of the liquid crystal panel 102 is SXGA (1280 × 1024). ) Is the frequency of either.

As shown in Equation 1, since the input signal is generated during one period of the vertical synchronization signal Vsync, the burst driving frequency Bfreq corresponds to the division of the result of the multiplication operation of the vertical synchronization signal Vsync and the input signal. is determined by dividing by ⁱ .

Therefore, even when the vertical synchronization signal Vsync changes, the burst driving frequency Bfreq is generated by dividing the result of the multiplication operation of the vertical synchronization signal Vsync and the input signal by 2 ⁱ as shown in Equation 1, so that the burst driving frequency Bfreq It is generated as shown in Table 1 below. In this case, the burst driving frequency Bfreq is synchronized with the source output enable signal SOE, the gate output enable signal GOE, and the gate shift clock GSC, and becomes an integer multiple of the vertical synchronization signal Vsync. Here, the burst driving frequency Bfreq may be generated as shown in Table 1 below, but is preferably generated in the range of 224 kHz to 600 kHz.

 Vsync (Hz)  Input Signal (Hz) Burst Drive Frequency (Bfreq) (Hz)  2 minutes  3 minutes  4 minutes  5 minutes  6 minutes  7 minutes  8 minutes  9 minutes  10 minutes 56 1024 14336 7168 3584 1792 896 448 224 112 56 60 1024 15360 7680 3840 1920 960 480 240 120 60 70 1024 17920 8960 4480 2240 1120 560 280 140 70 72 1024 18432 9216 4608 2304 1152 576 288 144 72 75 1024 19200 9600 4800 2400 1200 600 300 150 75

The gamma voltage supply unit 108 subdivides the driving power supplied from the DC / DC converter 114 to generate a plurality of gamma voltages for converting data supplied to the data driver 104 into an analog data signal. Supply to the data driver 104.

The data driver 104 converts the gamma voltage (data signal) corresponding to the gray scale value of the data Data from the timing controller 110 in response to the data control signal DCS from the timing controller 110. The gamma voltage is supplied to the data lines DL1 to DLm.

The gate driver 106 sequentially supplies a scan pulse, that is, a gate high voltage VGH, to the gate lines GL1 to GLn in response to the gate control signal GCS from the timing controller 110. The horizontal line of the liquid crystal panel 102 is selected.

The inverter 116 supplies the lamp driving power Vbl for driving the backlight unit 118 to the backlight unit 118 according to the burst driving frequency Bfreq supplied from the timing controller 110.

FIG. 6 is a block diagram schematically showing the inverter 116 shown in FIG. 2, and FIG. 7 is a waveform diagram showing a drive waveform of the inverter 116.

6 and 7, the inverter 116 includes a pulse width modulator 300 for generating a pulse width modulated signal PP using a burst driving frequency Bfreq and a reference voltage Vref, and a backlight. A driving frequency generator 310 generating a driving frequency DF for driving the unit 118 and a driving frequency MDW are generated by mixing the driving frequency DF and the pulse width modulation signal PP. The mixer 320 and a power amplifier 330 for amplifying the mixed driving frequency MDW by the lamp driving power Vbl and supplying the mixed driving frequency MDW to the backlight unit 118.

The pulse width modulator 300 includes an integrator 302 and a comparator 304.

The integrator 302 integrates the burst driving frequency Bfreq to generate a triangular wave CW and supplies it to the comparator 304.

The comparator 304 pulse-modulates the triangular wave CW in accordance with the reference voltage Vref to generate a pulse width modulated signal PP and supplies it to the mixer MDW.

The driving frequency generator 310 generates a driving frequency DF of 30 Hz to 70 Hz for driving the backlight unit 118 and supplies it to the mixing unit 320.

The mixing unit 320 generates a mixed driving frequency MDW by mixing the driving frequency DF from the mixing unit 320 in the high period of the pulse width modulation signal PP from the comparator 304 and generating the mixed driving frequency MDW. The mixed drive frequency MDW is supplied to the power amplifier 330.

The power amplifier 330 amplifies the mixed driving frequency MDW from the mixing unit 320 to the lamp driving power Vbl to supply the backlight unit 118 so that the backlight unit 118 can be driven.

The backlight unit 118 generates light corresponding to the lamp driving power Vbl supplied from the inverter 116 and supplies the light to the liquid crystal panel 102. Here, the backlight unit 118 may be configured as a single cold cathode fluorescent lamp or an external electrode fluorescent lamp, and may include a plurality of cold cathode fluorescent lamps or external electrode fluorescent lamps. Can be configured.

In addition, the backlight unit 118 further includes a plurality of optical members for improving the brightness of the light generated from the lamp.

As described above, the driving device and driving method of the liquid crystal display according to the exemplary embodiment of the present invention include a source output generated by vertical / horizontal synchronization signals Vsync and Hsync, a data enable signal DE, and a clock signal DCLK. The burst driving frequency Bfreq is generated using any one of the enable signal SOE, the gate output enable signal GOE, and the gate shift clock GSC.

Accordingly, in the present invention, the burst driving frequency Bfreq is synchronized with the source output enable signal SOE, the gate output enable signal GOE, and the gate shift clock GSC, and the integer multiple of the vertical synchronization signal Vsync is increased. Therefore, due to the interference between the burst driving frequency Bfreq and the vertical synchronization signal Vsync, wave noise such as a horizontal wave generated in the liquid crystal panel 102 may be minimized. As a result, the present invention synchronizes the burst driving frequency Bfreq with the scan of the gate line so that the wave noise is stopped and invisible.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention It will be apparent to those skilled in the art.

Drive device and a drive method of a liquid crystal display according to the embodiment of the present invention as described above, by driving the inverter divides the source output enable signal, a gate output enable signal, and a gate shift clock 2 ⁱ generates a burst drive frequency It is possible to minimize wave noise generated in the liquid crystal panel due to the interference between the burst driving frequency and the vertical synchronization signal. As a result, in the present invention, since the burst driving frequency maintains the ratio of multiples to the vertical synchronization signal, the scan of the gate line and the burst driving frequency are synchronized at all resolutions of the liquid crystal panel, so that the wave noise is stopped and not visible.

Claims (11)

A liquid crystal panel which displays an image by adjusting light transmittance of a liquid crystal cell formed at an intersection of the plurality of data lines and the plurality of gate lines; A backlight unit for irradiating light onto the liquid crystal panel; A driving unit for driving the liquid crystal panel; A timing controller for generating a control signal for controlling the driving unit according to an input synchronization signal and for generating a burst driving frequency using the control signal; And an inverter for driving the backlight unit according to the burst driving frequency. The method of claim 1, The driving unit, A data driver for supplying a data signal to the data lines according to the control signal; And a gate driver for supplying scan signals to the gate lines according to the control signal. The method of claim 2, The timing controller; A data processor for sorting input data and supplying the data to the data driver; A data control signal generator configured to generate a data control signal including a source output enable signal for controlling the data driver; A gate control signal generator configured to generate a gate control signal including a gate output enable signal and a gate shift clock for controlling the gate driver; And a burst driving frequency generator configured to generate the burst driving frequency by using any one of the source output enable signal, the gate output enable signal, and the gate shift clock. The method of claim 3, wherein The burst driving frequency generation unit divides any one of the source output enable signal, the gate output enable signal, and the gate shift clock by 2 ⁱ (where i is a positive integer of 2 or more) to generate the burst driving frequency. A drive device for a liquid crystal display device comprising i flip-flops. The method of claim 4, wherein And said i flip-flops are D flip-flops or T flip-flops connected in series. The method of claim 4, wherein I is a driving range of the liquid crystal display device, characterized in that 3 to 10 range. A liquid crystal display comprising a liquid crystal panel for displaying an image by adjusting a light transmittance of a liquid crystal cell formed at an intersection of a plurality of data lines and a plurality of gate lines. Generating a control signal according to an input synchronization signal and generating a burst driving frequency using the control signal; Supplying a data signal to the data lines in synchronization with supplying a scan signal to the gate lines according to the control signal; Generating a lamp driving power according to the burst driving frequency; And driving a backlight unit according to the lamp driving power to irradiate light to the liquid crystal panel. The method of claim 7, wherein Generating the control signal and the burst driving frequency, Generating a data control signal comprising a source output enable signal for supplying a data signal to the data lines; Generating a gate control signal including a gate output enable signal and a gate shift clock for supplying a scan signal to the gate lines; And generating the burst driving frequency by using any one of the source output enable signal, the gate output enable signal, and the gate shift clock. The method of claim 8, Generating the burst driving frequency is connected in series i of using the flip-flop of the source output enable signal and a gate output enable signal and the gate shift any of the 2 ⁱ (stage of the clock, i is 2 or more Positive integer) by dividing to generate the burst driving frequency. The method of claim 9, And the i flip flops are D flip flops or T flip flops. The method of claim 9, I is in the range of 3 to 10, the driving method of the liquid crystal display device.

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