KR20070050593A - Image sensor and method for manufacturing the same - Google Patents

Abstract

The present invention is to provide an image sensor and a method for manufacturing the same, which can solve the noise by increasing the capacitance of the floating diffusion region, a photodiode, a floating diffusion region for receiving and storing the photocharge generated from the photodiode and And an image sensor including at least one capacitor connected in parallel with the floating diffusion region to increase the capacitance of the floating diffusion region, and a first transistor for amplifying and outputting the charge accumulated in the floating diffusion region and the capacitor. To provide. And a photodiode formed in the substrate, a floating diffusion region formed in the substrate to accumulate charges generated in the photodiode, and an amplification of the charge accumulated in the floating diffusion region connected to the floating diffusion region. A first interlayer insulating film formed through a gate electrode formed through the plurality of contact plugs respectively connected to the gate electrode and the floating diffusion region to cover the gate electrode, and on the first interlayer insulating film to be connected to the contact plug. An image sensor includes a lower electrode of a formed capacitor, a second interlayer insulating layer formed on the first interlayer insulating layer to cover the lower electrode, and an upper electrode of a capacitor formed on the second interlayer insulating layer.

 Image sensor, photo diode, floating diffusion, capacitance, capacitor, parallel connection.

Description

Image sensor and manufacturing method thereof {IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME}

1 is a circuit diagram showing a unit pixel of a general CMOS image sensor.

FIG. 2 is a plan view illustrating unit pixels of a CMOS image sensor corresponding to FIG. 1. FIG.

3 is a cross-sectional view taken along the line II ′ of FIG. 2;

4 is a circuit diagram illustrating a unit pixel of a CMOS image sensor according to an exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view of a CMOS image sensor corresponding to FIG. 4. FIG.

FIG. 6 is a cross-sectional view of a CMOS image sensor that does not include a second capacitor C ₂ , such as 'A' in FIG. 4.

7 is a cross-sectional view illustrating a method of manufacturing a CMOS image sensor according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

T: transfer transistor R: reset transistor

D: drive transistor S: select transistor

C ₁ , C ₂ : Capacitor 110: Substrate

UP ₁ , UP ₂ , UP ₃ : first to third regions 111: device isolation layer

114: gate electrode 116: floating diffusion region

118: first interlayer insulating film

119a, 119b, and 119c: first to third contact plugs

120: first metal layer 120a, 125: lower electrode of the capacitor

121: second interlayer insulating film 122, 127: upper electrode of capacitor

123: third interlayer insulating film 124a, 124b: fourth and fifth contact plugs

125: fourth interlayer insulating film

The present invention relates to an image sensor and a method of manufacturing the same, and more particularly, to a complementary metal-oxide-semiconductor (CMOS) image sensor for controlling the capacitance of a floating diffusion region and a method of manufacturing the same.

Recently, the demand of digital cameras is exploding with the development of video communication using the Internet. Moreover, the demand for small camera modules increases as the popularity of mobile communication terminals such as PDAs equipped with cameras, International Mobile Telecommunications-2000 (IMT-2000), Code Division Multiple Access (CDMA) terminals, etc. increases. Doing.

As a camera module, an image sensor module using a Charge Coupled Device (CCD) or a Complementary Metal-Oxide-Semiconductor (CMOS) image sensor, which are basic components, is widely used.

In general, a CMOS image sensor implements an image by forming a photodiode and a MOS transistor in a unit pixel and sequentially detecting a signal in a switching manner. Currently, a unit pixel of most CMOS image sensors is implemented. One photodiode and four NMOS transistors in which control signals Tx, Rx, Dx, and Sx are respectively input to the gate are configured.

1 is a circuit diagram illustrating a unit pixel of a general CMOS image sensor.

Referring to FIG. 1, a unit pixel of a CMOS image sensor includes one photo diode that receives light and generates photocharges, and a controller for controlling the photocharges of the photodiode. At this time, the control unit amplifies the transfer transistor (T) for transporting the photocharge collected from the photodiode to the floating diffusion region, the reset transistor (R) for resetting the potential of the floating diffusion region, and the potential of the floating diffusion region. In order to output a signal amplified from the drive transistor (D) and the drive transistor (D), which functions as a source follower buffer amplifier (S), it is composed of a switching transistor (S) . Here, the other transistors not shown are load transistors to which a bias voltage is applied.

The unit pixel of the CMOS image sensor uses a native NMOSFET to detect light in the visible wavelength range of the photodiode, and then transfers the detected photocharge to the floating diffusion region, that is, the gate of the drive transistor D. Output as an electrical signal at the output terminal (Vout).

FIG. 2 is a plan view illustrating unit pixels of a CMOS image sensor corresponding to FIG. 1, and FIG. 3 is a cross-sectional view taken along the line II ′ of FIG. 2. Hereinafter, a CMOS image sensor according to the related art will be briefly described with reference to FIG. 3.

Referring to FIG. 3, a conventional CMOS image sensor includes a photodiode (not shown) in a substrate 10 in an active region in which an isolation layer 11 for defining a field region and an active region is formed. ) And floating diffusion regions 16 (FD) are formed, and four transistor gate electrodes (not shown) including a gate electrode 14 for a drive transistor are formed on the substrate 10, respectively. Here, the gate electrode 14 for the drive transistor is electrically connected to the floating diffusion region 16 through one metal wiring 20. In addition, the metal wiring 20 is connected to the gate electrode 14 and the floating diffusion region 16 for the drive transistor through the first and second contact plugs 19a and 19b, respectively.

However, the CMOS image sensor according to the related art has a transfer transistor T when the C _FD has a significantly smaller value than the C _PD , that is, when the capacitance of the floating diffusion region is significantly smaller than that of the photodiode. Of the photodiode and the electrons in the photodiode are not transferred to the floating diffusion region, and some remain in the channel region of the photodiode and / or the transfer transistor T even when the gate of the circuit is turned on. ) There is a problem that occurs. Such a charge sharing phenomenon causes unnecessary noise such as flicker noise, which causes deterioration of image quality of the image sensor. Therefore, to solve this noise, the C _FD value must be increased.

Accordingly, the present invention has been made to solve the above problems of the prior art, and to provide an image sensor and a method of manufacturing the same that can solve the noise by increasing the capacitance of the floating diffusion region.

According to a first aspect of the present invention, there is provided a photodiode, a floating diffusion region for receiving and storing photocharges generated from the photodiode, and the floating to increase capacitance of the floating diffusion region. An image sensor including at least one capacitor connected in parallel with a diffusion region, and a first transistor for amplifying and outputting the charge accumulated in the floating diffusion region and the capacitor.

In the present invention according to the first aspect described above, when at least two or more of the capacitors are connected, they are connected in parallel with each other.

According to a second aspect of the present invention, there is provided a photodiode formed in a substrate, a floating diffusion region formed in the substrate so as to accumulate charge generated in the photodiode, and a floating diffusion region. A first interlayer insulating film formed through a gate electrode formed on the substrate to amplify the charge accumulated in the floating diffusion region, and a plurality of contact plugs respectively connected to the gate electrode and the floating diffusion region to cover the gate electrode. A lower electrode of a capacitor formed on the first interlayer insulating film so as to be connected to the contact plug, a second interlayer insulating film formed on the first interlayer insulating film to cover the lower electrode, and an upper portion of the second interlayer insulating film. Provided is an image sensor including an upper electrode of a capacitor.

In addition, the present invention according to the third aspect for achieving the above object, each of the substrate defined by the first to third region where the first to third pixels are to be formed, and in the substrate of the first to third region, respectively A photodiode formed, a floating diffusion region formed in the substrate so as to accumulate charges generated in the photodiode, and a gate electrode formed on the substrate so as to amplify the charge accumulated in the floating diffusion region connected to the floating diffusion region. A first interlayer insulating film formed to cover the entire structure including the gate electrode, a first contact plug formed in the first interlayer insulating film to be connected to the gate electrode, and the first interlayer insulating film to be connected to the floating diffusion region. Second and third contact plugs formed in the insulating film, and the first to third contact plugs of the first to third regions, respectively. A first metal layer formed on the first interlayer insulating film to be connected to the first interlayer insulating film, the first metal layer being separated from each other and connected to the second and third contact plugs, and a second interlayer insulating film formed to cover the first metal layer; A second metal layer formed on the second interlayer insulating film in the second and third regions, a third interlayer insulating film formed on an entire surface of the second interlayer insulating film so as to cover the second metal layer, and Fourth and fifth contact plugs formed in the third interlayer insulating film in the third region so as to be connected to the second metal layer and the first metal layer connected to the third contact plug, and the fourth and fifth contact plugs; An image sensor includes a third metal layer formed on the third interlayer insulating film in the third region so as to be connected, and a fourth interlayer insulating film and a fourth metal layer sequentially stacked on the third metal layer.

In addition, according to a fourth aspect of the present invention, there is provided a method of forming a plurality of gate electrodes on a substrate defined by first to third regions in which first to third pixels are to be formed. Forming a photodiode and a floating diffusion region in the substrate in the first to third regions, respectively, forming a first interlayer insulating film on the substrate to cover the gate electrode, and forming the gate in the first interlayer insulating film. Forming a first contact plug connected to a gate electrode for amplifying the charge accumulated in the floating diffusion region, and second and third contact plugs connected to the floating diffusion region, respectively; Depositing a first metal layer on the first interlayer insulating film including a third contact plug, and separating the first metal layer from each other in the third region Etching the first metal layer in a region corresponding to the formed inter-connected second and third contact plug regions, forming a second interlayer dielectric layer on the first interlayer dielectric layer to cover the first metal layer; Forming a second metal layer on the second interlayer insulating film in the second and third regions, respectively, and forming a third interlayer on the second interlayer insulating film in the first to third regions so as to cover the second metal layer. Forming an insulating film, and forming fourth and fifth contacts in the third interlayer insulating film of the third region so as to be connected to the second metal layer of the third region and the first metal layer connected to the third contact plug, respectively. Forming a plug, forming a third metal layer on the third interlayer insulating film in the third region so as to be connected to the fourth and fifth contact plugs, and on the third metal layer in the third region Fourth layer in turn Providing an insulating film and a method of manufacturing an image sensor, comprising the step of forming the metal layer 4.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and if a layer is said to be on another layer or substrate it may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

4 is a circuit diagram illustrating a unit pixel of a CMOS image sensor according to an exemplary embodiment of the present invention. Referring to FIG. 4, a CMOS image sensor according to an exemplary embodiment of the present invention includes a photodiode (PD), a floating diffusion region for receiving and storing photocharges generated from the photodiode, and a capacitance (C _FD) of the floating diffusion region. ) At least one capacitor C ₁ , C ₂ (hereinafter referred to as first and second capacitors) connected in parallel with the floating diffusion region, and the floating diffusion region and the first and second capacitors C ₁ , And a drive transistor D for amplifying and outputting the charge accumulated in the C ₂ ).

In addition, a reset transistor (R) connected between the power supply voltage terminal (V _DD ) and the floating diffusion region to reset the floating diffusion region, and a select for performing a switching role to output the amplified signal through the drive transistor (D). The semiconductor device may further include a transfer transistor T connected between the photodiode and the floating diffusion region to transfer the photocharges of the transistor S and the photodiode to the floating diffusion region. Here, the other transistors not shown are load transistors to which a bias voltage is applied.

In particular, according to the embodiment of the present invention, when two or more capacitors are connected, they are connected in parallel with each other, so that the first and second capacitors C ₁ and C ₂ are connected in parallel with each other.

In FIG. 4, a CMOS image sensor having a 4-Tr structure is illustrated as an example, but is applicable to all image sensors including a photodiode and a floating diffusion region. That is, it is also applicable to a CMOS image sensor having a 3-Tr structure. The CMOS image sensor having a 3-Tr structure does not include a transfer transistor (T). In addition, the unit pixel of the CMOS image sensor having a 4-Tr structure includes one photodiode and four NMOS transistors (T, R, respectively) in which control signals Tx, Rx, Dx, and Sx are respectively input to the gate. D, S).

Meanwhile, the CMOS image sensor according to the embodiment of the present invention has only _one first capacitor C ₁ to increase the capacitance C _FD of the floating diffusion region which is significantly smaller than the capacitance C _PD of the photodiode. It may be formed (not forming the second capacitor C ₂ , such as 'A').

That is, the image sensor according to the embodiment of the present invention may increase the capacitance C _FD of the floating diffusion region by additionally connecting at least one capacitor C ₁ and C ₂ to the floating diffusion region in parallel. Through this, the electrons in the photodiode cannot be transferred to the floating diffusion region, and some of the charge sharing phenomenon in which some of the electrons remain in the channel region of the photodiode and / or the transfer transistor T can be prevented. have.

5 is a cross-sectional view illustrating a CMOS image sensor corresponding to FIG. 4. That is, a cross-sectional view of a CMOS image sensor including both first and second capacitors C ₁ and C ₂ formed in parallel to the floating diffusion region as shown in FIG. 4.

Referring to FIG. 5, a floating diffusion region 116 (FD) is formed in the substrate 110 on which the device isolation layer 111 is formed to accumulate charges generated in the photodiode and the photodiode. In addition, the gate electrode 114 of the drive transistor is formed on the substrate 110 to be electrically connected to the floating diffusion region 116 to amplify the charge accumulated in the floating diffusion region 116, and the gate electrode 110 is formed on the substrate 110. A plurality of contact plugs 119a, 119b, and 119c (hereinafter, referred to as first to third contact plugs) connected to the gate electrode 114 and the floating diffusion region 116 so as to cover the electrode 114, respectively. One interlayer insulating film 118 is formed.

A lower electrode 120a (hereinafter referred to as a first lower electrode) of a capacitor is formed on the first interlayer insulating layer 118 at the same time as the first and second contact plugs 119a and 119b. Preferably, the metal layer 120 connected to the third contact plug 119c is further formed on the same layer as the first lower electrode 120a so as to be separated from the first lower electrode 120a on the first interlayer insulating layer 118. do.

In addition, an upper electrode 122 (hereinafter, referred to as a first upper electrode) of a capacitor is formed on the second interlayer insulating layer 121 formed to cover both the first lower electrode 120a and the metal layer 120. As a result, a first capacitor C ₁ having a structure in which the first lower electrode 120a / the second interlayer insulating layer 121 / the first upper electrode 122 are sequentially stacked is formed.

In addition, a third interlayer insulating layer 123 is formed on an entire surface of the second interlayer insulating layer 121 to cover the first upper electrode 122, and the first upper electrode 122 and the third interlayer insulating layer 123 are formed in the third interlayer insulating layer 123. The fourth and fifth contact plugs 124a and 124b are formed to be connected to the metal layer 120, respectively.

The lower electrode 125 (hereinafter referred to as a second lower electrode) / fourth interlayer insulating film 126 / of the capacitor is connected to the fourth and fifth contact plugs 124a and 124b on the third interlayer insulating film 123. A second capacitor C ₂ having a structure in which an upper electrode 127 (hereinafter referred to as a second upper electrode) of the capacitor is sequentially stacked is formed.

As a result, first and second capacitors C ₁ and C ₂ connected in parallel with the floating diffusion region 116 and in parallel therewith are completed. By forming the first and second capacitors C ₁ and C ₂ , the overall capacitance of the floating diffusion region 116 may be increased.

FIG. 6 is a cross-sectional view of a CMOS image sensor that does not include a second capacitor C ₂ , such as 'A' in FIG. 4. Referring to FIG. 6, in the substrate 110 on which the device isolation layer 111 is formed, floating diffusion regions 116 and FD are formed to accumulate a photodiode (not shown) and charges generated in the photodiode. In addition, the gate electrode 114 of the drive transistor is formed on the substrate 110 to be electrically connected to the floating diffusion region 116 to amplify the charge accumulated in the floating diffusion region 116, and the gate electrode 110 is formed on the substrate 110. A plurality of contact plugs 119a, 119b, and 119c (hereinafter, referred to as first to third contact plugs) connected to the gate electrode 114 and the floating diffusion region 116 so as to cover the electrode 114, respectively. One interlayer insulating film 118 is formed.

In addition, on the first interlayer insulating film 118, the lower electrode 120a of the capacitor connected to the first and second contact plugs 119a and 119b and the metal layer 120 connected to the third contact plug 119c are formed. Each is formed.

In addition, an upper electrode 122 of the capacitor is formed on the second interlayer insulating layer 121 formed to cover the lower electrode 120a and the metal layer 120 of the capacitor. As a result, the first capacitor C ₁ including the lower electrode 120a / the second interlayer insulating film 121 / the upper electrode 122 is formed.

As a result, the first capacitor C ₁ connected in parallel with the floating diffusion region 116 is completed. By forming the first capacitor C ₁ , the overall capacitance of the floating diffusion region 116 may be increased.

7 is a cross-sectional view for explaining a method of manufacturing a CMOS image sensor according to an embodiment of the present invention. Hereinafter, a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention will be described with reference to FIG. 7.

First, the substrate 110 defined by the first to third regions UP ₁ , UP ₂ , and UP _{3 in} which the first to third unit pixels UP are to be formed is provided. Here, the capacitances of the floating diffusion regions are different in the first to third regions UP ₁ , UP ₂ , and UP ₃ . For example, the capacitance increases in the order of the first, second, and third regions UP ₁ , UP ₂ , UP ₃ .

Subsequently, a plurality of gate electrodes 114 are formed on the substrate 110 in the first to third regions UP ₁ , UP ₂ , and UP ₃ , respectively. For example, in the case of the 4-Tr structure, gate electrodes of a transfer transistor including a drive transistor, a reset transistor, and a select transistor are formed for each of the first to third regions. For convenience of description, only the gate electrode 114 of the drive transistor for amplifying the charge accumulated in the floating diffusion region is shown.

Next, a photodiode (not shown) is formed in each of the substrates 110 of the first to third regions UP ₁ , UP ₂ , and UP ₃ by performing a mask process and an impurity ion implantation process. Then, the floating diffusion regions 116 are formed in the substrates 110 of the first to third regions UP ₁ , UP ₂ , and UP ₃ , respectively, to accumulate charges generated in the photodiodes.

Subsequently, a first interlayer insulating film 118 is formed on the substrate 110 to cover the gate electrode 114. In this case, the first interlayer insulating film 118 is formed of an oxide film-based material. For example, the first interlayer insulating film 118 may include a high density plasma (HDP) oxide film, a boron phosphorus silicate glass (BPSG) film, a phosphorus silicate glass (PSG) film, a plasma enhanced tetra orthysilicate (PETOS) film, and a plasma enhanced PECVD film. Single layer film or lamination thereof using any one of Chemical Vapor Deposition (USG) film, USG (Un-doped Silicate Glass) film, FSG (Fluorinated Silicate Glass) film, Carbon Doped Oxide (CDO) film and Organic Silicate Glass (OSG) film It is formed into a laminated film.

Next, a first contact hole exposing a part of the gate electrode 114 in the first interlayer insulating layer 118 of the first to third regions UP ₁ , UP ₂ , and UP ₃ by performing a mask process and an etching process. Second and third contact holes (not shown) exposing portions of the floating diffusion region 116 are formed, respectively.

Subsequently, a plug material is deposited on the first interlayer insulating layer 118 to fill the first to third contact holes, and then planarize the first to third regions UP ₁ , UP ₂ , and UP ₃ . First contact plugs 119a connected to the gate electrode 114 and second and third contact plugs 119b and 119c connected to the floating diffusion region 116 are respectively formed in the first interlayer insulating film 118 of FIG. .

Subsequently, a metal layer 120 (hereinafter, referred to as a first metal layer) is deposited on the first interlayer insulating layer 118 including the first to third contact plugs 119a, 119b, and 119c.

Then, between the third area (UP ₃₎ the second and third contact plugs (119b, 119c) formed in the third region (UP ₃₎ such that the first metal layer 120 are separated from each other in the embodiment a masking process and etching process, The first metal layer 120 in the region corresponding to the etching is etched. Accordingly, the lower electrode 120a of the capacitor electrically connecting the first and second contact plugs 119a and 119b to each other on the first interlayer insulating film 118 of the third region UP ₃ is referred to as a first lower electrode. The first metal layer 120 is spaced apart from the first lower electrode 120a by a predetermined distance on the first interlayer insulating layer 118 exposed to one side of the first lower electrode 120a.

Preferably, the second and third contact plugs 119b formed in the second region UP ₂ are separated from each other not only in the third region UP ₃ but also in the second region UP ₂ . The first metal layer 120 in the region corresponding to between 119c is etched.

Subsequently, a second interlayer insulating layer 121 is formed on the entire surface of the first interlayer insulating layer 118 so as to cover the first metal layer 120 and the first lower electrode 120a.

Subsequently, after depositing the metal layer 122 (hereinafter, referred to as a second metal layer) on the second interlayer insulating layer 121, a mask process and an etching process are performed to perform the second metal layer 122 of the first region UP ₁ . Is etched, and the second metal layer 122 of the second and third regions UP ₂ and UP ₃ is left. As a result, an upper electrode 122 (hereinafter referred to as a first upper electrode) of the capacitor is formed on the second interlayer insulating film 121 in the second and third regions.

Therefore, the first lower electrode 120a / the second interlayer insulating layer 121 / the first upper electrode in the second and third regions UP ₂ and UP ₃ having a larger capacitance than the first region UP ₁ . A capacitor C ₁ (hereinafter, referred to as a first capacitor) having a structure in which the 122 is stacked may be formed. Through this, in the second and third regions UP ₃ , the capacitance C _FD + C ₁ obtained by adding the capacitance of the first capacitor C ₁ to the capacitance of the first region UP ₁ as a whole can be obtained. have.

Subsequently, a third interlayer insulating layer 123 is formed on the second interlayer insulating layer 121 in the first to third regions UP ₁ , UP ₂ , and UP ₃ to cover the first upper electrode 122. Then, the third area (UP ₃₎ a third fourth and fifth contact plugs in the interlayer insulating film 123 of the first top electrode 122 and the metal layer 120 and the third region (UP ₃₎ to be connected to each 124a and 124b are formed.

Subsequently, a metal layer (not shown; hereinafter referred to as a third metal layer) is deposited on the entire surface of the third interlayer insulating film 123 including the fourth and fifth contact plugs 124a and 124b, and then a part of the third metal layer is deposited. Etching is selectively performed to remove the third metal layers of the first and second regions UP ₁ and UP ₂ . As a result, a lower electrode 125 (hereinafter, referred to as a second lower electrode) of the capacitor remaining only in the third region UP ₃ is formed.

Subsequently, a fourth interlayer insulating film 126 and a metal layer (not shown below, referred to as a fourth metal layer) are sequentially deposited along the step of the entire structure including the second lower electrode 125. Thereafter, a mask process and an etching process are performed to etch the fourth metal layer and the fourth interlayer insulating layer 126 in the first and second regions UP ₁ and UP ₂ . As a result, an upper electrode 127 (hereinafter referred to as a second upper electrode) of the capacitor is formed on the fourth interlayer insulating film 126 of the third region UP ₃ .

Accordingly, the second lower electrode 125, the fourth interlayer insulating layer 126, and the second upper electrode 127 may be stacked only in the third region UP ₃ having a larger capacitance than the second region UP ₂ . A capacitor C ₂ (hereinafter referred to as a second capacitor) having a structure is formed. As a result, in the third region UP ₃ , the capacitance C _FD + C ₁ , in which the capacitances of the first and second capacitors C ₁ and C ₂ are added to the capacitance of the first region UP ₁ as a whole. + C ₂ ) can be obtained.

As described above, in the embodiment of the present invention, in order to control each capacitance for each unit pixel region having a different capacitance of the floating diffusion region, the number of capacitors connected in parallel to the floating diffusion region is selectively adjusted. For example, the number of capacitors formed in the unit pixel region in which it is necessary to increase the capacitance in the floating diffusion region without increasing the capacitance in the unit pixel region in which the capacitance of the floating diffusion region does not need to be increased is increased by the desired capacitance. To increase.

 Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, by further connecting at least one capacitor to the floating diffusion region in parallel, the capacitance of the floating diffusion region can be increased. Through this, the electrons in the photodiode are not all transferred to the floating diffusion region, and some of the charge sharing phenomena remaining in the channel region of the photodiode and / or the transfer transistor can be prevented, thereby solving the noise of the image sensor. Therefore, it is possible to form an image sensor having improved image characteristics.

Claims (16)

Photo diodes; A floating diffusion region configured to receive and store photocharges generated from the photodiode; At least one capacitor connected in parallel with the floating diffusion to increase the capacitance of the floating diffusion; And A first transistor for amplifying and outputting the charge accumulated in the floating diffusion region and the capacitor Image sensor comprising a. The method of claim 1, And at least two capacitors are connected in parallel with each other. The method according to claim 1 or 2, A second transistor connected between a power supply voltage terminal and the floating diffusion region to reset the floating diffusion region; And A third transistor which performs a switching role to output a signal amplified through the first transistor Image sensor further comprising. The method of claim 3, wherein And a fourth transistor connected between the photodiode and the floating diffusion region to transfer the photocharge of the photodiode to the floating diffusion region. A photodiode formed in the substrate; A floating diffusion region formed in the substrate to accumulate charges generated in the photodiode; A gate electrode connected to the floating diffusion region and formed on the substrate to amplify the charge accumulated in the floating diffusion region; A first interlayer insulating film formed through the plurality of contact plugs respectively connected to the gate electrode and the floating diffusion region to cover the gate electrode; A lower electrode of a capacitor formed on the first interlayer insulating film so as to be connected to the contact plug; A second interlayer insulating film formed on the first interlayer insulating film to cover the lower electrode; And An upper electrode of a capacitor formed on the second interlayer insulating film Image sensor comprising a. The method of claim 5, And a metal layer formed on the first interlayer insulating layer and connected to the contact plug on the same layer as the lower electrode so as to be separated from the lower electrode. A substrate defined by first to third regions in which the first to third pixels are to be formed; Photodiodes respectively formed in the substrates of the first to third regions; Floating diffusion regions respectively formed in the substrate to accumulate charges generated in the photodiode; A gate electrode connected to the floating diffusion region and formed on the substrate to amplify the charge accumulated in the floating diffusion region; A first interlayer insulating film formed to cover the entire structure including the gate electrode; A first contact plug formed in the first interlayer insulating film to be connected to the gate electrode and second and third contact plugs formed in the first interlayer insulating film to be connected to the floating diffusion region; And formed on the first interlayer insulating layer so as to be connected to the first to third contact plugs of the first to third regions, respectively, in the third region, being separated from each other and connected to the second and third contact plugs, respectively. A first metal layer; A second interlayer insulating film formed to cover the first metal layer; A second metal layer formed on the second interlayer insulating film in the second and third regions; A third interlayer insulating film formed on the entire surface of the second interlayer insulating film so as to cover the second metal layer; Fourth and fifth contact plugs formed in the third interlayer insulating film of the third region to be connected to the second metal layer of the third region and the first metal layer connected to the third contact plug, respectively; A third metal layer formed on the third interlayer insulating film in the third region so as to be connected to the fourth and fifth contact plugs; And A fourth interlayer insulating film and a fourth metal layer sequentially stacked on the third metal layer Image sensor comprising a. The method of claim 7, wherein And the first metal layer of the second region is separated from each other as in the third region. The method according to claim 7 or 8, The first to third regions have different capacitances. The method of claim 9, And a stack structure of the first metal layer, the second interlayer insulating film, and the second metal layer connected to the first and second contact plugs formed in the second area. The method of claim 10, The stacked structure of the first metal layer / the second interlayer insulating film / the second metal layer connected to the first and second contact plugs formed in the third region becomes a first capacitor, and the third metal layer / fourth interlayer insulating film / And the stack structure of the fourth metal layer is a second capacitor. Forming a plurality of gate electrodes on a substrate defined by first to third regions in which the first to third pixels are to be formed; Forming a photodiode and a floating diffusion region in the substrate of the first to third regions, respectively; Forming a first interlayer insulating film on the substrate to cover the gate electrode; Forming a first contact plug connected to a gate electrode for amplifying charge accumulated in the floating diffusion region among the gate electrodes, and a second and third contact plug connected to the floating diffusion region, respectively, in the first interlayer insulating layer; step; Depositing a first metal layer on the first interlayer insulating film including the first to third contact plugs; Etching the first metal layer in an area corresponding to the area between the second and third contact plugs formed in the third area so that the first metal layer is separated from each other in the third area; Forming a second interlayer insulating film on the first interlayer insulating film so as to cover the first metal layer; Forming a second metal layer on the second interlayer insulating film in the second and third regions, respectively; Forming a third interlayer insulating film on the second interlayer insulating film in the first to third regions so as to cover the second metal layer; Forming fourth and fifth contact plugs in the third interlayer insulating film of the third region so as to be connected to the second metal layer of the third region and the first metal layer connected to the third contact plug, respectively; Forming a third metal layer on the third interlayer insulating film in the third region so as to be connected to the fourth and fifth contact plugs; And Sequentially forming a fourth interlayer insulating film and a fourth metal layer on the third metal layer in the third region. Image sensor manufacturing method comprising a. The method of claim 12, The etching of the first metal layer corresponds to a region between the second and third contact plugs formed in the second and third regions so that the first metal layer is separated from each other in the second region as well as the third region. An image sensor manufacturing method for etching the first metal layer of the region. The method of claim 12 or 13, wherein forming a third metal layer on the third interlayer insulating film of the third region, Depositing the third metal layer on the third interlayer insulating film in the first to third regions; And Selectively etching a portion of the third metal layer to remove the third metal layer in the first and second regions. Image sensor manufacturing method comprising a. The method according to claim 12 or 13, And forming one capacitor in the second region by sequentially stacking the first metal layer, the second interlayer insulating layer, and the second metal layer connected to the first and second contact plugs. The method of claim 15, In the third region, the first metal layer / the second interlayer insulating film / the second metal layer connected to the first and second contact plugs are sequentially stacked to form a first capacitor, and the third metal layer / fourth interlayer insulating film / And stacking the fourth metal layers in sequence to form a second capacitor.

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