KR20070049292A - Array substrate and liquid crystal display panel and liquid crystal display device having the same - Google Patents

Abstract

Disclosed are a liquid crystal display panel which prevents flicker and improves display quality, and a liquid crystal display device having the same. The liquid crystal display panel includes a second substrate coupled to the first substrate to receive the liquid crystal layer, and the second substrate is defined by a plurality of gate lines extending in the first direction and data lines extending in the second direction. A base substrate including a display area in which pixels are formed, a peripheral area surrounding the display area, a first common voltage wire extending in a second direction and formed in the first peripheral area to provide a first common voltage to the display area; A second common voltage wire extending in a second direction and formed in the second peripheral area to provide a first common voltage to the display area, a third common voltage wire and a first common voltage to which the second common voltage provided from the display area is applied; And a common voltage compensator configured to compensate for a difference between the first common voltage applied from the wiring and the second common voltage applied from the third common voltage wiring. By equally forming the potential level of the common voltage applied across the display area, the flicker phenomenon can be prevented and the display quality of the liquid crystal display device can be improved.

Description

ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME

1 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a plan view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

3 is an enlarged partial view of a portion of the array substrate illustrated in FIG. 2.

4 is a diagram for describing storage voltage lines and common voltage lines formed on the array substrate illustrated in FIG. 2.

5A is a waveform diagram illustrating a common voltage provided by a line inversion scheme.

5B is a waveform diagram illustrating distortion of a common voltage provided by a line inversion method.

FIG. 6 is a diagram illustrating an embodiment of a common voltage compensator shown in FIG. 2.

FIG. 7 is a diagram conceptually illustrating an embodiment of the gate driving chip illustrated in FIG. 2.

Explanation of symbols on the main parts of the drawings

100, 200: liquid crystal display 110: display unit

120: control unit 130: power supply unit

140: data driver 150: gate driver

210: liquid crystal display panel 220: source printed circuit board

230: data TCP 240: gate drive chip

250: common voltage compensator

CVL1: first common voltage wiring CVL2: second common voltage wiring

CVL3: third common voltage wiring SP: short point

SE: storage voltage wiring BE: bridge wiring

The present invention relates to a liquid crystal display panel and a liquid crystal display device having the same, and more particularly, to a liquid crystal display panel and a liquid crystal display device having the same to improve the display quality by preventing the flicker phenomenon.

Recently, display devices are also required to be lighter and thinner in accordance with the trend of lighter and thinner monitors, laptops, TVs, and mobile communication terminals, and various flat panel displays instead of conventional cathode ray tubes are required to meet such demands. ), Development and popularization are rapidly taking place.

Liquid crystal display (LCD) is one of such flat panel display devices, which injects a liquid crystal material having dielectric anisotropy between two substrates, applies an electric field, and adjusts the strength of the electric field. It is a device that displays a desired image by controlling the amount of light transmitted through.

Recently, the liquid crystal display has been rapidly expanded in its installation range and is being used as a display device of various devices such as a notebook, a monitor of a computer, a TV and a mobile communication terminal, and accordingly, a demand for improving display quality is increasing.

The liquid crystal display device includes a liquid crystal display panel. The liquid crystal display panel has an array substrate, an opposing substrate, and a liquid crystal layer interposed between the array substrate and the opposing substrate. The array substrate has a plurality of data lines and gate lines that cross each other, and consists of a plurality of pixels defined by the data lines and the gate lines.

Each of the plurality of pixels includes a switching element, a liquid crystal capacitor, and a storage capacitor. The first electrode of the liquid crystal capacitor is a pixel electrode connected to the drain electrode of the switching element, and the second electrode is a common electrode formed on the opposing substrate. The first electrode of the storage capacitor is a pixel electrode, and the second electrode is a common electrode applied to the array substrate.

The gate signal applied to the gate line is applied to the gate electrode of the switching element, and when the switching element is turned on, the data signal applied to the data line is applied to the pixel electrode which is the first electrode of the liquid crystal capacitor through the source electrode of the switching element. .

In addition, after the data signal is applied to the pixel electrode, which is the first electrode of the storage capacitor, the inverted common voltage is applied to the second electrode of the storage capacitor in line units to maintain the potential level of the data signal. Accordingly, charge is charged in the liquid crystal capacitor and the storage capacitor by the data signal applied to the liquid crystal capacitor and the data signal stored in the storage capacitor, and the arrangement angle of the liquid crystal is changed according to the charge rate of the charge. The image data is displayed by the light transmitted or reflected through the liquid crystal layer whose alignment angle is changed.

The storage voltage line constituting the storage capacitor is connected to the common voltage line in a first direction and overlaps the pixel electrode. In addition, the second electrode of the storage capacitor, that is, the common electrode, receives a common voltage from the outside by a common voltage line formed in the second direction at both ends of the liquid crystal display panel.

At this time, the common voltage wiring formed in the region opposite to the region where the gate driving chip providing the gate signal among the common voltage wiring is formed is formed by the same mask when forming the storage voltage wiring and interconnected on the same array. do.

However, the common voltage lines formed in the region adjacent to the gate driving chip are formed on different arrays by different masks from the storage voltage lines. Therefore, the common voltage wiring formed in the region adjacent to the gate driving chip is electrically connected through the storage voltage wiring and the bridge wiring, and the wiring width thereof is relatively narrower than that of the common voltage wiring formed in the region facing the gate driving chip. You lose.

In addition, signal lines for providing a gate signal are disposed in the peripheral region in which the gate driving chip is formed, so that the space between the gate driving chips is narrow. As a result, the impedances of the common voltage wiring and the storage voltage wiring adjacent to the gate driving chip are relatively increased, so that the distortion of the common voltage provided to each pixel increases, resulting in a difference in the potential level of the common voltage applied across the storage voltage wiring. As a result, a flicker phenomenon occurs.

An object of the present invention for solving the above problems is to provide a liquid crystal display panel that can provide a common voltage applied across the storage voltage wiring at the same potential level.

Another object of the present invention is to provide a liquid crystal display device having the liquid crystal display panel.

In order to achieve the above object, a liquid crystal display panel according to an exemplary embodiment of the present invention includes a first substrate on which a common electrode is formed and a second substrate in combination with the first substrate to accommodate a liquid crystal layer.

In this case, the second substrate includes a base substrate, a first common voltage line, a second common voltage line, a third common voltage line, and a common voltage compensator. The base substrate includes a display area in which a plurality of pixels defined by gate wires extending in a first direction and data wires extending in a second direction, and a peripheral area surrounding the display area. The first common voltage line extends in the second direction and is formed in a first peripheral area of the peripheral area to provide a first common voltage to the display area. The second common voltage line extends in the second direction and is formed in a second peripheral region facing the first peripheral region to provide the first common voltage to the display region. The third common voltage wiring is formed in a predetermined region of the peripheral region, and a second common voltage provided from the display region is applied. The common voltage compensator compensates for a difference between a first common voltage applied from the first common voltage line and a second common voltage applied from the third common voltage line.

In order to achieve the above object, the liquid crystal display according to the exemplary embodiment includes a display unit, a gate driver, a data driver, and a controller. The display unit includes a display area in which a plurality of pixels are formed and a peripheral area surrounding the display area. The gate driver provides a gate signal to the display area. The data driver provides a data signal to the display area. The controller provides a driving signal to the gate and the data driver.

In this case, the display unit may be formed in a first peripheral area of the peripheral area to extend the first common voltage line in the second direction to provide a first common voltage to the display area, and to face the first peripheral area. A second common voltage line formed in a second peripheral area to provide the first common voltage to the display area, and a third common voltage formed in a predetermined area of the peripheral area and to which a second common voltage provided from the display area is applied And a common voltage compensator configured to compensate for a difference between the first common voltage applied from the voltage wiring and the first common voltage wiring and the second common voltage applied from the third common voltage wiring.

According to the liquid crystal display panel and the liquid crystal display device, the potential difference of the common voltage applied to both ends of the storage voltage wiring is generated due to the impedance that increases as the common voltage wiring formed on one side of the array substrate is formed adjacent to the other signal wirings. This prevents the flicker phenomenon and improves the display quality of the liquid crystal display.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display device 100 according to an exemplary embodiment of the present invention may include a display unit 110, a timing controller 120, a power supply unit 130, a data driver 140, and a gate driver 150. Include.

The display unit 110 includes an array substrate (not shown) in which a thin film transistor (TFT) array is formed, an opposite substrate (not shown) provided to face the array substrate, and a liquid crystal interposed between the array substrate and the opposite substrate. Layer (not shown).

The display unit 110 will be described in detail with reference to FIGS. 2 to 7.

The timing controller 120 controls the overall operation of the liquid crystal display device 100. The timing controller 120 is provided with a raw data signal DATA_O and a first control signal CNTL1 of red (R), green (G), and blue (B) from a host system such as an external graphic controller (not shown). Accordingly, the first data signal DATA1, the second control signal CNTL2, the third control signal CNTL3, and the fourth control signal CNTL4 for displaying an image are output to the display unit 110.

Specifically, the first control signal CNTL1 includes a main clock signal MCLK, a horizontal sync signal HSYNC, a vertical sync signal VSYNC, and the like. The second control signal CNTL2 includes a horizontal start signal STH, an inversion signal REV, a data load signal TP, and the like that control the data driver 140. The third control signal CNTL3 includes a start signal STV, a clock signal CK, an output enable signal OE, and the like that control the gate driver 150. The fourth control signal CNTL4 includes a clock signal CLK and an inverted signal REV for controlling the power supply 130.

In addition, the timing controller 120 provides the data driver 140 with the first data signals DATA1 of R ', G', and B 'whose output timing of the raw data signal DATA_O is controlled.

The power supply unit 130 is provided to the display unit 110 in response to the fourth control signal CNTL4, and the first common voltage Vcom1 having the inverted potential in units of lines and the analog driving voltage provided to the data driver 140. A gate on / off voltage Von.Voff provided to the AVDD and the gate driver 150 is output.

The data driver 140 includes a gray voltage generator (not shown) and a data driver circuit (not shown).

The gray scale voltage generator outputs a plurality of reference gray scale voltages corresponding to the number of gray scale levels based on the distribution resistor having the resistance ratio to which the gamma curve is applied, using the analog driving voltage AVDD provided from the power supply unit 140 as a reference voltage. do.

The data driver circuit may be formed of a single chip. The data driving circuit generates a gray voltage based on the reference gray voltage output from the gray voltage generator. In addition, the first data signal DATA1 of the digital form is converted into the data voltages D1, ..., Dm based on the gray scale voltage, and the output timing of the data voltages D1, ..., Dm is controlled. Output to the data lines DL.

To this end, the data driving circuit includes a gamma string for distributing the reference gray voltage corresponding to the gamma curve, and a digital-analog converter for converting the first data signal DATA1 to the data voltages D1,..., Dm. .

The gate driver 150 includes a gate driver circuit. The gate driving circuit may be formed in a predetermined region of the array substrate constituting the display unit 110 or may be formed of a single chip.

FIG. 2 is a plan view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 3 is an enlarged partial view of a portion of the array substrate illustrated in FIG. 2, and FIG. 4 is shown in FIG. 2. FIG. 4 is a diagram for describing storage voltage lines and common voltage lines formed on the illustrated array substrate.

Referring to FIG. 2, the liquid crystal display 200 according to an exemplary embodiment of the present invention includes a liquid crystal display panel 210, a source printed circuit board 220, a data TCP 230, and a gate driving chip 240. do.

The liquid crystal display panel 210 includes an array substrate 211, an opposing substrate 212, and a liquid crystal layer (not shown) interposed between the two substrates 211 and 212. Here, the liquid crystal display panel 210 refers to the display unit 110 shown in FIG. 1.

The array substrate 211 is a transparent glass substrate on which TFTs as switching elements are formed. Source and gate terminals of the TFTs are respectively connected to data lines DL1 to DLm and gate lines GL1 to GLn formed on the array substrate 211, and the drain terminal is connected to a pixel electrode made of a transparent conductive material. do.

The array substrate 211 includes a plurality of pixels defined by data and gate lines DL and GL, and each of the plurality of pixels has the TFT, the liquid crystal capacitor, and the storage capacitor. The first electrode of the liquid crystal capacitor is a pixel electrode connected to the drain electrode of the TFT, and the second electrode is a common electrode formed on the opposing substrate. The first electrode of the storage capacitor is the pixel electrode and the second electrode is a common electrode applied to the array substrate 211. This will be described in more detail as follows.

Referring to FIG. 3, the array substrate 211 is a substrate on which a plurality of pixels, which are a basic unit for displaying an image, is formed in a matrix form. The j th pixel Pji of the plurality of pixels includes a j th gate line GLj, an i th data line DLi, a j th thin film transistor (TFT), and a j th pixel electrode. (PEji).

The j-th gate line GLj extends in the first direction D1, and the i-th data line DLi extends in the second direction D2 orthogonal to the first direction D1, such that the j-th gate line GLj ) And insulated.

The j th pixel line PAji is formed by the i th data line DLi and the j th gate line GLj which are adjacent to the i th data line DLi-1 and the j th gate line GLj-1. Define. A j th TFT (Tji) and a j j pixel electrode PEji are formed in the j j pixel area PAji.

The gate electrode G of the j th TFT Tji is branched from the j th gate line GLj, the source electrode S is branched from the i th data line DLi, and the drain electrode D is the j th pixel. It is electrically connected to the electrode PEji. Accordingly, the TFT Tji outputs the data signal applied to the i th data line DLi to the j th pixel electrode PEji in response to the gate signal applied to the j th gate line GLj.

The j th pixel Pji is further provided with a j th storage voltage line SEji to which the first common voltage Vcom1 is applied, and defines a storage capacitor facing the j j pixel electrode PEji.

The j-th storage voltage line SEji extends in the first direction D1 in parallel with the j-th gate line GLj and adjacent to the j-th storage voltage line SEji-1 adjacent to the first direction D1. It is electrically connected to the ji + 1 th storage voltage line SEji + 1. In addition, the ji storage voltage line SEji may be branched in the second direction D2 to be parallel to the i-th data line DLi.

The ji storage voltage line SEji may be formed of aluminum (Al), aluminum alloy (Al alloy), chromium (Cr), molybdenum (Mo), or the like on the same layout as the j-th gate line GLj. In addition to the above-described metals and metal alloys, it may be formed of various metals or conductors.

On the other hand, the ji storage voltage line SEji is electrically separated from the j-1i storage voltage line SEj-1i and the j + 1i storage voltage line SEj + 1i adjacent to each other in the second direction D2. .

2 and 4, the array substrate 211 is connected to the storage voltage line SE, and the first common voltage, which is provided from the power supply unit 130 shown in FIG. 1, to the storage voltage line SE. When the first and second common voltage lines CVL1 and CVL2 and the first common voltage Vcom1 are applied to the storage voltage line SE, the second common voltage Vcom2 is distorted. The first common voltage Vcom1 is received from the third common voltage line CVL3 and the first common voltage line CVL1, and the second common voltage Vcom2 is received from the third common voltage line CVL3. A common voltage compensator 250 is formed to compensate for the distortion component of the voltage Vcom1.

The first common voltage line CVL1 is formed at the same time when the gate lines GL1 to GLn are formed by the gate mask on the same layout as the storage voltage line SE, and is defined by the pixels. The first peripheral area SA1 is formed in the peripheral area SA surrounding the DA. The gate driving chip 240 is mounted in the first peripheral area SA1, and the signal lines for providing the gate driving signal lamp to the gate driving chip 240, the gate lines connected to the gate driving chip 240, and the like. The first common voltage line CVL1 and the storage voltage line SE are electrically connected to each other through the bridge line BE formed to be electrically insulated from the signal lines and the gate lines.

The second common voltage line CVL2 is formed when the gate lines GL1 to GLn are formed by the gate mask on the same layout as the storage voltage line SE, and faces the first peripheral area SA1. It is formed in the second peripheral area SA2. Since the signal lines and the gate lines are not formed in the first peripheral area SA1, the second common voltage line CVL2 and the storage voltage line SE are connected to each other when formed by the gate mask.

The first and second common voltage wires CVL1 and CVL2 may be configured so that the storage voltage wires SE may smoothly supply current by an RC delay or the like depending on the position on the panel. Although electrically connected to both ends of the storage voltage line SE in the peripheral areas SA1 and SA2, only one of the first and second common voltage lines CVL1 and CVL2 may be formed.

In addition, in the exemplary embodiment of the present invention, the gate driving chip 240 is formed in the first peripheral area SA1, but the gate driving chip 240 may be formed in the second peripheral area SA2, In order to divide and drive the lines GL1 to GLn, the first and second peripheral areas SA1 and SA2 may be formed. In this case, the second common voltage wire CVL2 may be electrically connected to the second common voltage wire CVL1 through the bridge wire BE in the same manner as the first common voltage wire CVL1.

In addition, the gate driving chip 240 may be formed in a predetermined circuit pattern on the first peripheral area SA1 or the second peripheral area SA2 of the array substrate 211.

The array substrate 211 according to an embodiment of the present invention further includes a third common voltage wiring CVL3 and a common voltage compensator 250.

Another signal formed around the first common voltage line CVL1 when the first common voltage Vcom1 is applied to the third common voltage line CVL3 through the first common voltage line CVL1 to the storage voltage line SE. As the interconnections are formed, impedances of the first common voltage interconnection CVL1 and the storage voltage interconnection SE are relatively increased to apply a second common voltage Vcom2 formed by distorting the first common voltage Vcom1. .

For example, when the third common voltage wiring CVL3 is formed in the first direction D1 in the third peripheral area SA3, and the common voltage compensator 350 is formed in the first peripheral area SA1, the third common voltage wiring CVL3 is formed in the first peripheral area SA1. 1 extends to the peripheral area SA1 and is connected to the common voltage compensator 250.

The third common voltage line CVL3 may be connected to a predetermined region of the storage voltage line SE, and is provided on the array substrate 211 to provide the first common voltage Vcom1 to the common electrode formed on the opposing substrate 212. It may be connected to a short point (SP).

That is, the short point SP is formed to transfer the first common voltage Vcom1 provided to the array substrate 211, but as described above, a plurality of wires are formed around the first common voltage line CVL1. As a result, impedances of the first common voltage line CVL1 and the storage voltage line SE increase, and accordingly, the second common voltage Vcom2 in which the first common voltage Vcom1 is distorted is disposed on the opposing substrate 312. Since it is provided as the second common voltage (Vcom2) from the short point (SP). The plurality of short points SP may be formed, and the third common voltage line CVL3 may be connected to the plurality of short points SP.

The common voltage compensator 250 is connected to the first common voltage line CVL1 and the third common voltage line CVL2, and the second common voltage Vcom2 and the first common voltage line CVL2 are provided. The first common voltage Vcom1 is amplified and output in proportion to the difference of the first common voltage Vcom1 provided by the common voltage line CVL1.

The structure and operation of the common voltage compensator 250 are as follows.

5A is a waveform diagram illustrating a common voltage provided by the line inversion method, FIG. 5B is a waveform diagram illustrating the distortion of the common voltage provided by the line inversion method, and FIG. 6 is a common voltage shown in FIG. 1 is a diagram illustrating an embodiment of a compensator. FIG. 7 is a diagram conceptually illustrating an embodiment of the gate driving chip illustrated in FIG. 2.

5A and 5B, when the current gate line GLk is activated, the data signal Vd is applied to the data lines DL1 to DLm connected to the gate line GLk, and the next gate line GLk. The data signal Vd remains at a potential lowered by a predetermined kick-back voltage level caused by the distorted component of the first common voltage Vcom1 until +1) is activated. do. In this case, the first common voltage Vcom1 and the data signal are provided to have inverted phases in line units, and the first common voltage Vcom1 and the data signal are provided to have inverted phases.

That is, as described above, the same first common voltage Vcom1 is provided to the array substrate 211 through the first common voltage Vcom1 through the first common voltage wire CVL1 and the second common voltage wire CVL2. As shown in FIG. 5B, the first common voltage Vcom1 is distorted as the impedance of the first common voltage line CVL1 and the storage voltage line SE is increased to form a second common voltage Vcom2. The data signal Vd fluctuates as shown in FIG. 5A due to the voltage difference between the common voltages applied across the storage voltage line SE. As a result, flicker occurs in the liquid crystal display panel.

Referring to FIG. 6, the common voltage compensator 250 is, for example, a first common voltage wire CVL1 connected to the positive input terminal + to receive the first common voltage Vcom1, and to receive a negative input terminal ( The third common voltage wiring CVL3 is connected to-) to receive the second common voltage Vcom2 and to be formed as an operational amplifier having a precious loop in which an output is provided to the negative input terminal (-). Can be.

The common voltage compensator 250 is connected to the first common voltage line CVL1 and the third common voltage line CVL3 and is provided from the third common voltage line CVL3 and the first common voltage Vcom2. By amplifying and outputting the first common voltage Vcom1 that is proportional to the difference of the first common voltage Vcom1 provided from the voltage wiring CVL1, the first common voltage Vcom1 forms the first common voltage wiring CVL1. This prevents distortion when provided to the storage voltage wiring SE.

That is, as shown in FIG. 5B, the difference between the distorted second common voltage Vcom2 and the first common voltage Vcom1 may be compared, and the first common voltage Vcom1 may be amplified as much as the first common voltage Vcom1. It is provided to the wiring CVL1. Therefore, the skew of the second common voltage Vcom2 is compensated as the first common voltage Vcom1 provided from the outside is provided back to the first common voltage wiring CVL1 at a potential level amplified in proportion to the distortion component. Thus, the first common voltage Vcom1 provided from the outside is provided to the storage voltage line SE as it is. Therefore, the potential of the common voltage provided across the storage voltage line SE is provided with the same level of potential, and the flicker phenomenon due to the difference in the applied voltage applied across the storage voltage line SE is prevented.

Referring to FIG. 7, the common voltage compensator 250 may be formed in the gate driving chip 240 illustrated in FIG. 2. Gate pads P1 to Pn electrically connected to the gate lines GL1 to GLn are formed on the gate driving chip 240, and the gate driving chip 240 is formed on an array substrate by a chip on glass (COG) process. When mounted on the 211, the dummy pad is inclined in the direction in which the gate pads P1 to Pn are formed due to the weight of the gate pads P1 to Pn to prevent a problem in which a defect occurs during bonding. Fields DP1 to DPt are formed.

Accordingly, when the common voltage compensator 250 includes the op amp, the first common voltage line CVL1 and the third common voltage line CVL1 are formed on the dummy pads DP1 to DPt. ), The input of the op-amp is connected to the dummy pads DP1 to DPt, and the output of the op-amp is connected to the dummy pads DP1 to DPt to form a first common voltage line CVL1. It can be formed to be connected to). By forming the common voltage compensator 250 inside the gate driving chip 240, an increase in the size of the array substrate 211 can be prevented, and process margins of the array substrate 211 can be ensured to the same level as in the prior art. Can be.

Referring back to FIG. 2, the opposing substrate 212 is disposed facing the array substrate 211. The opposite substrate 212 has red (R), which is a color pixel. A color filter layer (not shown) in which green (G) and blue (B) pixels are formed by a thin film process may be formed. A common electrode (not shown) made of a transparent conductive material is coated on the front surface of the opposing substrate 212.

The source printed circuit board 220 generates a data driving signal and a gate driving signal and outputs the data driving signal to the data TCP 230. In this case, a gate driving wiring 213 for providing the gate driving signal to the gate driving chip 240 is formed on the array substrate 211. The source printed circuit board 220 is connected to the array substrate 211 through the data TCP 230.

Here, the grayscale voltage generator included in the timing controller 120, the power supply 130, and the data driver 140 illustrated in FIG. 1 may be formed on the source printed circuit board 220. The data driving signal includes a first data signal DATA1, a second control signal CNTL2, an analog driving voltage AVDD, and the like, and the gate driving signal includes gate on / off voltages Von and Voff, and The third control signal CNTL3 may be included.

The data TCP 230 is configured in plural to drive the data lines DL1 to DLm into a plurality of blocks, and is attached to the third peripheral area SA3 of the peripheral area SA of the array substrate 211. . In addition, a data driving chip 231 is provided in the data TCP 230 to provide data voltages to the data lines DL1 to DLm in response to the data driving signal. Here, the data TCP 230 means the data driver 140 shown in FIG. 1.

The gate driving chip 240 may be mounted in the first peripheral area SA1 or the second peripheral area SA2 and may be formed in a predetermined circuit pattern on the first or second peripheral areas SA1 and SA2. have. The gate driving chip 240 sequentially switches the gate lines GL1 to the gate on / off voltages Von and Voff provided from the power supply 130 shown in FIG. 1 in response to the third control signal CNTL3. Provide to GLn). That is, the gate driver chip 240 refers to the gate driver 150 illustrated in FIG. 1.

In this manner, the first common voltage Vcom1 applied at both ends of the liquid crystal display panel 300 is prevented from being applied at different potential levels.

According to the present invention as described above, by providing a common voltage applied across the storage voltage wiring at the same potential level, it is possible to prevent the flicker phenomenon caused by the difference in the applied voltage, thereby improving the display quality of the liquid crystal display device You can.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (10)

A first substrate on which a common electrode is formed; And A second substrate coupled to the first substrate to receive a liquid crystal layer; The second substrate, A base substrate including a display area in which a plurality of pixels are defined by gate lines extending in a first direction and data lines extending in a second direction, and a peripheral area surrounding the display area; A first common voltage line extending in the second direction and formed in a first peripheral area of the peripheral area to provide a first common voltage to the display area; A second common voltage line extending in the second direction and formed in a second peripheral region facing the first peripheral region to provide the first common voltage to the display region; A third common voltage line formed in a predetermined area of the peripheral area and to which a second common voltage provided from the display area is applied; And And a common voltage compensator configured to compensate for a difference between a first common voltage applied from the first common voltage line and a second common voltage applied from the third common voltage line. The semiconductor device of claim 1, further comprising: a gate driving chip mounted in the first peripheral region and sequentially providing a gate signal to the gate lines; The common voltage compensator is formed in the gate driving chip. 2. The circuit of claim 1, wherein the common voltage compensator has a feedback loop in which a first common voltage is provided to a positive input terminal, the second common voltage is provided to a negative input terminal, and an output is provided to the negative input terminal. A liquid crystal display panel comprising an off-amp. The liquid crystal display panel of claim 1, wherein the first common voltage is inverted in units of lines. The liquid crystal display panel of claim 1, wherein the second substrate further comprises a short point for providing the first common voltage to the common electrode. The liquid crystal display panel of claim 5, wherein the third common voltage line is electrically connected to the short point. A display unit including a display area in which a plurality of pixels are formed and a peripheral area surrounding the display area; A gate driver configured to provide a gate signal to the display area; A data driver which provides a data signal to the display area; A power supply unit providing a first common voltage to the display area; And A timing controller configured to provide a driving signal to the gate and the data driver; The display unit, A first common voltage line formed in a first peripheral area of the peripheral area to provide the first common voltage to the display area; A second common voltage line extending in the second direction and formed in a second peripheral region facing the first peripheral region to provide the first common voltage to the display region; A third common voltage line formed in a predetermined area of the peripheral area and to which a second common voltage provided from the display area is applied; And And a common voltage compensator configured to compensate for a difference between a first common voltage applied from the first common voltage line and a second common voltage applied from the third common voltage line. The method of claim 7, wherein the gate driver is formed of a single chip, And the common voltage compensator is formed inside the gate driving chip. The liquid crystal display of claim 7, wherein the display unit further comprises a short point for providing the first common voltage to the common electrode. The liquid crystal display of claim 9, wherein the third common voltage line is electrically connected to the short point.

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