KR20070044920A - Method for fabricating the same of semiconductor device with recess gate - Google Patents

Method for fabricating the same of semiconductor device with recess gate Download PDF

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KR20070044920A
KR20070044920A KR1020050101241A KR20050101241A KR20070044920A KR 20070044920 A KR20070044920 A KR 20070044920A KR 1020050101241 A KR1020050101241 A KR 1020050101241A KR 20050101241 A KR20050101241 A KR 20050101241A KR 20070044920 A KR20070044920 A KR 20070044920A
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pad oxide
etching
oxide film
gas
recess
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남기원
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
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Abstract

본 발명은 패드산화막에 대한 실리콘의 선택비를 증가시키고, 패드산화막의 슬로프문제를 해결하기위한 반도체 소자의 제조방법을 제공하기 위한 것으로, 본 발명은 반도체 기판상에 패드산화막을 형성하는 단계, 상기 패드산화막상에 하드마스크패턴을 형성하는 단계, 상기 하드마스크패턴을 식각마스크로 하고 하이드로카본계 가스와 산소가스의 혼합가스를 이용하여 상기 패드산화막을 식각하는 단계, 상기 하드마스크패턴을 식각마스크로 하여 상기 패드산화막 식각 후 노출되는 반도체 기판을 식각하여 리세스게이트를 위한 리세스를 형성하는 단계를 포함하고, 상술한 본 발명은 웨이퍼내 반도체 기판에 대한 식각 손실 불균일을 방지하고, 패드산화막의 수직한 프로파일을 형성하여 안정적인 리세스게이트 프로파일과 안정적인 전기적 특성을 향상 시킬 수 있는 효과가 있다.The present invention is to provide a method for manufacturing a semiconductor device to increase the selectivity of silicon to the pad oxide film, and to solve the slope problem of the pad oxide film, the present invention comprises the steps of forming a pad oxide film on a semiconductor substrate, the Forming a hard mask pattern on the pad oxide film, etching the pad oxide film using a mixed gas of a hydrocarbon gas and an oxygen gas, and etching the hard mask pattern as an etch mask. Forming a recess for a recess gate by etching the exposed semiconductor substrate after etching the pad oxide layer, wherein the present invention prevents etching loss non-uniformity with respect to the semiconductor substrate in the wafer, and vertically Stable recess gate profile and stable electrical characteristics by forming one profile There is to improve effectiveness.

리세스, 패드산화막, 슬로프, 선택비, 과도식각 Recess, pad oxide, slope, selectivity, overetch

Description

리세스 게이트를 갖는 반도체 소자의 제조방법{METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE WITH RECESS GATE}A method of manufacturing a semiconductor device having a recess gate {METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE WITH RECESS GATE}

도 1은 종래기술에 따른 반도체 소자의 구조를 설명하기 위한 구조도,1 is a structural diagram for explaining the structure of a semiconductor device according to the prior art,

도 2a 내지 도 2d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 소자분리막21 semiconductor substrate 22 device isolation film

23 : 패드산화막 24 : 하드마스크23: pad oxide film 24: hard mask

25 : 감광막 26 : 리세스25 photosensitive film 26 recess

27 : 게이트절연막 28 : 게이트패턴27: gate insulating film 28: gate pattern

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 리세스 게이트를 갖 는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a recess gate.

반도체 소자가 초고집적화 됨에 따라 게이트를 평탄한 활성영역 위에 형성하는 기존의 플라나 게이트(Planar Gate)배선 형성 방법은 게이트 채널길이(Gate channel Length)가 점점 작아지고 이온주입도핑(Implant Dopping)농도가 증가함에 따라 전계(Electric Filed) 증가에 의해 접합 누설전류(Junction Leakage)가 생겨 소자의 리프레시특성을 확보하기가 어렵다.As the semiconductor devices become highly integrated, the conventional planar gate wiring forming method for forming a gate over a flat active region becomes smaller as the gate channel length and the ion implantation doping concentration increase. As a result, an increase in electric filed causes junction leakage, which makes it difficult to secure refresh characteristics of the device.

이를 개선하기 위해 게이트 배선 형성방법으로 활성영역 기판을 리세스패턴으로 식각 후 게이트를 형성하는 리세스게이트 공정이 실시되고 있다. 상기 리세스게이트 공정을 적용하면 채널길이 증가 및 이온주입 도핑 농도의 감소가 가능하여 소자의 리프레시 특성이 개선된다.In order to improve this, a recess gate process is performed in which an active region substrate is etched into a recess pattern and a gate is formed using a gate wiring method. Applying the recess gate process can increase the channel length and decrease the ion implantation doping concentration, thereby improving the refresh characteristics of the device.

도 1은 종래기술에 따른 반도체 소자를 설명하기 위한 구조도이다.1 is a structural diagram for explaining a semiconductor device according to the prior art.

도 1을 참조하면, 반도체 기판(11) 상에 패드산화막(12)이 형성된다. 패드산화막(12) 상에 리세스 예정지역이 오픈된 하드마스크(13)이 형성된다. 하드마스크(13)는 도시되지는 않았지만, 하드마스크(13) 상에 리세스 예정지역이 오픈된 감광막을 형성하고, 감광막의 마진부족으로 폴리실리콘 하드마스크를 사용하여, 상기 감광막을 식각마스크로 하드마스크를 식각한 후, 감광막을 제거하여 형성된 것이다. Referring to FIG. 1, a pad oxide film 12 is formed on a semiconductor substrate 11. On the pad oxide film 12, a hard mask 13 in which a recess scheduled region is opened is formed. Although not shown, the hard mask 13 may form a photoresist film having a recess scheduled region open on the hard mask 13, and use the polysilicon hard mask due to lack of margin of the photoresist film, thereby hardening the photoresist film as an etch mask. After etching the mask, it is formed by removing the photosensitive film.

하드마스크(13)를 식각마스크로 패드산화막(12)을 식각한다. 상기 식각은 CF4 또는 C2F6 중에서 어느 하나를 사용하여 진행하되, 패드산화막(12)의 과도식각 이 필수적인데, 패드산화막(12)과 반도체 기판(11)의 낮은 식각선택비로 패드산화막(12)에 대한 과도식각을 진행할 경우 패드산화막(12)의 식각모양은 수직하지만 빠른 실리콘 식각율로 반도체 기판(11) 표면의 식각 균일도 불안정(100) 문제를 야기한다.The pad oxide layer 12 is etched using the hard mask 13 as an etching mask. The etching may be performed using either CF 4 or C 2 F 6 , but over-etching of the pad oxide layer 12 is essential. The pad oxide layer 12 may be formed at a low etching selectivity of the pad oxide layer 12 and the semiconductor substrate 11. In the case of the excessive etching of 12), the etched shape of the pad oxide film 12 is vertical but has a high silicon etch rate, which causes a problem of instability of the etching uniformity 100 of the surface of the semiconductor substrate 11.

또한, 패드산화막(12)의 과도식각을 감소시킬 경우 패드산화막(12)의 언에치(unetch) 또는 타겟부족에 의한 패드산화막 슬로프(200)모양이 유발되어, 후속 반도체 기판(11) 리세스 식각시 패드산화막 슬로프(200)를 따라 불안정한 CD(Critical Dimension)을 가지게 된다. In addition, when the excessive etching of the pad oxide film 12 is reduced, the pad oxide film slope 200 may be formed by unetching or lacking a target of the pad oxide film 12, thereby recessing the subsequent semiconductor substrate 11. During etching, the pad oxide film has an unstable CD (critical dimension) along the pad oxide film slope 200.

상기한 본 발명은, 과도식각에 의한 실리콘 식각 불균일로 웨이퍼내 Vt 불안정 또는 리프레시 변화 등을 유발할 수 있고, 타겟 부족에 의한 패드산화막 경사 프로파일은 후속 리세스 되는 반도체 기판의 사이즈를 변화시킬 수 있다.The present invention described above may cause Vt instability or refresh change in the wafer due to uneven silicon etching due to excessive etching, and the pad oxide film inclination profile due to lack of target may change the size of the subsequently recessed semiconductor substrate.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로, 패드산화막에 대한 실리콘의 선택비를 증가시키고, 패드산화막의 슬로프문제를 해결하기위한 리세스 게이트를 갖는 반도체 소자의 제조방법을 제공하는데 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and provides a method for manufacturing a semiconductor device having a recess gate for increasing the selectivity of silicon to the pad oxide film and solving the slope problem of the pad oxide film. The purpose is to.

상기 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 반도체 기판상에 패드산화막을 형성하는 단계, 상기 패드산화막상에 하드마스크패턴을 형성 하는 단계, 상기 하드마스크패턴을 식각마스크로 하고 하이드로카본계 가스와 산소가스의 혼합가스를 이용하여 상기 패드산화막을 식각하는 단계, 상기 하드마스크패턴을 식각마스크로 하여 상기 패드산화막 식각 후 노출되는 반도체 기판을 식각하여 리세스게이트를 위한 리세스를 형성하는 단계를 포함한다.The method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a pad oxide film on a semiconductor substrate, forming a hard mask pattern on the pad oxide film, the hard mask pattern as an etching mask and a hydrocarbon Etching the pad oxide layer using a mixed gas of an oxygen-based gas and an oxygen gas, and etching the semiconductor substrate exposed after the pad oxide layer is etched using the hard mask pattern as an etch mask to form a recess for a recess gate Steps.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도 2a 내지 도 2d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체 기판(21) 상에 소자분리막(22)을 형성한다. 소자분리막(22)은 활성영역을 정의하기 위한 것으로, 적어도 3000Å의 깊이로 형성한다.As shown in FIG. 2A, the device isolation layer 22 is formed on the semiconductor substrate 21. The device isolation layer 22 is used to define an active region and is formed to a depth of at least 3000 microns.

이를 위해, 반도체 기판(21)의 소정영역을 식각하여 트렌치를 형성한다. 상기 트렌치에 절연막을 매립하고, 화학적기계적연마(Chemical Mechanical Polishing : CMP)로 분리하여 형성한다.To this end, a trench is formed by etching a predetermined region of the semiconductor substrate 21. An insulating film is embedded in the trench, and separated by chemical mechanical polishing (CMP).

이어서, 소자분리막(22) 상에 패드산화막(23)을 형성한다.Subsequently, a pad oxide film 23 is formed on the device isolation film 22.

다음으로, 패드산화막(23) 상에 하드마스크(24)를 형성한다. 여기서, 하드마스크(24)는 후속 반도체 기판(21)을 식각시 감광막(25)의 마진을 확보하기 위한 하 드마스크로 사용하기 위한 것으로, 폴리실리콘으로 형성한다.Next, a hard mask 24 is formed on the pad oxide film 23. Here, the hard mask 24 is used as a hard mask for securing the margin of the photosensitive film 25 when the subsequent semiconductor substrate 21 is etched, and is formed of polysilicon.

다음으로, 하드마스크(24) 상에 감광막(25)을 형성하고, 노광 및 현상으로 패터닝한다. 패터닝된 감광막(25)을 식각마스크로 하드마스크(24)를 식각한다.Next, a photosensitive film 25 is formed on the hard mask 24 and patterned by exposure and development. The hard mask 24 is etched using the patterned photoresist 25 as an etch mask.

따라서, 패드산화막(23) 상에 리세스 예정지역이 오픈된 하드마스크(24)와 감광막(25)를 순차적으로 형성할 수 있다.Accordingly, the hard mask 24 and the photosensitive film 25 having the recess scheduled region open on the pad oxide film 23 may be sequentially formed.

이어서, 감광막(25)을 산소플라즈마를 이용하여 제거한다. Subsequently, the photosensitive film 25 is removed using oxygen plasma.

도 2b에 도시된 바와 같이, 하드마스크(24)를 식각마스크로 패드산화막(23)을 식각한다. 여기서, 패드산화막(23)의 식각은 하이드로카본계 가스인 CHF3와 산소가스(O2)의 혼합가스를 이용하여 식각하되, CHF3는 20sccm∼60sccm, O2는 2sccm∼7sccm의 유량으로, 챔버의 압력은 3mT∼30mT, 탑파워를 300Ｗ∼1000Ｗ, 바텀파워를 100Ｗ∼500Ｗ로 하여 진행한다. As shown in FIG. 2B, the pad oxide layer 23 is etched using the hard mask 24 as an etch mask. Here, the etching of the pad oxide film 23 is etched using a mixed gas of CHF 3 and oxygen gas (O 2 ) which is a hydrocarbon gas, CHF 3 is 20sccm ~ 60sccm, O 2 is a flow rate of 2sccm ~ 7sccm, The chamber pressure is 3 mT to 30 mT, the top power is 300 kPa to 1000 kPa, and the bottom power is 100 kPa to 500 kPa.

상기 CHF3와 O3의 혼합가스를 사용하면, 반도체 기판(21)의 높은 식각선택비를 유지하여 반도체 기판(21)의 적은 손실로도 패드산화막(23)의 충분한 과도식각이 가능하고, 반도체 기판(21)의 손실 불균일 현상의 방지가 가능하다.When the mixed gas of CHF 3 and O 3 is used, a high etching selectivity of the semiconductor substrate 21 is maintained, and sufficient overetching of the pad oxide film 23 is possible even with a small loss of the semiconductor substrate 21. It is possible to prevent loss unevenness of the substrate 21.

특히, CHF3와 O2의 혼합가스에서 CHF3에 비하여 O2의 비율을 증가시킬수록 반도체 기판(21)의 식각선택비가 더 좋아진다.In particular, it becomes more to increase the proportion of O 2 in comparison to CHF 3 in the gas mixture of CHF 3 and O 2 prefer etching selectivity of the semiconductor substrate 21 ratio.

도 2c에 도시된 바와 같이, 하드마스크(24)를 식각마스크로 리세스 예정지역의 반도체 기판(26)을 식각하여 리세스(26)을 형성한다.As shown in FIG. 2C, the recess 26 is formed by etching the semiconductor substrate 26 in the region to be recessed using the hard mask 24 as an etch mask.

여기서, 리세스(26)의 형성은 HBr, Cl2와 O2의 혼합가스를 이용하여 1500Å∼2000Å의 깊이가 되도록 식각공정을 진행한다.Here, the formation of the recess 26 is performed by an etching process using a mixed gas of HBr, Cl 2 and O 2 to have a depth of 1500 kPa to 2000 kPa.

이후에, 패드산화막(25)과 식각잔류물의 제거를 위해 세정공정을 진행한다. 세정공정은 HF 또는 BOE 중에서 어느 하나로 실시한다.Thereafter, a cleaning process is performed to remove the pad oxide film 25 and the etching residues. The washing process is carried out with either HF or BOE.

다음으로, 라운딩공정을 실시한다. 이는 리세스(26)의 탑코너를 라운딩 시키기 위한 것으로, CDE(Chemical Dry Etch)방식으로 실시한다. CDE방식은 CF4 와 O2가 혼합된 플라즈마로 실시한다.Next, a rounding process is performed. This is to round the top corner of the recess 26, and is carried out by a chemical dry etching (CDE) method. The CDE method is performed by a plasma in which CF 4 and O 2 are mixed.

위와같이, CDE방식으로 리세스(26)의 탑코너가 라운딩 되어, 누설전류의 스트레스 포인트를 제거하므로 리프레시특성이 개선된다.As described above, the top corner of the recess 26 is rounded by the CDE method, thereby eliminating the stress point of the leakage current, thereby improving the refresh characteristics.

도 2d에 도시된 바와 같이, 리세스(26)가 포함된 반도체 기판(21)의 전면에 게이트절연막(27)을 형성한다.As shown in FIG. 2D, the gate insulating layer 27 is formed on the entire surface of the semiconductor substrate 21 including the recess 26.

이어서, 게이트절연막(27) 상에 리세스(26)에 일부가 매립되고, 나머지는 반도체 기판(21)의 상부로 노출된 게이트패턴(28)을 형성한다. Subsequently, a portion of the recess 26 is buried in the gate insulating layer 27, and the gate pattern 28 exposed to the upper portion of the semiconductor substrate 21 is formed.

게이트패턴(28)은 게이트전극(28a)과 게이트하드마스크(28b)가 순차적으로 적층된 구조를 갖는다. 여기서, 게이트전극(28a)는 폴리실리콘과 WSix가 적층된 구조로 형성하고, 게이트하드마스크(28b)는 Si3N4로 현성한다.The gate pattern 28 has a structure in which the gate electrode 28a and the gate hard mask 28b are sequentially stacked. Here, the gate electrode 28a is formed in a structure in which polysilicon and WSix are stacked, and the gate hard mask 28b is formed of Si 3 N 4 .

상기한 본 발명은, CHF3와 O2의 혼합가스로 실리콘의 식각선택비를 높여 패드산화막에 대해 충분한 과도식각을 진행하여 패드산화막의 수직한 프로파일을 형 성하고, 동시에 반도체 기판의 손실을 최소화 하여 식각 손실 불균일을 방지할 수 있다.In the present invention described above, the etching selectivity of the silicon is increased by the mixed gas of CHF 3 and O 2 to perform a sufficient transient etching on the pad oxide film to form a vertical profile of the pad oxide film, and at the same time minimize the loss of the semiconductor substrate. To prevent the loss of etching.

본 발명의 기술 사상은 상기 바람직한 실시예들에 따라 구체적으로 기록되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명에 의한 반도체 소자의 제조방법은 웨이퍼내 반도체 기판에 대한 식각 손실 불균일을 방지하고, 패드산화막의 수직한 프로파일을 형성하여 안정적인 리세스게이트 프로파일과 안정적인 전기적 특성을 향상 시킬 수 있는 효과가 있다.The manufacturing method of the semiconductor device according to the present invention described above has the effect of preventing the etching loss non-uniformity of the semiconductor substrate in the wafer, and to form a vertical profile of the pad oxide film to improve a stable recess gate profile and stable electrical characteristics. have.

Claims (7)

반도체 기판상에 패드산화막을 형성하는 단계;Forming a pad oxide film on the semiconductor substrate; 상기 패드산화막상에 하드마스크패턴을 형성하는 단계;Forming a hard mask pattern on the pad oxide layer; 상기 하드마스크패턴을 식각마스크로 하고 하이드로카본계 가스와 산소가스의 혼합가스를 이용하여 상기 패드산화막을 식각하는 단계; 및Etching the pad oxide layer using the hard mask pattern as an etching mask and using a mixed gas of a hydrocarbon-based gas and an oxygen gas; And 상기 하드마스크패턴을 식각마스크로 하여 상기 패드산화막 식각 후 노출된 반도체 기판을 식각하여 리세스게이트를 위한 리세스를 형성하는 단계Forming a recess for a recess gate by etching the exposed semiconductor substrate after the pad oxide layer is etched using the hard mask pattern as an etch mask 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 하이드로카본계가스는 CHF3 가스를 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.The hydrocarbon-based gas manufacturing method of a semiconductor device, characterized in that using the CHF 3 gas. 제2항에 있어서,The method of claim 2, 상기 혼합가스에서, 상기 CHF3 가스는 상기 산소가스보다 사용되는 유량이 더 큰 것을 특징으로 하는 반도체 소자의 제조방법.In the mixed gas, the CHF 3 gas is a semiconductor device manufacturing method, characterized in that the flow rate is larger than the oxygen gas used. 제3항에 있어서,The method of claim 3, 상기 혼합가스에서, 상기 CHF3 가스는 상기 산소가스 대비 3배 내지 30배의 유량을 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.In the mixed gas, the CHF 3 gas is a semiconductor device manufacturing method, characterized in that using a flow rate of 3 to 30 times the oxygen gas. 제4항에 있어서,The method of claim 4, wherein 상기 CHF3 가스의 유량은 20sccm∼60sccm으로, 상기 O2 가스의 유량은 2sccm∼7sccm으로 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.The flow rate of the CHF 3 gas is 20sccm ~ 60sccm, the flow rate of the O 2 gas is used in 2sccm ~ 7sccm. 제1항 내지 제5항에 있어서,The method according to claim 1, wherein 상기 패드산화막 식각은,The pad oxide film etching is, 압력은 3mT∼30mT, 탑파워는 300Ｗ∼1000Ｗ, 바텀파워는 100Ｗ∼500Ｗ의 조건으로 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.A pressure is 3 mT to 30 mT, the top power is 300 kPa to 1000 kPa, and the bottom power is 100 kPa to 500 kPa. 제1항 내지 제5항에 있어서,The method according to claim 1, wherein 상기 리세스를 형성하는 단계는 HBr, Cl2와 O2의 혼합가스를 사용하여 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.Forming the recess is a method of manufacturing a semiconductor device, characterized in that performed using a mixed gas of HBr, Cl 2 and O 2 .
KR1020050101241A 2005-10-26 2005-10-26 Method for fabricating the same of semiconductor device with recess gate KR20070044920A (en)

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