KR20070036494A - Method for forming semiconductor device - Google Patents

Abstract

The present invention provides a method for manufacturing a semiconductor device suitable for preventing a junction attack due to misalignment when forming a recess gate, the method for manufacturing a semiconductor device of the present invention for preparing a recessed semiconductor substrate; Forming a first gate insulating film on the recessed semiconductor substrate; Forming a plug filling the recess on the first gate insulating film; Removing the first gate insulating film; Forming a second gate insulating film on the semiconductor substrate from which the first gate insulating film is removed; Etching the second gate insulating layer using a mask, but leaving a portion of the second gate insulating layer to cover the edge of the recess; And forming a gate covering an edge of the plug on the second gate insulating layer.

Recess gate, misalignment, gate oxide

Description

 Semiconductor device manufacturing method {METHOD FOR FORMING SEMICONDUCTOR DEVICE}

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention;

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 device isolation film

23 recess 24 first gate oxide film

25a: plug 26: second gate oxide film

27: first photoresist pattern 28a: first gate conductive film

29a: second gate conductive film 30a: gate hard mask

31: second photoresist pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming a recess gate in a semiconductor device.

In general, a planar gate forming method is a method in which a gate is formed on an active region of a flat substrate. The gate channel length is gradually decreased due to the reduction of the pattern size, and is due to the increase in the electric field as the ion doping concentration increases. It is difficult to ensure the refreshing characteristics of the device due to one junction leakage.

As a gate forming method for improving this, a transistor structure having a recess channel having a gate formed through a recess formed in a semiconductor substrate as a semiconductor device is highly integrated to a level of 100 nm or less has been proposed.

This increases the effective channel length by forming a recess in the region where the channel of the transistor is to be formed, thereby improving the punch through effect in which the impurities of the source and drain diffuse laterally and substantially reducing the distance between the source and drain. Widen

In addition, since the source / drain junction and the channel formation region are formed in an elevated structure, junction leakage due to channel doping can be minimized, which ultimately helps high integration of semiconductor devices.

Therefore, by applying the recess gate process, it is possible to increase the channel length and reduce the ion doping concentration, thereby greatly improving the refresh characteristics of the device.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, a recess 13 is formed on a predetermined region of the semiconductor substrate 11 on which the device isolation film 12 is formed.

Next, the gate oxide film 14 is formed on the semiconductor substrate 11 including the recess 13.

Next, a polysilicon film 15 and a tungsten silicide 16 are laminated on the gate oxide film 14 as a gate conductive film, and a gate hard mask 17 is deposited on the tungsten silicide 16.

Subsequently, the photoresist pattern 18 is formed on the predetermined region of the gate hard mask 17.

As shown in FIG. 1B, the gate hard mask 17 is etched using the photoresist pattern 18 as an etch barrier, and the tungsten silicide 16 and polysilicon are etched using the etched gate hard mask 17a as an etch barrier. The film 15 is sequentially patterned to form a recess gate in which the gate oxide film 13 / polysilicon film 15a / tungsten silicide 16a / gate hard mask 17a are stacked.

At this time, the patterned polysilicon film 15, tungsten silicide 16, and gate hard mask 17 are abbreviated as polysilicon film 15a, tungsten silicide 16a, and gate hard mask 17a.

However, due to the reduction in the size of forming the resist pattern in the process of ultrafine patterning of the semiconductor device, alignment margins become weak during the recess gate patterning. As shown in FIG. 1C, the recess 13 and the recess are shown. Misalignment (A) between the set gates occurs, which causes difficulties in DRAM production due to problems such as a decrease in yield in manufacturing devices.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device suitable for preventing a junction attack caused by misalignment when forming a recess gate.

A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of preparing a semiconductor substrate having a recess, forming a first gate insulating film on the semiconductor substrate with a recess, the first gate insulating film Forming a plug filling the recess on the substrate; removing the first gate insulating layer; forming a second gate insulating layer on the semiconductor substrate from which the first gate insulating layer is removed; using a mask Etching the second gate insulating layer, leaving a portion of the second gate insulating layer to cover the edge of the recess, and forming a gate covering the edge of the plug on the second gate insulating layer. .

The present invention also provides a method for preparing a semiconductor substrate including a recess, forming a first gate insulating film on the recessed semiconductor substrate, and forming a conductive film on the first gate insulating film to fill the recess. Forming a plug by planarizing etching the conductive layer using the first gate insulating layer as an etch target, and forming a second gate insulating layer on the entire surface of the resultant product on which the plug is formed, wherein the plug is thickly formed on the side surface of the plug; A blanket dry etching of the second gate insulating film on the plug, and forming a gate on the plug.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

(First embodiment)

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

As shown in FIG. 2A, the isolation layer 22 is formed on the semiconductor substrate 21 using a shallow trench isolation (STI) process. Next, the recess 23 is formed in a predetermined region of the semiconductor substrate 21 to form the recess 23.

The recess 23 selectively etches a predetermined thickness of the semiconductor substrate 21 using a polysilicon hard mask (not shown) on a predetermined region of the semiconductor substrate 21, and then removes the polysilicon mask. It is formed by carrying out the process.

Subsequently, a gate oxide film SiO ₂ is formed on the entire surface of the semiconductor substrate 21 on which the recess 23 is formed by thermal oxidation. In this case, the gate oxide film is referred to as a first gate oxide film 24.

On the other hand, the first gate oxide film 24 is formed to a thickness of 30 to 70 GPa, and the plug conductive film 25 is deposited by filling the recess 23 until the recess 23 is filled on the first gate oxide film 24. Landfill 23). As the plug conductive film 25, for example, a polysilicon film is used.

As shown in FIG. 2B, the first gate oxide layer 24 is used as a barrier under a plasma source of TCP (Transformer Coupled Plasma) / ICP (Inductively Coupled Plasma) type, with a pressure of 50 to 200 mT, a source power of 300 to 1000 mW, and 100 With a bias power of ˜400 kW, chlorine plasma Cl ₂ was flowed at a flow rate of ₃₀ to 100 sccm, HBr was flowed at 30 to 200 sccm, and subjected to etch back or chemical mechanical polishing (CMP). The plug conductive film 25 is polished to form a plug 25a embedded in the recess 23. At this time, the plug 25a is the lower electrode layer of the recess gate.

As shown in FIG. 2C, after forming the plug 25a embedded in the recess 23, the first gate oxide film remaining on the semiconductor substrate 21 using hydrofluoric acid solution (HF) or BOE solution ( 24) Remove.

As shown in FIG. 2D, the second gate oxide layer 26 is formed on the entire surface of the semiconductor substrate 21 from which the first gate oxide layer 24 is removed.

As shown in FIG. 2E, a first photoresist pattern 27 is formed on a predetermined region of the second gate oxide layer 26.

In this case, the first photoresist pattern 27 is formed on the second gate oxide layer 26, and covers the expected region of misalignment, that is, the recess corner, with respect to the subsequent recess gate pattern size. The second gate oxide film 26 is formed for the open pattern to have a width smaller than the line width. At this time, the open area of the first photoresist pattern is smaller than the line width of the recess.

Accordingly, the second gate oxide layer 26 may be selectively etched by applying the source and bias power in a solid direction under a TCP / ICP type plasma source using the first photoresist pattern 27 as a barrier to thereby plug 25a. ).

More specifically, the Florin-based plasmas C _x F _y and CHF _z (x, y, z are 1 to 10) at a pressure of 30 to 100 mT and an applied power of 300 to 500 mW under a high density plasma source of TCP / ICP type The second gate oxide film 26 is etched by mixing at a ratio of 1: 1: 2 and adding a reaction gas (eg, Ar). At this time, since the second gate oxide layer 26 is formed to cover the recess edge portion after etching, even if the recess gate and the plug 25a are misaligned in a subsequent process, a short with the landing plug can be prevented. have.

As shown in FIG. 2F, the first photoresist pattern 27 is stripped, and the material film 28 for the first gate conductive film, the material film 29 for the second gate conductive film, and the gate hard on the front surface of the resultant. The mask material film 30 is sequentially deposited.

In this case, the first gate conductive film 28 is made of, for example, a polysilicon film, the second gate conductive film 29 is made of tungsten silicide, and the gate hard mask material film 30 is formed of a nitride film. use.

Subsequently, a second photoresist pattern 31 is formed on a predetermined region of the gate hard mask material film 30.

As shown in FIG. 2G, a recess gate patterning process is performed using the second photoresist pattern 31 as an etching mask.

First, the gate hard mask 30a is formed by etching the gate hard mask material layer 30 using the second photoresist pattern 31 as an etching mask.

Subsequently, the second photoresist pattern 31 is stripped, and the gate hard mask 30a is used as an etch barrier to sequentially etch the second gate conductive film material layer 29 and the first gate conductive film material film 28. The gate conductive film 29a and the first gate conductive film 28a are formed.

Through the above-described series of processes, the recess gate is formed in a structure in which the plug 25a, the first gate conductive layer 28a, the second gate conductive layer 29a, and the gate hard mask 30a are stacked.

Therefore, after the gate patterning, the plug 25a, the first gate conductive film 28a, and the second gate conductive film 29a are formed on the gate oxide film using the first gate oxide film 24 and the second gate oxide film 26 as gate oxide films. ) And a recess gate 200 in which the gate hard mask 30a is stacked.

As shown in FIG. 2H, even when misalignment occurs in the recess gate patterning, the second gate oxide layer 26 is formed in a structure covering the corners of the recess 23 during the recess gate patterning. Complementary weak point areas can be prevented to prevent shorting of subsequent recess gates and landing plugs due to misalignment.

Second Embodiment

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

As shown in FIG. 3A, the isolation layer 22 is formed on the semiconductor substrate 21 using a shallow trench isolation (STI) process. Next, the recess 23 is formed in a predetermined region of the semiconductor substrate 21 to form the recess 23.

The recess 23 selectively etches a predetermined thickness of the semiconductor substrate 21 using a polysilicon hard mask (not shown) on a predetermined region of the semiconductor substrate 21, and then removes the polysilicon mask. It is formed by carrying out the process.

Subsequently, a gate oxide film SiO ₂ is formed on the entire surface of the semiconductor substrate 21 on which the recess 23 is formed by thermal oxidation. In this case, the gate oxide film is referred to as a first gate oxide film 24.

On the other hand, the first gate oxide film 24 is formed to a thickness of 30 to 70 GPa, and the plug conductive film 25 is deposited by depositing the recesses 23 until the recess 23 is filled on the first gate oxide film 24. Landfill 23). As the plug conductive film 25, for example, a polysilicon film is used.

As shown in FIG. 3B, the first gate oxide layer 24 is used as a barrier under a plasma source of a TCP (Transformer Coupled Plasma) / ICP (Inductively Coupled Plasma) type, having a pressure of 50 to 200 mT, a source power of 300 to 1000 mW, and 100 At a bias power of ˜400 kW, chlorine-based plasma Cl ₂ is flowed at a flow rate of ₃₀ to 100 sccm, HBr is flowed at 30 to 200 sccm, and etched back. Alternatively, chemical mechanical polishing (CMP) is performed to polish the plug conductive film 25 to form a plug 25a embedded in the recess 23. At this time, the plug 25a is the lower electrode layer of the recess gate.

As shown in FIG. 3C, a blanket etch is performed without a mask on which the plug is formed to selectively remove only the second gate oxide layer 26 on the plug 25a to expose the plug 25a.

On the other hand, the second gate oxide layer 26 is thickly formed at the corners of the recess 23 and is thinly formed on the plug 25a only by the second gate oxide layer 26 on the plug 25a. By etching, the edge of the recess 23, that is, the misalignment weak point is formed thick, and may compensate for the misaligned region.

More specifically, the second gate oxide layer 26 may be etched in the form of a blanket spacer to prevent misalignment failure by the plug 25a and the second gate oxide layer 26 even when misalignment occurs between the plug 25a and the gate line. It can be.

As shown in FIG. 3D, the first gate conductive layer 27, the second gate conductive layer 28, and the gate hard mask 29 are formed on the result of the blanket etching of the second gate oxide layer 26 to open the plug. Stacked to form a recess gate 200.

As described above, in order to form a plug in the recess and to prevent an area in which misalignment occurs, the second gate oxide film is thickly left at the misalignment weak point of the recess top portion, and then the recess process is performed to perform subsequent recess gate patterning. Even if the misalignment between the recess and the gate occurs, the short between the landing plug and the gate can be prevented due to the first gate oxide film.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

In the above-described invention, the gate gate is free from the misalignment problem because the gate gate is separated from the gate polysilicon in the weak point recess region of the misalignment point by the second gate oxide patterned in the misalignment margin size during the recess gate etching. Can increase the channel length and decrease the ion doping concentration.

In addition, since the refresh characteristics of the device are greatly improved, it is possible to secure design rules and maximize process margins, thereby achieving effects such as high integration of semiconductor devices including logic, improved yields, and reduced production costs.

Claims (12)

Preparing a recessed semiconductor substrate; Forming a first gate insulating film on the recessed semiconductor substrate; Forming a plug formed on the first gate insulating layer and filling the recess; Removing the first gate insulating film on the semiconductor substrate; Forming a second gate insulating film on the semiconductor substrate from which the first gate insulating film is removed; Etching the second gate insulating layer using a mask, but leaving a portion of the second gate insulating layer to cover the edge of the recess; And Forming a gate to span an edge of the plug and the recess Semiconductor device manufacturing method comprising a. The method of claim 1, Forming a plug to fill the recess on the first gate insulating film, Forming a plug conductive film on the semiconductor substrate on which the first gate insulating film is formed until the recess is filled; And planarization etching the plug conductive film. The method of claim 2, The planarization etching is a semiconductor device manufacturing method which proceeds by etch back or chemical and mechanical polishing. The method of claim 3, wherein And the etch back is flattened and etched under a TCP / ICP type plasma source at a pressure of 50 kPa to 200 mT, a source power of 300 to 1000 kPa, and a bias power of 100 to 400 kPa. The method of claim 3, wherein The etch back is, A method of manufacturing a semiconductor device, wherein the chlorine-based plasma is Cl ₂ with 30 to 100 sccm and HBr with 30 to 200 sccm. The method of claim 1, The removing of the first gate insulating film may include: A semiconductor device manufacturing method using a hydrofluoric acid solution (HF) or a BOE solution. The method of claim 1, The mask is, And forming a width smaller than a line width of the recess gate while covering the recess edge. The method of claim 1, Etching the second gate insulating layer using the mask, but leaving a portion of the second gate insulating film to cover the edge of the recess, Under a high density plasma source of TCP / ICP type, the reaction gas is mixed at a ratio of 1: 1 to 1: 2 by mixing Florin-based plasma C _x F _y and CHF _z at a pressure of 30 to 100 mT and a source power of 300 to 500 kW. The method of manufacturing a semiconductor device by etching the second gate insulating film by adding. The method of claim 1, The plug is a semiconductor device manufacturing method of forming a polysilicon film. Preparing a recessed semiconductor substrate; Forming a first gate insulating film on the recessed semiconductor substrate; Filling the recess by forming a conductive film on the first gate insulating film; Forming a plug by planarizing etching the conductive layer using the first gate insulating layer as an etching target; Forming a second gate insulating film on the entire surface of the resultant product in which the plug is formed, and being thickly formed on the side surface of the plug; A blanket dry etching of the second gate insulating layer on the plug; And Forming a gate on the plug Semiconductor device manufacturing method comprising a. The method of claim 10, The first gate insulating film and the second gate insulating film are silicon oxide films. The method of claim 9, The plug is a semiconductor device manufacturing method of forming a polysilicon film.

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