KR20070035942A - Semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor design technology, and more particularly, to provide a semiconductor memory device that detects a defect in a data transmission line irrespective of a cell core region including a memory cell. In the failure detection circuit of the data transmission line of the device, the data transmission unit for controlling the data transmission between the local input / output line and the global input / output line, the read signal and the write signal and the local input / output line reset signal to generate the A data decoder controlling a data transmitter, a column decoder controlling a data transfer between a memory cell and the local input / output line by outputting a column select signal, and the read signal or the column select signal and the column signal according to a test mode signal. A test mode control unit for preventing activation of a local input / output line reset signal; The present invention provides a semiconductor memory device including a first data temporary storage and a second data temporary storage located at the local input / output line.

Data transmission line, cell core area, defect detection circuit, state machine, local input / output line, global input / output line

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

1 is a block diagram illustrating a general semiconductor memory device.

2A and 2B are timing diagrams of the semiconductor memory device of FIG.

3 is a view for explaining a failure detection method of a data transmission line of a semiconductor memory device according to an embodiment of the present invention.

4A and 4B are circuit diagrams illustrating a test mode control unit 211.

5A and 5B are timing diagrams of a semiconductor memory device using a first data store as a temporary store of data.

6A and 6B are timing diagrams of a semiconductor memory device using a second data store as a temporary store of data.

Explanation of symbols on the main parts of the drawings

201: state machine 203: decoder unit

205: cell core area 207: first data transfer control unit

209: test mode control unit 211: test mode control unit

213: first data transmission unit 215: second data transmission unit

217: first data storage 219: second data transmission control unit

221: data pin 223: second data storage

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a data transmission line failure detection circuit of a semiconductor memory device.

As a typical semiconductor memory device (DRAM), an increase in data throughput per unit time is required according to a change in surrounding environment. Accordingly, the external clock frequency (CLK Frequency) of the DRAM which inputs / outputs data in synchronization with the external clock CLK is also increasing. In this situation, when the internal circuit of the DRAM becomes more diversified and complicated, and the designed product is actually manufactured, it is more difficult to interpret the defect than the past when a defect occurs. In this case, the defect means that most of the data written to the memory is not normally output when the data is read again.

In the case of a defective data output abnormally, there can be a variety of causes, typically an abnormal output due to a defective memory cell itself of the DRAM, or errors in the process of amplifying the cell data, or cell data After amplification normally, there are errors in the transmission and other logic configuration errors.

In particular, the higher the speed, the more errors and marginal defects of the logic part that require synchronization to the external clock CLK appear. This becomes a delay factor in product development, which is a problem of falling behind the competition.

1 is a block diagram illustrating a general semiconductor memory device.

Referring to FIG. 1, a semiconductor memory device receives a clock CLK, a cas signal (/ CAS), a Lars signal (/ RAS), and the like, and defines a state machine 101 for defining an internal operation of the semiconductor memory device. A decoder unit 103 for selecting memory cells in response to the output signals RASACT, CASACT, and Address of the device 101, a cell core region 105 including a plurality of memory cells, and read / write commands. A first data transmitter control unit 107 for controlling the first data transmitter 109 by outputting a read signal RDEN, a local input / output line reset signal LIORSTB, and a write signal WDEN in response to the " A second data transfer control unit 113 for controlling the second data transfer unit 111 in response to an output signal of the state machine 101, a memory cell of the cell core region 105, and a first data transfer unit 109; Local I / O line (LIOi) for transmitting data between the data, the first data transmission unit 109 and the second data transmission unit 111 to transmit data And a I / O line (GIOi), data pin 115 to send and receive data from the outside.

Here, the first data transmission unit 109 includes a write receiver and a driver, a read amplifier and a driver, and the second data transmission unit 111 includes a read receiver and a driver, a write amplifier and a driver, and a data input / output path. do.

The operation of the semiconductor memory device according to time will be described below.

2A and 2B are timing diagrams of the semiconductor memory device of FIG. 1 and will be described with reference to the reference numerals of FIG. 1.

First, referring to FIG. 2A, in the write operation, write data is applied to the data pin 115 by the write command, and the write data is applied to the global input / output line GIOi by the second data transfer unit 111. Delivered.

The local input / output line reset signal LIORSTB and the write signal WDEN, which are output signals of the first data transmission controller 107, are deactivated and activated, respectively. This is a task for delivering write data to the local input / output line (LIOi).

At this time, in response to the rising edge of the write signal WDEN to the logic level high, the write data causes a potential difference in the local input / output lines LIO and LIOB.

Subsequently, in response to a potential difference between the local input / output lines LIO and LIOB, a column select signal for driving the YI transistor (a transistor connecting the bit line and the local input / output lines LIO and LIOB) YI) is activated to transfer the potential difference to the bit line.

The potential difference between the local input / output lines LIO and LOIB disappears in response to the falling edge of the local input / output line reset signal LIORSTB to the logic level low. That is, the operation of transferring the write data to the memory cell of the cell core region 105 is finished.

Next, referring to FIG. 2B, as a read operation, the local input / output line reset signal LIORSTB is deactivated by the read command, and the column select signal YI is activated to drive the YI transistor. Accordingly, the read data of the memory cell in the cell core region 105 is transferred (potential difference induced) to the local input / output lines LIO and LIOB.

Subsequently, by the activation of the read signal RDEN, the potential difference (lead data) of the local input / output lines LIO and LIOB is transmitted to the global input / output line GIOi and output through the data pin 115.

As described above, in a general semiconductor memory device, write data is written to the cell core region 105 via the data pin 115, and read data of the cell core region 105 exits to the outside via the data pin 115.

In this case, in order to detect a failure of the data transmission line, the cell core region 105 is tested under the condition that there is no defect.

However, since the cell core region 105 is the finest and finest region in the semiconductor memory device, various defects appear in reality. Therefore, it is difficult to detect a failure of a data transmission line operating under complicated timing control due to a failure of the cell core region 105, resulting in a long development period.

That is, the failure detection of the data transmission line means detecting the case where the read data becomes abnormal in the process of checking the transmission state through normal read data (data transmitted from the memory cell to the outside). At this time, when the data transmission line is tested with the lead data which is already in an abnormal state, it is difficult to detect a defect of the correct data transmission line.

The present invention has been proposed to solve the above problems of the prior art, and a first object of the present invention is to provide a semiconductor memory device that detects a defect in a data transmission line irrespective of a cell core region including a memory cell. .

Another object of the present invention is to provide a semiconductor memory device which detects a failure between a data pin and a local input / output line.

Another object of the present invention is to provide a semiconductor memory device that detects a failure between a data pin and a global input / output line.

According to an aspect of the present invention for achieving the above technical problem, in the defect detection circuit of the data transmission line of the semiconductor memory device, a data transmission unit for controlling data transmission between the local input / output line and the global input / output line A data transfer controller controlling the data transfer unit by generating a read signal, a write signal, and a local input / output line reset signal, and a column for controlling data transfer between the memory cell and the local input / output line by outputting a column selection signal. A decoder, a test mode control unit for preventing activation of the read signal or the column selection signal and the local input / output line reset signal according to a test mode signal, a first data temporary storage located at the global input / output line, and the local input A semiconductor memory device including a second data temporary storage located at the output line.

In the defect detection circuit of the data transfer line of the semiconductor memory device, a data transfer unit controlling data transfer between a local input / output line and a global input / output line, and generating a read signal and a write signal to control the data transfer unit. According to an aspect of the present invention, there is provided a semiconductor memory device including a data transfer control unit, a test mode control unit which prevents activation of the read signal according to a test mode signal, and a first data temporary storage located at the global input / output line.

In addition, in the defect detection circuit of the data transmission line of the semiconductor memory device, the data transmission unit for controlling the data transfer between the local input / output line and the global input / output line, the local input / output line reset signal to generate the data transfer A data decoder controlling a unit; a column decoder unit controlling a data transfer between a memory cell and the local input / output line by outputting a column selection signal; and resetting the column selection signal and the local input / output line according to a test mode signal. The present invention provides a semiconductor memory device including a test mode control unit preventing a signal from being activated and a second data temporary storage located at the local input / output line.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a view for explaining a failure detection method of a data transmission line of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, the semiconductor memory device receives a clock CLK, a cas signal (/ CAS), a las signal (/ RAS), and the like, and defines a state machine 201 that defines an internal operation of the semiconductor memory device. Decoder unit 203 for selecting memory cells in response to output signals RASACT, CASACT, and Address of the device 201, a cell core region 205 including a plurality of memory cells, read / write commands (Read / Write) In response to the output signal of the first data transmission controller 207 and the state machine 201 to output the read signal RDEN, the local input / output line reset signal LIORSTB, and the write signal WDEN. The local data input / output line for transmitting data between the second data transmission control unit 219 controlling the second data transmission unit 215 and the memory cell of the cell core region 205 and the first data transmission unit 213 ( LIOi), a global input / output line (GIOi) for transmitting data between the first data transmission unit 213 and the second data transmission unit 215, from the outside Data signals TLCHECK0 and TLCHECK1 of the test mode determination unit 209 and the test mode determination unit 209 which determine the test mode entry in response to the output signals of the data pin 221 and the state machine 201 that send and receive data. In response to the test mode control unit 211 to control the first data transmission unit 213, located in the global input / output line (GIOi), the temporary storage of write data (data transmitted to the memory cell from the outside) A second data store 223 is disposed in the first data store 217 and the local input / output line LIOi to temporarily store the write data.

Here, the first data transmission unit 213 includes a write receiver and a driver, a read amplifier and a driver, and the second data transmission unit 215 includes a read receiver and a driver, a write amplifier and a driver, and a data input / output path. do.

The first data storage 217 and the second data storage 223 may be selectively provided depending on how far the data pin 221 detects a failure of the data transmission line.

That is, the first data storage 217 is used to check the transmission status of the second data transmission unit 215, and the first data storage 217 is used to check the transmission status of the first and second data transmission units 213 and 215. 2 data storage 223 is used.

In addition, the first data store 217 may be an inverter type latch circuit, and the second data store 223 may be implemented as a local input / output line LIOi itself.

Referring to the operation when the first data storage 217 is used, when write data is input through the data pin 221, the test mode determination unit 209 selects the first test mode signal TLCHECK0. ) In this case, the first test mode signal TLCHECK0 is a signal for selecting the first data storage 217 as a temporary storage of write data.

Subsequently, the write data is temporarily stored in the first data store 217 after passing through the second data transfer unit 215. At this time, the failure detection of the circuit located before the first data storage 217 is performed. That is, it monitors whether the write data is normally transmitted.

The write data is written to the memory cells of the cell core region 205 after passing through the first data transfer unit 213.

Thereafter, the read data of the memory cell is transferred to the first data transfer unit 213 through the local input / output line LIOi. At this time, the test mode controller 211 receiving the first test mode signal TLCHECK0 prevents the read data from being transmitted to the global input / output line GIOi, which is read from the test mode controller 211. This prevents the read data from being transmitted by preventing the signal RDEN from being activated.

Subsequently, the write data temporarily stored in the first data storage 217 is output and transmitted to the second data transmission unit 215, and finally transferred to the outside through the data pin 221.

In summary, after the write data is temporarily stored in the first data store 217 during the write operation, the read data output from the memory cell during the read operation is prevented from being transmitted by the first data transfer unit 213. Thereafter, the write data temporarily stored in the first data storage 217 is transmitted to the outside. That is, a failure is detected by monitoring data transmission between the data pin 221 and the second data transfer unit 215 during the write operation and the read operation.

Next, the operation when using the second data store 213 will be described. When write data is input through the data pin 221, the test mode determiner 209 selects the second test mode signal to select a temporary store. Print (TLCHECK1). In this case, the second test mode signal TLCHECK1 is a signal for selecting the second data store 213 as a temporary store of write data.

Subsequently, the write data is temporarily stored in the second data store 223 located in the local input / output line LIOI after passing through the second data transmitter 215 and the first data transmitter 213. At this time, the failure detection of the data transmission circuit located before the second data store 223 is performed. The write data is then written to the memory cells of the cell core region 205.

At this time, the test mode control unit 211 prevents the local input / output line reset signal LIORSTB from being activated so that the write data is temporarily stored in the local input / output line LIOi. That is, the write data is temporarily stored in the second data storage 223.

Subsequently, according to the read operation, read data of the memory cell is loaded on the bit line. At this time, the test mode control unit 211 prevents activation of the column selection signal YI, which is a driving signal of the YI transistor, thereby preventing the read data from the memory cell from being transmitted to the local input / output line LIOi.

Therefore, the read data according to the subsequent read operation uses write data temporarily stored in the second data storage 211.

In summary, after the write data is temporarily stored in the second data store 223 during the write operation, the read data output from the memory cell during the read operation is prevented from driving by not driving the YI transistor. Thereafter, the write data temporarily stored in the second data store 223 is transmitted to the outside. That is, the data is detected between the data pin 221 and the first data transfer unit 213 during the write operation and the read operation to detect a failure.

As a result, the first data storage 217 and the second data storage 223 are used as temporary storage of the write data, and the write data is read in a state in which the read data output from the cell core region 205 is prevented from being transferred. It is used as data in operation to detect a defect in the data transmission line. That is, the defect of the data transmission line is detected regardless of the cell core region 205 where the defect frequently occurs.

4A and 4B are circuit diagrams illustrating the test mode control unit 211 and will be described with reference to the reference numerals of FIG. 3.

First, referring to FIG. 4A, the second data storage 223 is used as a temporary storage. In order to prevent the local input / output line LIOi from being reset, the test mode control unit 211 has a local input / output. Inverts the output signal of the first NOR1 and the first NOR1 to which the output line reset signal LIORSTB and the second test mode signal TLCHECK1 are input, and inverts the output signal to the second test mode signal TLCHECK1. The first inverter INV1 outputs the local input / output line reset signal RSTB-NEW controlled by the controller.

Next, referring to FIG. 4B, when the first data storage 217 is used as a temporary storage, the test mode control unit 211 uses the first test mode signal to prevent the read signal RDEN from being activated. Output signals of the first NAND gate NAND1 and the first NAND gate NAND1 that input the second inverter INV2 for inverting TLCHECK0, the output signal of the read signal RDEN, and the second inverter INV2. The third inverter INV3 outputs the read signal RDEN-NEW controlled by the first test mode signal TLCHECK0.

5A and 5B are timing diagrams of a semiconductor memory device using a first data storage as a temporary storage of data, and will be described with reference to FIG. 3.

First, referring to FIG. 5A, in the write operation, write data is applied to the data pin 221 by a write command, and the write data is applied to the global input / output line GIOi by the second data transfer unit 215. Delivered. In this case, the first test mode signal TLCHECK0 is output from the test mode determiner 209 to select the first data store 217. Accordingly, the first data store (GIOi) located in the global input / output line GIOi may be used. In 217, the write data is temporarily stored.

Subsequently, the local input / output line reset signal LIORSTB and the write signal WDEN, which are output signals of the first data transmission controller 213, are deactivated and activated, respectively. This is a task for delivering write data to the local input / output line (LIOi).

At this time, in response to the rising edge of the write signal WDEN to the logic level high, the write data causes a potential difference in the local input / output lines LIO and LIOB.

Subsequently, in response to a potential difference between the local input / output lines LIO and LIOB, a column select signal for driving the YI transistor (a transistor connecting the bit line and the local input / output lines LIO and LIOB) YI) is activated to transfer the potential difference to the bit line.

The potential difference between the local input / output lines LIO and LOIB disappears in response to the falling edge of the local input / output line reset signal LIORSTB to the logic level low. That is, the process of transferring the write data to the memory cell of the cell core region 205 is completed.

Next, referring to FIG. 5B, as a read operation, the local input / output line reset signal LIORSTB is deactivated by the read command, and the column select signal YI is activated to drive the YI transistor. Accordingly, the read data of the memory cells in the cell core region 205 is transferred (potential difference induced) to the local input / output lines LIO and LIOB.

Subsequently, the read signal RDEN output from the first data transfer controller 207 is deactivated (RDEN-NEW) by the test mode controller 211 and transferred to the first data transfer unit 213. That is, the read data located in the local input / output line LIOi is prevented from being transmitted to the global input / output line GIOi.

Subsequently, the write data previously stored in the first data store 217 is output and transmitted to the outside.

6A and 6B are timing diagrams of a semiconductor memory device using a second data storage as a temporary storage of data, and will be described with reference to FIG. 3.

First, referring to FIG. 6A, in the write operation, write data is applied to the data pin 221 by a write command, and the write data is applied to the global input / output line GIOi by the second data transfer unit 215. Delivered.

Subsequently, the local input / output line reset signal LIORSTB and the write signal WDEN, which are output signals of the first data transmission controller 213, are deactivated and activated, respectively. This is a task for delivering write data to the local input / output line (LIOi).

At this time, in response to the rising edge of the write signal WDEN to the logic level high, the write data causes a potential difference in the local input / output lines LIO and LIOB.

Subsequently, in response to a potential difference between the local input / output lines LIO and LIOB, a column select signal for driving the YI transistor (a transistor connecting the bit line and the local input / output lines LIO and LIOB) YI) is activated to transfer the potential difference to the bit line.

At this time, the second test mode signal TLCHECK1 is output from the test mode determiner 209 to control the test mode controller 211. Accordingly, the test mode control unit 211 prevents the local input / output line reset signal LIORSTB from being activated (RDEN-NEW) to prevent the write data from disappearing from the local input / output line LIOi. That is, the write data is temporarily stored in the second data storage 223.

Next, referring to FIG. 6B, as a read operation, the test mode controller 211 prevents the column selection signal YI from being activated (YI-NEW) so that the read data from the memory cell is local input / output line. Prevents passing to (LIOi).

Subsequently, the second data storage unit 223 outputs the temporarily stored write data to the first data transmission unit 213, which is a global input / output line (GIOi), the second data transmission unit 215, and a data pin. It is transmitted to the outside via 221.

As described above, the first data storage 217 and the second data storage 223 are used as temporary storages of the write data, and the write data is prevented from being transmitted to the read data output from the cell core region 205. This is used as data during the read operation to detect a defect in the data transmission line. That is, the defect of the data transmission line is detected regardless of the cell core region 205 where the defect frequently occurs.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, since the type and arrangement of the logic used in the above-described embodiment is implemented as an example in which both the input signal and the output signal are high active signals, the implementation of the logic may also change when the active polarity of the signal is changed. There is no such embodiment, because the number of cases is too large, and the change in the embodiment is a matter that can be easily technically inferred by those skilled in the art of the present invention belongs directly to each case I will not mention it.

In addition, in the above-described embodiment, the test mode determination unit 209, the test mode control unit 211, and the first data storage 217 have been described as an example of implementing a plurality of logic circuits. It is just an implementation.

As described above, the present invention can detect a defect in a data transmission line regardless of a cell core region in which a defect frequently occurs due to a complicated structure.

Therefore, the defect detection area of the semiconductor memory device can be reduced, and the cause of the defect can be quickly dealt with, thus securing the product competitiveness.

Claims (16)

In a defect detection circuit of a data transmission line of a semiconductor memory device, A data transmission unit controlling data transmission between the local input / output line and the global input / output line; A data transmitter controlling a data transmitter by generating a read signal, a write signal, and a local input / output line reset signal; A column decoder to output a column select signal to control data transfer between a memory cell and the local input / output line; A test mode controller which prevents activation of the read signal or the column selection signal and the local input / output line reset signal according to a test mode signal; A first data temporary store located at the global input / output line; And Second data temporary storage located at the local input / output line Semiconductor memory device comprising a. The method of claim 1, The test mode signal is output from a test mode determiner, wherein the first test mode signal is a signal for selecting a first data temporary storage, and the second test mode signal is a signal for selecting a second data temporary storage. Semiconductor memory device. The method of claim 2, The test mode control unit, A read signal deactivator for preventing activation of the read signal; A column selection signal inactivation unit for preventing activation of the column selection signal; And And a local input / output line reset signal deactivation unit for preventing activation of the local input / output line reset signal. The method of claim 3, The read signal deactivation unit, A first inverter for inverting the first test mode signal; A first NAND gate inputting the read signal and the output signal of the first inverter; And And a second inverter for inverting the output signal of the first NAND gate. The method of claim 3, The local input / output line reset signal deactivation unit, A first NOR gate configured to receive the second test mode signal and a local input / output line reset signal; And And a third inverter for inverting the output signal of the first NOR gate. The method of claim 1, And the first data temporary storage and the second data temporary storage are selectively provided according to a defect detection area of a data transmission line. The method of claim 1, And the first data temporary storage is an inverter type latch circuit. The method of claim 1, And the second data temporary storage is a local input / output line itself. In a defect detection circuit of a data transmission line of a semiconductor memory device, A data transmission unit controlling data transmission between the local input / output line and the global input / output line; A data transmission unit controller which generates a read signal and a write signal to control the data transmission unit; A test mode control unit which prevents activation of the read signal according to a test mode signal; And A first data temporary storage located at the global input / output line Semiconductor memory device comprising a. The method of claim 9, The test mode control unit, A fourth inverter for inverting the first test mode signal; A second NAND gate inputting the read signal and the output signal of the first inverter; And And a fifth inverter for inverting the output signal of the second NAND gate. The method of claim 9, And the first data temporary storage is an inverter type latch circuit. In a defect detection circuit of a data transmission line of a semiconductor memory device, A data transmission unit controlling data transmission between the local input / output line and the global input / output line; A data transmission unit control unit generating a local input / output line reset signal to control the data transmission unit; A column decoder to output a column select signal to control data transfer between a memory cell and the local input / output line; A test mode controller which prevents activation of the column selection signal and the local input / output line reset signal according to a test mode signal; Second data temporary storage located at the local input / output line Semiconductor memory device comprising a. The method of claim 12, The test mode signal is output from a test mode determiner, wherein the first test mode signal is a signal for selecting a first data temporary storage, and the second test mode signal is a signal for selecting a second data temporary storage. Semiconductor memory device. The method of claim 13, The test mode control unit, A column selection signal inactivation unit for preventing activation of the column selection signal; And And a local input / output line reset signal deactivation unit for preventing activation of the local input / output line reset signal. The method of claim 14, The local input / output line reset signal deactivation unit, A second NOR gate configured to receive the second test mode signal and a local input / output line reset signal; And And a sixth inverter for inverting the output signal of the second NOR gate. The method of claim 13, And the second data temporary storage is a local input / output line itself.

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