KR100939117B1 - Semiconductor memory apparatus and method for reliable data access - Google Patents

Abstract

The present invention allows a semiconductor memory device to guarantee reliable column access operation even in the event of environmental changes or changes in operating frequency. To this end, the semiconductor memory device according to the present invention detects and amplifies data applied to a local data line in response to a read command and starts transmitting the data to a global data line. Internal control circuitry for disconnecting data lines. Accordingly, the present invention can prevent the degradation of data reliability that may occur in transferring data applied to the local data line to the global data line even in the case of environmental changes such as process, voltage level, temperature, or change in operating frequency.

Memory device, column command, semiconductor, column access, column select signal

Description

Semiconductor memory device and method thereof for stable data access {SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR RELIABLE DATA ACCESS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device capable of operating at high speed, and more particularly, to an apparatus for stably securing an operation margin necessary for performing internal operations for data access, even in environmental changes such as processes, voltage levels, and temperatures. It is about a method.

In a system composed of a plurality of semiconductor devices, the semiconductor memory device is for storing data. When data is requested from a data processing device such as a central processing unit (CPU), the semiconductor memory device outputs data corresponding to an address input from a device requesting data, or at a position corresponding to the address. Stores data provided from the data requesting device.

As the operating speed of a system composed of semiconductor devices has increased and the technology related to semiconductor integrated circuits has been developed, semiconductor memory devices have been required to output or store data at a higher speed. In order for a semiconductor memory device to operate safely at a higher speed, several circuits in the semiconductor memory device must be able to operate at a high speed, and also a signal or data can be transferred at a high speed.

In practice, the operation of the semiconductor memory device is delayed through various control circuits for reading data stored in the unit cell or writing externally input data to the unit cell, and connecting lines and connecting devices for transferring such input / output data. In addition, a delay occurs when data output from the semiconductor memory device is transferred to a device that requests data in the system. In systems operating at high speeds, delays in signal and data transfer not only reduce system performance, but also reduce the stability and reliability of operation. In particular, the delay occurring in the path through which the data is transferred is likely to change according to a given operating environment, which adversely affects the operation of the semiconductor memory device.

In general, the faster the semiconductor memory device outputs data of a unit cell (generally a read operation in a memory operation) after a command is input from an external device, the better the performance is, in particular, a large amount such as an image. In the case of a semiconductor memory device for graphic processing that processes data quickly, the time required to output the data is a very important performance indicator. To speed up the input and output of data, there should be no error in detecting and amplifying the data stored in the unit cell and transferring it to the outside through the data line. In addition, after outputting data, the semiconductor memory device must perform an essential operation such as restoring the original position and precharging the bit line for the next data access operation. As described above, although the semiconductor memory device is required to perform the above-described operation in a shorter time, it is becoming more complicated to control a plurality of internal operations performed according to an external command due to a system clock having a high frequency. If each internal operation is not performed within a predetermined time, the semiconductor memory device loses the reliability of the operation.

1 is a block diagram illustrating a general semiconductor memory device.

As illustrated, the semiconductor memory device may include a column control signal generator 110, a first delay unit 120, a write enable generator 130, a second delay unit 140, and a third delay unit 150. , And read enable generation unit 160.

When a write command is applied from the outside, the semiconductor memory device must activate a write enable signal BWEN and a column select signal YI for transferring data applied to a bit line connected to a unit cell. On the other hand, when a read command is applied from the outside, the semiconductor memory device must activate the column select signal YI and the read enable signal IOSTB for transferring data output from the unit cell to the outside. Here, the write enable signal BWEN is a signal for controlling a write driver for transferring data transmitted through the global input / output line GIO to the local input / output line LIO, and the column select signal YI is a local input / output signal. A signal for controlling the switching means for transferring the data transferred to the line (LIO) to the bit line sense amplifier (BLSA). In addition, the read enable signal IOSTB activates an I / O sense amplifier (IOSA) for sensing and amplifying data transmitted to the local input / output line (LIO) and delivering the data to the global input / output line (GIO). to be.

First, the column control signal generator 110 receives a column access command output from a command decoder (not shown) that outputs a result of decoding a command applied from the outside and outputs a column access enable signal YAE. The column access enable signal YAE is input to the first delay unit 120 and the second delay unit 140. The first delay unit 120 delays the column access enable signal YAE for a predetermined time in response to the command acknowledgment signal WT indicating whether the command applied from the outside is a read command or a write command, and then the write enable generation unit. Output to 130. In detail, when the command applied from the outside is a write command, the first delay unit 120 outputs a delay after a predetermined time delay of the column access enable signal YAE, but in the case of a read command, the first delay unit 120 is output. Is deactivated. The write enable generator 130 activates the write enable signal BWEN in response to the output of the first delay unit 120.

The second delay unit 140 receiving the column access enable signal YAE outputs the column select signal YI after a delay for a predetermined time. In addition, in response to the command acknowledgment signal WT, when the read command is applied from the outside, the second delay unit 140 transmits the column select signal YI to the third delay unit 150. Although output, the second delay unit 140 does not transmit a signal to the third delay unit 150 when a write command is applied from the outside. When a read command is applied from the outside, the third delay unit 150 delays the output of the second delay unit 140 for a predetermined time and outputs it to the read enable generation unit 160. The read enable generation unit 160 activates the read enable signal IOSTB in response to the output of the third delay unit 150.

As described above, the write enable signal BWEN, the column select signal YI, and the read enable signal IOSTB are changed by varying the delay amount of the column access enable signal YAE using a plurality of delay means. The control is to optimize the operation of the semiconductor memory device by being activated at different times according to read or write operations.

FIG. 2 is a waveform diagram illustrating an operation of the semiconductor memory device shown in FIG. 1. In particular, FIG. 2 illustrates an internal operation of the semiconductor memory device when a read command is applied.

The semiconductor memory device senses and amplifies data output from the unit cell corresponding to the read command, transfers the data to the local data lines LIO and LIOB in response to the column select signal YI, and then amplifies the data by the input / output sense amplifier IOSA. . To this end, first, the local line precharge signal LIOPCG for precharging the local data line LIO is deactivated to a logic low level. When the column select signal YI is activated to a logic high level during the column select period YIP, the sense-amplified data is transferred to the local data lines LIO and LIOB. The transferred data is amplified by the read enable signal IOSTB which is activated after the data transfer time tYIO after the column select signal YI is activated.

In this case, the data transfer time tYIO is transmitted to the local data lines LIO and LIOB through switching means operating in response to the column selection signal YI. The time it takes for the minimum input / output sense amplifier (IOSA) to sense and amplify. Therefore, the column selection section YIP in which the column selection signal YI is activated should be kept longer than the data transfer time tYIO. In addition, the sense amplification time tYIO_OVER for detecting and amplifying the data transferred to the local data lines LIO and LIOB must also be guaranteed. That is, the column selection interval (YIP) should be able to guarantee the minimum detection amplification time (tYIO_OVER) after the data transfer time (tYIO). When the input / output sense amplifier (IOSA) can sense and amplify data and transmit the data to the global input / output line (GIO), the column select signal YI is deactivated. Finally, when a predetermined time tYL passes after the column select signal YI is deactivated, the local line precharge signal LIOPCG is activated to a logic high level, and the local data lines LIO and LIOB are precharged. Here, whether to activate the local line precharge signal LIOPCG is determined by the column access enable signal YAE.

As described through the read operation, since the time point at which the column select signal YI and the read enable signal IOSTB should be activated is different from each other, as shown in FIG. 1, the third delay unit 150 is used. The activation time of each signal was controlled. In addition, it will be understood by those skilled in the art how the time at which the write enable signal BWEN and the column select signal YI are activated in the write operation will be fully understood, and thus a detailed description thereof will be omitted.

In the above-described read operation, the time point at which the column select signal YI and the read enable signal IOSTB are activated is very important to ensure high speed operation of the semiconductor memory device. For example, if the activation time of the read enable signal IOSTB lags behind, the pulse width of the column select signal YI should be wider. As a result, in order to adjust the activation time of the read enable signal IOSTB, the delay amount of the third delay unit 150 and the pulse width of the column access enable signal YAE generated by the column control signal generator 110 are adjusted. You have to control it. However, the third delay unit 150 may be formed through delay elements having predetermined delay amounts in two different circuits (that is, the column control signal generator 110 and the third delay unit 150) of the semiconductor memory device. It is very difficult to accurately adjust the delay amount and the pulse width of the column access enable signal (YAE).

3 is a waveform diagram illustrating a problem during operation of the semiconductor memory device illustrated in FIG. 1.

As illustrated, the semiconductor memory device responds to a read command when the activation period of the column select signal YI and the read enable signal IOSTB is overlapped to ensure the minimum detection amplification time tYIO_OVER. Data can be safely transferred outside. However, when the period in which the column selection signal YI and the read enable signal IOSTB are activated does not overlap, the detection amplification time tYIO_OVER cannot be guaranteed. That is, the reliability of data transmitted to the local data lines LIO and LIOB transmitted by the input / output sense amplifier IOSA activated by the read enable signal IOSTB to the global data line GIO is reduced.

In order to ensure the reliability of the operation, the semiconductor memory device should ensure that the read enable signal IOSTB is activated before the column select signal YI is deactivated during the read operation to ensure the minimum sense amplification time tYIO_OVER. However, in the semiconductor memory device shown in FIG. 1, there is no method of controlling the pulse width of the column select signal YI according to the activation time of the read enable signal IOSTB, and conversely, the pulse width of the column select signal YI. In response to this, there is no method of controlling the activation time of the read enable signal IOSTB. Therefore, a general semiconductor memory device may not be able to reliably guarantee the detection amplification time tYIO_OVER when the read timing is not executed correctly according to the designed minimum delay and the internal operation and the operation timing is changed due to the delay depending on the operating environment. . In addition, it is difficult to check the pulse width of the column selection signal YI and the activation time of the read enable signal IOSTB, which are controlled by separate circuits during the test process. As a result, the reliability of the operation of the semiconductor memory device is lowered. Since the time required for performing the internal operation in the semiconductor memory device having a high operating speed is not fixed and results in fluctuation, the operation margin for each internal operation must be sufficiently long to increase the operation reliability. This is a limitation in increasing the operation speed of the semiconductor memory device, making it difficult to operate the semiconductor memory device at high speed.

The present invention is to solve the above-mentioned problems and to control the data column access operation in the semiconductor memory device, to ensure a reliable column access operation in the event of environmental changes such as process, voltage level, temperature, or change in operating frequency. To control the deactivation time of the column selection signal, it is possible to normally transfer data from the local data line to the global data line.

According to the present invention, after the data applied to the local data line is sensed and amplified in response to a read command and started to be transmitted to the global data line, the internal device for disconnecting the local data line from the bit line sense amplifier, which senses and amplifies the data after a predetermined time has passed. A semiconductor memory device having a control circuit is provided.

The present invention also provides a first delay unit for generating a first control signal having a predetermined pulse width corresponding to a read command or a write command, and a first control signal transmitted only when a read command is applied for a second delay time. A second delay unit for delaying, a read enable generator for generating a read enable signal in response to an output of the second delay unit, a third delay unit for delaying the read enable signal by a third delay time, and writing A semiconductor memory device includes a column selection signal generation unit for generating a column selection signal in response to an output of a third delay unit in response to a first control signal when a command is applied.

Further, the present invention is to detect and amplify the data output from the unit cell in response to the read command, transferring the sense amplified data to the local data line, sense amplified data applied to the local data line to the global data line A method of operating a semiconductor memory device, the method comprising: transmitting the data, and blocking the sense amplified data transmitted to the local data line after a predetermined time after the data is started to be transmitted.

The semiconductor memory device controls a column access operation by a column select signal generated by decoding a command signal and an address signal applied from the outside in a semiconductor memory device having a high operation speed. In particular, the data amplified and sensed and output from the unit cell must be able to be transferred completely from the local data line to the global data line during the period in which the column selection signal is activated. It must be precharged. If the internal operation of the semiconductor memory device is not fully executed, a malfunction may occur and the reliability of the transmitted data may not be guaranteed. As a result, the operation reliability of the semiconductor memory device is also degraded. To this end, the present invention senses amplified by the bit line sense amplifier until the minimum time required for the input and output sense amplifier for transmitting the data applied to the local data line to the global data line to sense and amplify the data to the global data line Controls when the column select signal is inactive so that data can continue to be delivered to the local data line.

The present invention controls the deactivation time of the column selection signal during the operation of the semiconductor memory device to transfer data applied to the local data line to the global data line even in the event of environmental changes such as process, voltage level, temperature, or change in operating frequency. There is an advantage that can prevent the degradation of data reliability that can occur.

In addition, the present invention can control the pulse width of the column selection signal and the operation timing of the input / output sense amplifier even when the delay elements of the preset control circuit have different delay values after actual implementation, thereby providing an internal operation margin for the read command. As a result, internal defects of semiconductor memory devices such as data collision can be reduced even at high speed.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

As illustrated, the semiconductor memory device senses and amplifies data after a predetermined time after the data applied to a local data line is sensed and amplified and started to be transferred to a global data line in response to a read command and the local data. Internal control circuitry for disconnecting lines. In addition, the internal control circuit controls the flow of the data so that externally applied data may be stored in the unit cell through the local data line in response to a write command.

A semiconductor memory device according to an embodiment of the present invention has various components for transferring data corresponding to a read command and a write command between a unit cell and a data pad. Looking at the inside of the semiconductor memory device, data is transferred between the unit cell and the data pad through the local data line (LIO) and the global data line (GIO). In addition, the semiconductor memory device senses and amplifies data applied to the local data line LIO in response to the read enable signal IOSTB, and transmits the input / output sense amplifier and column selection signal YI to the global data line GIO. And switching means for connecting the local data line (LIO) and the bit line sense amplifier in correspondence thereto. In addition, the semiconductor memory device may include a write driver for transferring data applied through the global data line GIO to the local data line LIO in response to the write enable signal BWEN. The above-described internal control circuit controls the transfer of data through the local data line and the global data line in response to a read command or a write command, thereby controlling the operations of the input / output sense amplifier, the switching means, and the write driver. Allows data to be passed completely within

Referring to FIG. 4, the internal control circuit may enable the column access signal generation unit 410 for generating the column access enable signal YAE in response to a read command or a write command, and only when a write command is applied. A first delay unit 420 for delaying the signal YAE by a first delay time, a write enable generator BWEN for generating a write enable signal in response to an output to the first delay unit 420, The second delay unit 440 for outputting the first control signal Ylore by delaying the column access enable signal YEA by a second delay time, and the first control signal Ylore which is transmitted only when a read command is applied. ), The third delay unit 450 for delaying the third delay time by the third delay time, the read enable generator 460 for generating the read enable signal IOSTB in response to the output of the third delay unit 450, Delay the read enable signal IOSTB by a fourth delay time. The fourth delay unit 470 to correspond to the first control signal Ylore when a write command is applied, and the output IOSTBD of the fourth delay unit 470 when a read command is applied. And a column select signal generator 480 for generating a column select signal YI. Here, the column control signal generator 410 is disposed in the peripheral circuit region PERI, and the other illustrated components are disposed in the column control region COL_CONTROL.

In the present invention, unlike the prior art, the pulse width of the column access enable signal YAE is not used as the pulse width of the column select signal YI, so that the pulse width of the column access enable signal YAE can be determined in response to the activation time of the read enable signal IOSTB. do. That is, the activation time of the column select signal YI is the same as the conventional time when a certain time has passed since the activation time of the column access enable signal YAE, but the deactivation time of the column select signal YI is the read enable signal. It's been a while since (IOSTB) was activated. In detail, a time point at which the column select signal YI is inactivated is a time point after the fourth delay time tYIO_OVER after the read enable signal IOSTB is activated, and is determined by the fourth delay unit 470. 4 Delay time (tYIO_OVER) is the minimum time required for the input and output sense amplifiers to sense and amplify the data applied to the local data line and deliver it to the global data line. If the deactivation time of the column select signal YI is sufficient to maintain the fourth delay time, there is no problem in the operation of the semiconductor memory device. Therefore, in the present invention, the column access enable signal is used to increase the reliability of data transfer during the read operation. The pulse width of (YAE) no longer needs to be extended depending on the operating environment.

For reference, the third delay time tYIO determined by the third delay unit 450 may be such that the potential difference between the pair of local data lines is sensed and amplified by the minimum input / output sense amplifier due to the data transferred through the switching means. It's time to be ideal.

Since the internal operation for generating the write enable generation unit BWEN and the read enable signal IOSTB in the present invention is similar to that of the related art, a detailed description thereof will be omitted. Hereinafter, the first operation corresponding to the read command or the write command will be omitted. The column select signal generator 480 for generating the column select signal YI in response to the control signal Ylore or the output IOSTBD of the fourth delay unit 470 will be described.

FIG. 5 is a circuit diagram illustrating the column select signal generator 480 of FIG. 4. The column select signal YI is activated in response to both the read command and the write command. The column select signal generator 480 determines whether a read command or an external write command is applied through the command status signal WT. Figure out.

As shown, the column select signal generator 480 generates the column select signal YI, and the activation time is the column access enable generated by the column control signal generator 410 in the peripheral region PERI. The deactivation time is determined using the signal YAE, and the deactivation time is determined using the output IOSTB of the fourth delay unit 470 which delays the read enable signal IOSTB. As a result, the present invention needs to further check or test whether the activation section of the column select signal YI and the activation section of the read enable signal IOSTB overlap in order to confirm the reliability of data transmission. In order to adjust the interval in which the activation intervals of the two signals overlap, it can be easily controlled by simply adjusting the delay amount of the fourth delay unit 470. In addition, the present invention enables efficient control by distinguishing between an internal operation for a read command and an internal operation for a write command so that the column select signal YI can be generated.

Referring to FIG. 5, the column select signal generator 480 is activated when the first control signal Ylore is activated and deactivated when the output IOSTBD of the fourth delay unit 470 is activated. In response to the output of the pulse generator 482 for outputting the pulse generator 482 and the read command, if the write command is applied, the column is selected in response to the first control signal Ylore. And a logic unit 484 for activating the signal YI. Here, the first internal signal NA remains active until the output IOSTBD of the fourth delay unit 470 is activated even when the first control signal Ylore is inactivated. When the output (IOSTBD) is active, it goes inactive.

In detail, the pulse generator 482 receives the first control signal Ylore and the output IOSTBD of the fourth delay unit 470 through one input terminal, and crosses each of the outputs to the input terminal. It includes two NOR gates that are cross-coupled. In addition, the logic unit 484 may apply a negative logic NAND for outputting the column select signal YI in response to the first internal signal NA when a read command is applied and the command status signal WT is at a logic low level. Gate and an inverter and a NAND gate for outputting the column select signal YI in response to the first control signal Ylore when the command state signal WT is at a logic high level. It includes.

FIG. 6 is a waveform diagram illustrating the operation of the semiconductor memory device shown in FIG. 4.

As shown in the drawing, in the semiconductor memory device according to the present invention, the read enable signal output from the read enable generator 460 is the activation period of the first control signal Ylore output from the second delay unit 440. Regardless of whether the IOSTB is overlapped with the activation section, the activation section of the column select signal YI always overlaps with the activation section of the read enable signal IOSTB. That is, by deactivating the column select signal YI after a predetermined time after the read enable signal IOSTB is activated, the pulse width of the column select signal YI is changed according to the change of the operating environment in the semiconductor memory device. This can increase operational reliability for data transfer. Compared with the prior art illustrated in FIG. 3, the activation section of the column select signal YI can always overlap with the activation section of the read enable signal IOSTB, so that even when operating at a high speed, the activation section It can be seen that reliability is ensured in the data transfer process.

In addition, as shown in FIG. 4, the column select signal generator 480 based on the column access enable signal YAE in different ways in a read command or a write command corresponding to the command status signal WT. Since the select signal YI is generated, it is possible to perform efficient internal operations for the read command and the write command. Furthermore, the semiconductor memory device according to the present invention can easily adjust the pulse width of the column select signal YI by adjusting the delay amount of the fourth delay unit 470 when performing an internal operation corresponding to a read command. The degree of overlap between the activation periods of the column select signal YI and the read enable signal IOSTB can be easily controlled.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a block diagram illustrating a general semiconductor memory device.

FIG. 2 is a waveform diagram illustrating an operation of the semiconductor memory device shown in FIG. 1.

3 is a waveform diagram illustrating a problem during operation of the semiconductor memory device illustrated in FIG. 1.

4 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating the column select signal generator illustrated in FIG. 4.

FIG. 6 is a waveform diagram illustrating the operation of the semiconductor memory device shown in FIG. 4.

Claims (22)

delete Internal control for disconnecting the local data line from the bit line sense amplifier that senses and amplifies the data after a predetermined time after data applied to the local data line is sensed and amplified in response to a read command and started to be transferred to the global data line. With a circuit, And the internal control circuit controls the flow of data such that externally applied data can be stored in a unit cell through the local data line in response to a write command. The method of claim 2, An input / output sense amplifier configured to sense and amplify data applied to the local data line in response to a read enable signal and transmit the detected data to the global data line; And And switching means for connecting the local data line and the bit line sense amplifier in response to a column select signal. The method of claim 3, wherein The internal control circuit A column control signal generator for generating a column access enable signal in response to the read command or the write command; A first delay unit configured to delay the column access enable signal by a first delay time and output a first control signal; A second delay unit for delaying the first control signal transmitted only when the read command is applied by a second delay time; A read enable generator for generating the read enable signal in response to an output of the second delay unit; A third delay unit for delaying the read enable signal by a third delay time; And A semiconductor including a column select signal generation unit for generating the column select signal in response to the output of the third delay unit in response to the first control signal when the write command is applied; Memory device. The method of claim 4, wherein The column select signal generator A pulse generator for outputting a first internal signal that is activated when the first control signal is activated and deactivated when the output of the third delay unit is activated; And And a logic unit configured to activate the column select signal in response to the output of the pulse generator when the read command is applied and in response to the first control signal when the write command is applied. The method of claim 5, The first internal signal is activated even when the first control signal is inactivated until the output of the third delay unit is activated. The method of claim 6, Wherein the second delay time is a time required for the potential difference between the pair of local data lines to be at least as large as the input / output sense amplifier can sense and amplify due to the data transferred through the switching means. Device. The method of claim 7, wherein And wherein the third delay time is a minimum time required for the input / output sense amplifier to sense and amplify data and deliver the data to the global data line. The method of claim 4, wherein And a write driver for transferring data applied through the global data line to the local data line in response to a write enable signal. The method of claim 9, The internal control circuit A fourth delay unit configured to delay the column access enable signal by a fourth delay time only when the write command is applied; And And a write enable generation unit for generating a write enable signal in response to an output in the fourth delay unit. A first delay unit for generating a first control signal having a predetermined pulse width in response to a read command or a write command; A second delay unit for delaying the first control signal transmitted only when the read command is applied by a second delay time; A read enable generator for generating a read enable signal in response to an output of the second delay unit; A third delay unit for delaying the read enable signal by a third delay time; And The semiconductor memory includes a column select signal generation unit configured to generate a column select signal in response to the output of the third delay unit in response to the first control signal when the write command is applied. Device. The method of claim 11, And said column select signal controls switching means for connecting a local data line and a bit line sense amplifier. The method of claim 12, The column select signal generator A pulse generator for outputting a first internal signal that is activated when the first control signal is activated and deactivated when the output of the third delay unit is activated; And And a logic unit configured to activate the column select signal in response to the output of the pulse generator when the read command is applied and in response to the first control signal when the write command is applied. The method of claim 13, The first internal signal is activated even when the first control signal is inactivated until the output of the third delay unit is activated. The method of claim 14, And the second delay time is a time required for the potential difference between the pair of local data lines to be greater than or equal to that of the input / output sense amplifier due to the data transmitted through the switching means. The method of claim 15, And the third delay time is a minimum time required for the input / output sense amplifier to sense and amplify data and deliver the data to a global data line. The method of claim 12, And a column control signal generator for outputting a column access enable signal to the first delay unit in response to the read command or the write command. The method of claim 17, A fourth delay unit configured to delay the column access enable signal by a fourth delay time only when the write command is applied; And And a write enable generator configured to generate a write enable signal in response to an output of the fourth delay unit. The method of claim 18, And the write enable signal controls a write driver for transferring data applied through a global data line to a local data line. delete delete Sensing and amplifying data output from the unit cell in response to the read command; Passing the sense amplified data to a local data line; Sensing and amplifying data applied to the local data line and transferring the data to a global data line; Sensing and amplifying the data applied to the local data line and transferring the data to the global data line; Maintaining data transfer to the local data line for a minimum amount of time necessary to sense, amplify and transfer the data to the global data line; And Blocking the data transferred to the local data line.

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