JP2000243098A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which erroneous entry can be easily recognized by a user when a test mode is erroneously entered. SOLUTION: A test mode discriminating circuit 31 inputs an external command consisting of a chip-select signal/CS, a row address strobe signal/RAS, a column address strobe signal/CAS, a write-enable signal/WE, and the like, while inputs memory address signals A0-An. And an external command of the discriminating circuit 31 is a mode register set command, the circuit 31 discriminates whether an illegal pattern of a normal operation test mode of external memory address signals A0-An is inputted or not, and outputs a discrimination signal SGX. A test mode control circuit 32 switches signal lines L0, L1 based on the discrimination signal SGX, and inputs memory address signals A0, A1 to an address buffer/register and a bank selecting circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device which shifts to a test mode when a test command is input.

[0002]

2. Description of the Related Art Generally, semiconductor devices are subjected to various tests before they are shipped, and those that pass the tests are shipped as products. For example, in a test before shipment of a semiconductor memory device, a voltage higher than a normal value (a so-called spur high voltage) is applied to a certain input pin, the semiconductor memory device is set to a test mode, and various commands and data are transmitted. Various tests are executed as input to the device.

[0003]

By the way, the method of applying the super high voltage to the test mode requires a special circuit for detecting the super high voltage, and the special circuit is used only for the test. Since it is used, it is a problem in achieving high-density integration and reduction in circuit scale. Therefore, a method of setting a test mode using a special address not used by the user instead of the spur high voltage has been considered. For example, a command (a so-called illegal command) for which the use is prohibited is presented to the user in advance as an entry command to the test mode, and the test mode is set using the illegal command.

An SDRAM (Synchronous Dynamic Random)
Access Memory) and FCRAM (Fast Cycle Dynamic R)
andom Access Memory) fetches a chip select signal, a row address strobe signal, a column address strobe signal and a write enable signal supplied from an external device in synchronization with an external clock signal, and uses a combination of the fetched signals at that time. High-speed operation is achieved by deciding and operating a command. As a method of setting the test mode in the SDRAM or the like, a combination (external command) of each signal such as a chip select signal is set by a mode register set command (MRS).
And the memory address signals A0 to
Various test modes are set according to the combination of An.

More specifically, a mode register is provided in an SDRAM or the like, and the mode register uses a combination of a mode register set command and memory address signals A0 to An to perform various tests such as a counter test and a high load test of a cell plate. The mode is set.

The combination of the memory address signals A0 to An for determining various test modes includes a burst length,
Memory address signals A0-A used for setting the operation mode of the mode register set command such as CAS latency
Decided to avoid An combinations. That is, the memory address signals A0 to An for determining various test modes
A combination (illegal pattern) for which use by the user is prohibited is used as the combination. For example, when both the memory address signal A7 and the memory address signal A8 are at the H level (positive logic signal), the test mode is set, and the type of test is determined by the address signals other than the memory address signals A7 and A8.

However, in a system equipped with the SDRAM or the like, there is a possibility that an illegal command is accidentally generated. For example, when the power is turned on, the state of the input terminals of the SDRAM and the like on the system is in an indeterminate state. There is. That is, in an SDRAM or the like, there is a possibility that a mode register set command and an illegal pattern for determining various test modes are accidentally generated and the mode register is set to the test mode.

When an illegal command is accidentally generated and the test mode is set in the test mode as described above, if the test mode is a test mode in which external memory address signals A0 to An are not accepted, the user is prompted. The user can immediately notice the abnormality and stop the actual use. For example, in a test mode in which an internal circuit operates and a test is performed, such as an address counter test, a read date or the like is output even though the memory address signals A0 to An are not input. The actual use can be stopped by noticing the abnormality. The test mode is released by resetting the mode register.

On the other hand, in the test, a problem occurs in a test mode which is not different from the normal operation mode from the viewpoint of the user. For example, in a high load test of a cell plate, the only difference is that the internal voltage is changed to a high voltage, and the address input, access, and input / output of cell data from the outside are performed in exactly the same state as in normal use. Operate. In other words, the high load test of the cell plate is a burn-in test, and the operation (write operation, read operation, etc.) that is normally used in a state where the counter electrode of the memory cell is set to a high voltage.
Is executed.

Therefore, if the test mode of the high load test is accidentally entered, the user operates normally in spite of the SDRAM operating in the burn-in state. There is a possibility that it will enter into actual use without being noticed. The fact that the memory cell is actually used as it is means that the memory cell is continuously used in a state where a high voltage is applied between the opposite electrodes, and the SDRA is used.
The life of M is significantly shortened.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the first invention is to provide a semiconductor device which can be easily recognized by a user when a test mode is incorrectly entered. is there.

A second object of the present invention is to provide a semiconductor device which can be released even if a test mode is erroneously entered. A third object of the present invention is to provide a semiconductor device in which a test mode is hardly entered.

[0013]

According to the first aspect of the present invention, when a test mode is detected by the determination circuit, the control circuit determines the value or the value of one operation executing the test mode. Change the access time from normal operation.

According to the second aspect of the present invention, when the determination circuit detects that the operation mode including the address input, the access to the memory cell from the decoder, and the input / output of data has entered the test mode which can be executed. , The control circuit changes the value or the access time of at least one of the operation modes from the normal operation.

According to the third aspect of the present invention, the determination circuit detects that the operation mode including the address input, the access to the memory cell from the decoder, and the data input / output has entered the test mode which can be executed. With
Upon detecting a command signal related to at least one operation in the operation mode, the control circuit changes a value or an access time of at least one operation in the operation mode from a normal operation.

According to the present invention, when the determination circuit detects that the test mode has been entered, the control circuit changes the memory address signal to another memory address signal.

According to the present invention, when the determination circuit detects that the test mode has been entered, the control circuit changes the input data to another input data or the output data to another output data.

According to the present invention, when the determination circuit detects that the test mode has been entered, the control circuit changes the command signal to another command signal.
According to the invention, when the determination circuit detects that the test mode has been entered, the control circuit determines the number of clocks until the first output data is read or the number of clocks until the first input data is fetched. To change.

According to the present invention, when the determination circuit detects that the test mode has been entered, the control circuit sets the length of the continuously output data or the continuously input data. Change the length of.

According to the ninth aspect, when the determination circuit detects that the test mode has been entered, the control circuit supplies the signal supplied to the signal line to another signal line. According to the tenth aspect, when the determination circuit detects that the test mode has been entered, the control circuit inverts the signal supplied to the signal line.

According to the eleventh aspect, the timer circuit enters the test mode in which the determination circuit can execute an operation mode including address input, access to a memory cell from a decoder, and data input / output. , The timer circuit measures the time for terminating the test mode and shifting to the normal operation mode.

According to the twelfth aspect of the present invention, the determination circuit detects that the operation mode including the address input, the access to the memory cell from the decoder, and the data input / output has entered the test mode which can be executed. At the same time, when detecting a command signal relating to at least one operation in the operation mode, the timer circuit measures time for terminating the test mode and shifting to the normal operation mode.

According to the thirteenth aspect, when the determination circuit detects that the test mode has been entered, the timer circuit measures the time for shifting to the normal operation mode according to the type of the test mode.

According to the fourteenth aspect of the present invention, when the determination circuit detects that the test mode has been entered, the self-refresh counter counts time for terminating the test mode and shifting to the normal operation mode.

According to the fifteenth aspect of the present invention, when the test mode is detected by the determination circuit, the control circuit sets the value or access time of one operation executing the test mode to the normal operation. Change from. Then, the control circuit returns the changed state to a normal operation based on the time-up signal of the timer circuit.

According to the sixteenth aspect of the present invention, the determination circuit includes a plurality of test modes for a plurality of test modes capable of executing an operation mode including address input, access to a memory cell from a decoder, and data input / output. The predetermined illegal patterns are individually determined. When the determination circuit detects all of the plurality of predetermined illegal patterns, the determination circuit enters a test mode in which the operation mode can be executed.

According to the seventeenth and eighteenth aspects, when the determination circuit enters the test mode in which the operation mode can be executed, the timer circuit terminates the test mode and shifts to the normal operation mode. Clock the time.

According to the nineteenth aspect of the present invention, when the determination circuit enters a test mode in which the operation mode can be executed, the control circuit determines the value or access value for one operation executing the test mode. Change the time from normal operation.

According to the twentieth aspect of the present invention, when the determination circuit enters a test mode in which the operation mode can be executed, the control circuit determines the value or access value of one operation executing the test mode. Change the time from normal operation. Then, the control circuit returns the changed state to a normal operation based on the time-up signal of the timer circuit.

According to the present invention, when the determination circuit detects the test mode entry, the timer circuit measures the time for terminating the test mode and shifting to the normal operation mode.

According to the invention described in claim 22, the determination circuit individually determines a plurality of predetermined illegal patterns for a plurality of test modes. When the determination circuit detects all of the plurality of predetermined illegal patterns, the determination circuit enters a test mode in which the operation mode can be executed.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS. 1 to 4 show a first embodiment of the present invention embodied in a semiconductor memory device.
It will be described according to.

FIG. 4 shows an SDR having a test mode function.
It is a block diagram of AM (Synchronous Dynamic Random Access Memory). In FIG. 4, SDRAM 1 includes a clock buffer 10, a command decoder 11, an address buffer / register & bank select circuit 12, an I / O
Data buffer / register 13, control signal latch circuit 1
4, mode register 15, column address counter 1
6, a bank 0 circuit 17 and a bank 1 circuit 18.

In the bank 0 circuit 17 and the bank 1 circuit 18, the memory cells 2 arranged in a matrix are arranged.
1, a memory cell block including a row decoder 22, a sense amplifier 23, and a column decoder 24 (only the memory cell blocks 25a, 25b, 25c, and 25d are shown in FIG. 4), and a write amplifier / sense buffer 26. That is, in the SDRAM 1, a cell matrix (core circuit) in which memory cells are arranged in a matrix is divided into a plurality of bank units (in FIG. 4, the bank 0 circuit 17 and the bank 1 circuit 18). The cell matrix divided for each bank forms each block (memory cell blocks 25a, 25b, 25c, 25d in FIG. 4) in which a plurality of memory cells 21 are arranged in the row and column directions. Each block has a sense amplifier 23 for each column.

The clock buffer 10 receives a clock signal CLK and a clock enable signal CKE from an external device. The clock buffer 10 supplies a synchronous clock signal CLK1 to each circuit unit constituting the SDRAM 1 based on the clock signal CLK. The clock buffer 10 outputs a clock enable signal CKE to a command decoder 11, an address buffer / register & bank select circuit 12, an I / O
The data is supplied to the data buffer / register 13.

The command decoder 11 receives a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE from an external device. Is supplied.
Note that “/” in each signal / CS, / RAS, / CAS, / WE indicates a signal of negative logic, and the other indicates a signal of positive logic. The command decoder 11 determines the content of the external command according to the combination of the supplied signals,
Various contents of the external command are supplied to the control signal latch circuit 14 and the mode register 15 as internal commands. Then, the control signal latch circuit 14 latches the supplied internal command and supplies it to the bank 0 circuit 17 and the bank 1 circuit 18.

The address buffer / register & bank select circuit 12 receives an external memory address signal from an external device.
A0 to An are supplied, and the external memory address signals A0 to An
As the internal memory address signals A0 to An (for convenience of explanation, the symbols are made the same as those of the external memory address signals), the mode register 15, the column address counter 16, and the bank 0.
Circuit 17 and the bank 1 circuit 18. In the present embodiment, the address signal An of the most significant bit of the external memory address signals A0 to An is used for bank selection,
Either the circuit 17 for bank 0 or the circuit 18 for bank 1 is selected. Note that “n” of the address signal An is a variable and is an integer corresponding to the memory capacity.

The I / O data buffer / register 13
Data signals DQ0 to DQn and a data input / output mask signal DQM are supplied from an external device. The I / O data buffer / register 13 converts the data signals DQ0 to DQn into input data signals.
DQ0 to DQn as the circuit 17 for bank 0 and the circuit 1 for bank 1
8 Also, I / O data buffer / register 1
3, data signals DQ0 to DQn are supplied from the bank 0 circuit 17 and the bank 1 circuit 18. The I / O data buffer / register 13 supplies the data signals DQ0 to DQn to external devices as output data signals DQ0 to DQn. Further, the data input / output mask signal DQM masks the input / output data signals DQ0 to DQn as necessary.

The mode register 15 stores data in data writing and data reading in the state (combination) of the internal memory address signals A0 to An output when the internal command from the command decoder 11 is a mode register set command (MRS). It has a register for setting the burst length of the signal, and generates burst length information based on the burst length set from an external device. The combination of the external (internal) memory address signals A0 to An when setting the burst length is a combination (pattern) that is permitted to be used by the user in advance, and is prohibited from being used by the user. Not an illegal pattern.

The mode register 15 has a register for setting test modes for various tests. When the internal command is the mode register set command and the internal memory address signal A0
When .about.An is a plurality of types of illegal patterns determined in advance, the corresponding registers are set. The plurality of types of illegal patterns determined in advance are patterns that are prohibited from being used by the user in order to set various test modes.

Then, in the mode register 15,
The test mode is determined based on two of the memory address signal A7 and the memory address signal A8, and the memory address signal A
The test type is specified based on memory address signals other than 7, A8. In this embodiment, the test mode is entered when both the memory address signal A7 and the memory address signal A8 are at the H level.

Therefore, when the internal command is a mode register set command and the internal memory address signals A0 to An are a plurality of predetermined illegal patterns for testing, the mode register 15 sets the test mode to the register. Set. And the mode register 1
Reference numeral 5 outputs a test mode signal corresponding to the set test to necessary circuit units. As a result, various tests are executed.

The column address counter 16 is supplied with internal memory address signals A0 to An from the address buffer / register & bank select circuit 12, and supplies the address signal to each bank.

Next, the bank 0 circuit 17 will be described. The description of the configuration and function of the bank 1 circuit 18 having the same configuration and function as the bank 0 circuit 17 will be omitted.

The circuit 0 for the bank 0 stores each of the memory cells 2 in the memory cell blocks 25a, 25b, 25c, 25d.
1 is read out by the sense amplifier 23.
For example, in the memory cell block 25a, the row decoder 22 generates a word line selection signal for selecting a word line corresponding to the internal memory address signals A0 to An.
The sense amplifier 22 individually receives and holds data of all the memory cells 21 coupled to the word line selected by the word line selection signal via the bit line. The column decoder 24 generates a column line selection signal for simultaneously selecting a plurality of bits of the data held in the plurality of sense amplifiers 23.

At the time of data reading, the write amplifier / sense buffer 26 receives parallel data read from the selected memory cell block, and outputs the parallel data to the I / O data buffer / register 13 via a data bus. The signals are supplied as signals DQ0 to DQn. At the time of data writing, the write amplifier / sense buffer 26 receives the input data signals DQ0 to DQn, which are parallel data from the I / O data buffer / register 13, and buffers them into signals that can be processed by each memory cell block. Output on the global data bus.

The SDRAM 1 has a test mode detection circuit section 30. Next, the test mode detection circuit 3
0 will be described accordingly. Test mode detection circuit 3
0 has a test mode determination circuit 31 and a test mode control circuit 32.

In FIG. 1, test mode determination circuit 31
Are connected to a chip select signal input pin P1, a row address strobe signal input pin P2, a column address strobe signal input pin P3, and a write enable signal input pin P4. Like the command decoder 11, the test mode determination circuit 31 receives a chip select signal / CS, a row address strobe signal / RAS,
A column address strobe signal / CAS and a write enable signal / WE (that is, an external command) are supplied.

The test mode determination circuit 31 is connected to the address signal input pins PA0 to PAn, and receives memory address signals A0 to An from an external device.
More specifically, as shown in FIG. 2, the test mode determination circuit 31 includes a first determination circuit unit 31a and a second determination circuit unit 31b.
And a third determination circuit section 31c.

First and second determination circuit sections 31a, 31b
Is supplied with a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS and a write enable signal / WE from an external device, that is, an external command. Then, the first determination circuit unit 3
1a outputs an H-level first determination signal SGX1 to the third determination circuit section 31c when the external command is a mode register set command. On the other hand, the second determination circuit unit 31b
Outputs an H-level second determination signal SGX2 to the third determination circuit unit 31c when the external command is a read command.

The third determination circuit 31c is supplied with external memory address signals A0 to An from an external device. The third determination circuit unit 31c captures the external memory address signals A0 to An in response to the first determination signal SGX1 at the H level. Then, the third determination circuit unit 31c outputs the external memory address signal
Based on A0-An, it is determined whether the combination of each signal A0-An is a test mode (illegal pattern) and a test mode in which normal operation can be performed (illegal pattern of test mode in which normal operation can be performed). I do.

In the present embodiment, the third determination circuit section 31c
Determines the test mode based on the memory address signal A7 and the memory address signal A8.
The type of test is determined by the address signals except A8. More specifically, the test mode determination circuit 31
Address signals other than memory address signals A7 and A8
It is determined whether or not a test mode in which a normal operation is performed (executable). Then, the test mode determination circuit 3
1 generates and holds an H-level determination signal SGX when the illegal pattern is an illegal pattern in a test mode in which a normal operation can be performed.

Therefore, when the H-level first determination signal SGX1 is not output, or when the H-level first determination signal SGX1 is
Is output, and when a pattern other than the illegal pattern in the test mode in which the normal operation can be executed is input, the test mode determination circuit 31 does not generate the H-level determination signal SGX.

That is, the test mode determination circuit 31 determines that the signals (external commands) from the input pins P1 to P4 are mode register set commands and the signals from the input pins PA0 to PAn (external memory address signals A0 to An). Is determined to be an illegal pattern in a test mode in which a normal operation can be performed (executable), an H-level determination signal SGX indicating that a test mode in which a normal operation can be performed is entered in the third determination circuit unit 31c. Are generated and retained.

For example, when the combination of the address signals A0 to An is an address counter test, the address counter test is a test mode in which a normal operation is not performed, so that the H-level determination signal SGX is not latched.

On the other hand, the only difference is that the internal voltage is changed to a high voltage as in the high load test of the cell plate.
In a test mode (normal operation test mode) in which operations such as address input, access, and input / output of cell data from the outside are performed in exactly the same state as normal use, which is not different from the normal operation mode to the user. , An H-level determination signal SGX is latched.

Further, in a state where the H-level determination signal SGX indicating that the normal operation test mode has been entered is latched, the third determination circuit section 31c is thereafter fetched in synchronization with the clock signal CLK (synchronous clock signal CLK1). It waits whether the external command from the external device is a signal of a combination of read commands. That is, the third determination circuit unit 31c receives the H-level second determination signal SGX2 from the second determination circuit unit 31b.
Wait for.

Then, when the external command from the external device is a read command (H
When the second level determination signal SGX2 is input), the latched high-level determination signal SGX is output to the test mode control circuit 32. When the H-level determination signal SGX is not latched, even if the external command from the external device is a read command, the third determination circuit 31c
Does not latch the judgment signal SGX at the H level,
The H-level determination signal SGX is not output to the test mode control circuit 32.

That is, the test mode determination circuit 31
When the external command of the read command is input while the level determination signal SGX is latched, an H level determination signal SGX is output. Therefore, for example, if the external command is a mode register set command and the address signal A0
If the combination of .about.An is a test mode (normal operation test mode) for executing a high load test of the cell plate, the H-level determination signal SGX is latched. And
When an external read command is input, an H-level determination signal SGX is output to the test mode control circuit 32.

The test mode control circuit 32 connects any two of the signal lines L0 to Ln for inputting the memory address signals A0 to An to signal lines (in this embodiment, the signal lines L0 and L1 for the memory address signals A0 and A1). To change the memory address signals A0 to An
Is input to the address buffer / register & bank select circuit 12. In this embodiment,
The signal lines L2 to Ln cannot be switched, and the memory address signal A2
To An are input to the address buffer / register & bank select circuit 12 as they are. FIG. 3 is a circuit diagram of the test mode control circuit 32.

In FIG. 3, test mode control circuit 32
Has four first to fourth transfer gates 41 to 44 and an inverter circuit 45. The first transfer gate 41 connects the signal line L0 for inputting the memory address signal A0, which is wired between the input pin PA0 and the address buffer / register & bank select circuit 12, to a pin-side signal line.
It is provided so as to be divided into L0a and circuit-side signal line L0b. The first transfer gate 41 includes a PMOS transistor Q1 and an NMOS transistor Q2. The determination signal SGX from the test mode determination circuit 31 is input to the gate of the PMOS transistor Q1, and the determination signal SGX is input to the gate of the NMOS transistor Q2 via the inverter circuit 45. .

The second transfer gate 42 connects the signal line L1 for inputting the memory address signal A1 wired between the input pin PA1 and the address buffer / register & bank select circuit 12 to the pin-side signal line L1a and the circuit-side signal. It is provided so as to be divided into the line L1b. The second transfer gate 42 includes a PMOS transistor Q3 and an NMOS transistor Q4. The determination signal SGX is input to the gate of the PMOS transistor Q3,
An inverter circuit 4 is provided at the gate of the NMOS transistor Q4.
5, the judgment signal SGX is inputted.

The third transfer gate 43 is provided between the pin-side signal line L1a and the circuit-side signal line L0b. The third transfer gate 43 includes a PMOS transistor Q5 and an NMOS transistor Q6. The determination signal SGX is input to the gate of the PMOS transistor Q5 via the inverter circuit 45,
The determination signal SGX is input to the gate of the MOS transistor Q6.

The fourth transfer gate 44 is provided between the pin-side signal line L0a and the circuit-side signal line L1b. The fourth transfer gate 44 includes a PMOS transistor Q7 and an NMOS transistor Q8. The determination signal SGX is input to the gate of the PMOS transistor Q7 via the inverter circuit 45,
The determination signal SGX is input to the gate of the MOS transistor Q8.

Therefore, the test mode determination circuit 31
When the level judgment signal SGX is not output, the first
The second and fourth transfer gates 41 and 42 are turned on, and the third and fourth transfer gates 43 and 44 are turned off. As a result, the memory address signal A0 input from the input pin PA0 is input to the address buffer / register & bank select circuit 12 via the signal line L0 (pin side signal line L0a and circuit side signal line L0b). The memory address signal A1 input from the input pin PA1 is input to the address buffer / register & bank select circuit 12 via the signal line L1 (pin side signal line L1a and circuit side signal line L1b).

On the other hand, when the test mode judgment circuit 31 outputs the judgment signal SGX at the H level, the first and second transfer gates 41 and 42 are turned off, and the third and fourth transfer gates 43 and 44 are turned on. I do. As a result, the memory address signal A0 input from the input pin PA0 is transmitted via the pin-side signal line L0a of the signal line L0 and the circuit-side signal line L1b of the signal line L1 to the address buffer / register &
It is input to the bank select circuit 12. Also, input pin PA
The memory address signal A1 inputted from the address buffer / register & bank select circuit 1 via the pin side signal line L1a of the signal line L1 and the circuit side signal line L0b of the signal line L0.
2 is input. That is, the memory address signal A0 input from the input pin PA0 and the memory address signal A1 input from the input pin PA1 are switched and the address buffer /
It is input to the register & bank select circuit 12.

Next, the operation of the test mode detection circuit section 30 configured as described above will be described. Now, when the system power supply is turned on, if a mode register set command is accidentally generated on the input pins P1 to P4 and an illegal pattern for the test mode is generated on the input pins PA0 to PAn, the SDRAM 1 sets the mode register 15 To enter the test mode. As a result, the SDRAM 1 executes a test based on the contents of the illegal pattern for the test mode.

At this time, if the set test mode is one of the normal operation test modes, for example, a test mode of a high load test of a cell plate, the SDRAM 1 sets the voltage between the common electrodes of the memory cell 21 to a normal voltage. Wait for a new external command and memory address signals A0 to An in order to perform a normal operation by applying a voltage higher than the voltage. On the other hand, the test mode determination circuit 31 latches the determination signal SGX at the H level and waits for a read command.

In the high load test of the cell plate, since the data reading of the memory cell 21 is performed, the external command of the read command from the external device and the memory address signals A0 to An designating the memory cell 21 to be read are transmitted to the SDRAM.
1 is input.

When an external read command is input, the test mode determination circuit 31 outputs the latched H-level determination signal SGX to the test mode control circuit 32. The test mode control circuit 32 turns off the first and second transfer gates 41, 42 and turns on the third and fourth transfer gates 43, 44. And
The test mode control circuit 32 switches between the memory address signal A0 input from the input pin PA0 and the memory address signal A1 input from the input pin PA1 and inputs the same to the address buffer / register & bank select circuit 12.

Therefore, in this read operation, a memory address signal different from the memory address signal of the address of the memory cell 21 specified by the external device is input to the address buffer / register & bank select circuit 12. As a result, the memory cell 21 at the address based on the different memory address signal is specified and its contents are read. That is, the contents of the memory cell 21 different from the memory cell 21 specified by the external device are read. Therefore, the user easily recognizes that the content of the memory cell 21 different from the specified memory cell 21 is read and differs from the expected content, and operates in an abnormal state for some reason (high cell plate height). Operating in the test mode of the load test).

Then, once the user turns off the system power supply and starts up or restarts again, the test mode of the mode register 15 is reset, and the SDRAM 1 enters the normal operation mode.

When an actual test is performed by inputting a test command to the input pins P1 to P4 and PA0 to PAn before shipping the SDRAM 1 as a product, the address of a memory cell from which data is read may be switched. Since it is known in advance, the test can be performed in consideration of the switching, and no inconvenience occurs in the test.

Next, the SDRAM 1 constructed as described above
Are described below. (1) In the present embodiment, the SDRAM 1 is provided with the test mode detection circuit unit 30 including the test mode determination circuit 31 and the test mode control circuit 32. Then, the test mode determination circuit 31 determines whether or not the operation mode is a normal operation test mode in which a normal operation is performed, and outputs an H-level determination signal SGX when a read command is generated after determining the test mode. The test mode control circuit 32 responds to the determination signal SGX by using the address signal A0 and the address signal A.
Address buffer / register &
The memory cell 2 is input to the bank select circuit 12 and is different from the memory cell 21 of the address designated by the external device.
1 is read.

Therefore, the user easily recognizes that the contents are different from the expected contents, and recognizes that the user is operating in an abnormal state for some reason (operating in the test mode of the high load test of the cell plate). be able to.

Then, if the user once turns off the system power supply, restarts the system, or restarts the system, it is possible to avoid the continuation of the operation in the test mode of the high load test of the accidentally generated cell plate. That is, the memory cell 2
A user's use in a high load test of a cell plate in which normal operation is performed except that a high voltage is applied between one counter electrode is quickly recognized and avoided.

Therefore, the memory cell 21 can be continuously used without being noticed while a high voltage is applied between the opposing electrodes of the memory cell 21 to shorten the life of the memory cell 21. (2) The test mode determination circuit 31 of the present embodiment outputs the determination signal SGX when a read command is generated. That is, when data is written to a memory cell at a specified address based on a write command, the data is written to a memory cell at the specified address. Therefore,
In an operation of writing data to the memory cell 21 at the specified address and then reading data written to the memory cell 21 at the specified address, the memory cell 21 of the address previously written at the time of the read operation is specified. Because there is no data, it can be easily recognized that the data is different.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. The present embodiment is characterized in that when a test mode (normal operation test mode) is entered by a command and an address signal generated by accident, the test mode is canceled after a lapse of a predetermined time. In the present embodiment, a configuration different from that of the first embodiment will be described for convenience of description.

FIG. 5 is a block circuit diagram for explaining the test mode detection circuit of the present embodiment, and FIG. 6 is a block circuit diagram for explaining the configuration of the SDRAM 1 having the test mode detection circuit.

5 and 6, the test mode detection circuit 30 includes a timer circuit 51. The timer circuit 51 receives the determination signal SGX from the test mode determination circuit 31.
Enter Then, the timer circuit 51 outputs a one-pulse time-up signal STP to the test mode determination circuit 31 after a predetermined time (for example, one second) elapses in response to the H-level determination signal SGX. I have.

When the time-up signal STP is input, the test mode determination circuit 31 loses the output H-level determination signal SGX. Therefore, the test mode control circuit 32 returns to the original normal state.

The test mode determination circuit 31 outputs a determination signal SGX to the mode register 15. The mode register 15 outputs the H level judgment signal SG.
In response to the disappearance of X, the test mode held at that time is reset, and the test mode signal output from the mode register 15 is lost.

FIG. 7 shows a third example of the test mode determination circuit 31.
It is a circuit diagram of a judgment circuit unit 31c. Note that the test mode determination circuit 31 of the present embodiment includes first to third determination circuit units 31a to 31c as in the first embodiment. Then, the first and second determination circuit units 31a, 31 of the present embodiment
The configuration of 1b is the second determination signal SGX2 of the second determination circuit 31b.
Since it is almost the same as the first embodiment except that the disappearance timing of the third determination circuit section 31c is different, the description thereof is omitted, and the third determination circuit section 31c will be described in detail.

For the sake of simplicity, in the present embodiment, the number of normal operation test modes for performing a normal operation is three.
The description will be made on the assumption that the test mode is determined based on the memory address signals A7 and A8 and the normal operation test mode is determined based on the memory address signals A9 to A11. Each illegal pattern in the three types of normal operation test modes is as follows.

The illegal pattern in the first normal operation test mode is a pattern in which the memory address signal A10 is at L level and the other memory address signals A7 to A9 and A11 are at H level. The illegal pattern in the second normal operation test mode is a pattern in which the memory address signal A11 is at the L level and the other memory address signals A7 to A10 are at the H level. The illegal pattern in the third normal operation test mode is a pattern in which the memory address signal A9 is at the L level and the other memory address signals A7, A8, A10, and A11 are at the H level.

In FIG. 7, the third determination circuit 31c
It has a determination unit 56, a gate unit 57, a holding unit 58, and an output unit 59. The determination unit 56 includes a first NAND circuit 61
To 63 and inverter circuits 71 to 73. The gate portion 57 is provided with the first to third transfer gates 6.
4 to 66 and an inverter circuit 74.
The holding section 58 includes first to third latch circuits 67 to 69. The output unit 59 includes a NOR circuit 70, inverter circuits 76 and 77, and a transfer gate 78.

First, the determination section 56 will be described. First
The NAND circuit 61 is a NAND circuit having five input terminals,
Input memory address signals A7 to A9 and A11,
The memory address signal A10 is input via the inverter circuit 71. That is, the first NAND circuit 61 determines whether or not the illegal pattern in the first normal operation test mode has been input.

When the illegal pattern in the first normal operation test mode is input, the first NAND circuit 61 outputs an output signal which falls from the H level to the L level. The output signal of the first NAND circuit 61 is output to the first latch circuit 67 via the first transfer gate 64.

The second NAND circuit 62 is a NAND circuit having five input terminals, and receives the memory address signals A7 to A10 and the memory address signal A11 via the inverter circuit 72. That is, the second NAND circuit 62
It is determined whether an illegal pattern in the second normal operation test mode has been input.

When the illegal pattern in the second normal operation test mode is input, the second NAND circuit 62 outputs an output signal that falls from H level to L level. The output signal of the second NAND circuit 62 is output to the second latch circuit 68 via the second transfer gate 65.

The third NAND circuit 63 is a NAND circuit having five input terminals, and includes memory address signals A7, A8, A10, A11.
, And a memory address signal A9 via the inverter circuit 73. That is, the third NAND circuit 6
In step 3, it is determined whether an illegal pattern in the third normal operation test mode has been input.

When the illegal pattern in the third normal operation test mode is input, the third NAND circuit 63 outputs an output signal that falls from H level to L level. The output signal of the third NAND circuit 63 is output to the third latch circuit 69 via the third transfer gate 66.

Next, the gate section 57 will be described. Each of the first to third transfer gates 64 to 66 includes a PMOS transistor Q11 and an NMOS transistor Q12. Then, the PMOS transistor Q11
Of the first determination signal via the inverter circuit 74
SGX1 is input, and the first determination signal SGX1 from the first determination circuit unit 31a is input to the gate of the NMOS transistor Q12. Therefore, when a mode register set command is input from an external device, the first determination signal SGX1 at H level is output from the first determination circuit unit 31a, and the first to third transfer gates 64 to 66 are turned on. As a result, the first to third NAND circuits 61 to 6
3 are output to the corresponding first to third latch circuits 67 to 69, respectively.

On the other hand, when the mode register set command is not input from the external device, the first determination circuit unit 3
Since the first determination signal SGX1 at the H level is not output from 1a, the first to third transfer gates 64 to 66 are turned off. As a result, the first to third NAND circuits 61 to 6
No. 3 output signal is not output to the corresponding first to third latch circuits 67 to 69, respectively.

Next, the holding section 58 will be described. First
To third latch circuits 67 to 69 include two NAND circuits 67
a to 69a, 67b to 69b and two inverter circuits 6
7c to 69c and 67d to 69d, respectively.

The NAND circuit 67 of each of the latch circuits 67 to 69
Reference numerals a to 69a denote NAND circuits having two input terminals, which are connected to the first to third transfer gates 64 to 66, respectively, and are connected to inverter circuits 67c to
It is connected to its own output terminal via 69c.

The NAND circuit 67 of each of the latch circuits 67 to 69
b to 69b are NAND circuits having two input terminals, which are connected to output terminals of the preceding NAND circuits 67a to 69a, respectively. The other input terminal (reset input terminal) of each of the NAND circuits 67b to 69b receives a one-pulse time-up signal STP from the timer circuit 51 via an inverter circuit 75.

The inverter circuits 67d to 69d of the latch circuits 67 to 69 are respectively connected to the NAND circuits 67b to 67b of the preceding stage.
69b, and is connected to the output terminals of the NAND circuits 67b to 69b.
b, and inverts the output signals of latch circuits 67 to 6 respectively.
9 as an output signal.

Therefore, when each of the latch circuits 67 to 69 is at the H level at the reset input terminal of each of the NAND circuits 67b to 69b and the output of each of the latch circuits 67 to 69 is at the L level, the corresponding one of the NAND circuits 67a to 69a respectively. When an L-level signal is input via the first to third transfer gates 64 to 66, the output signals of the NAND circuits 67a to 69a change from the L level to the H level. Then, the output signals of the next-stage NAND circuits 67b to 69b change from the H level to the L level, and the output signals of the latch circuits 67 to 69 change to the H level. As a result, each of the latch circuits 67 to 69 holds the H-level output signal until the one-pulse time-up signal STP is input from the timer circuit 51. When one pulse time-up signal STP is input to each of the latch circuits 67 to 69, the output thereof becomes L level.

That is, each of the latch circuits 67 to 69 determines that the corresponding first to third NAND circuits 61 to 63 are in the normal operation test mode, and outputs the L level output from the first to third NAND circuits 61 to 63. When the signal is output, the content of the H level is held. And one pulse time-up signal STP
Is input, each of the latch circuits 67 to 69 holds the content of the L level.

Next, the output section 59 will be described. The NOR circuit 70 receives the output signals (contents held) of the latch circuits 67 to 69. That is, the NOR circuit 70 outputs an L-level output signal when the content held by at least one of the latch circuits 67 to 69 is at the H level. The output signal of the NOR circuit 70 is
As a determination signal SGX.

The output terminal of the inverter circuit 76 is connected to the fourth transfer gate 78. The fourth transfer gate 78 is connected to each of the PMOS transistors Q1
3 and an NMOS transistor Q14. The second determination signal SGX2 is input to the gate of the PMOS transistor Q13 via the inverter circuit 77.
The second determination signal S is applied to the gate of the MOS transistor Q14.
GX2 is input. Accordingly, when a read command is input from an external device, the second H level
The determination signal SGX2 is output from the second determination circuit unit 31b,
The fourth transfer gate 78 is turned on. As a result, the output signal of the inverter circuit 76 (judgment signal SGX)
Is output via the fourth transfer gate 78.

Conversely, when a read command is not input from an external device, the second determination signal SGX2 at H level is not output, so that the fourth transfer gate 78 is turned off. As a result, the output signal (judgment signal SGX) of the inverter circuit 76 is not output via the fourth transfer gate 78.

That is, the second determination circuit section 31c includes
When an illegal pattern in any one of the third normal operation test modes is input together with the mode register set command, the corresponding normal operation test mode latch circuit holds the H level content. Then, when a read command is input, the H-level content held by the latch circuit is output as an H-level determination signal SGX.

When one-time-up signal STP is output from timer circuit 51, each latch circuit 6
7 to 69 are reset to hold the contents of the L level.
When the content of each of the latch circuits 67 to 69 becomes L level, the H level determination signal SGX becomes L level and disappears. In response to the disappearance of the H level determination signal SGX, the mode register 15 resets the previously set test mode.

The second judgment signal of the second judgment circuit 31b is used.
SGX2 is held until one pulse time-up signal STP is output and the contents of each of the latch circuits 67 to 69 become L level.
The determination circuit unit 31b receives the time-up signal STP, and eliminates the H-level second determination signal SGX2 based on the time-up signal STP.

Next, the operation of the test mode detection circuit section 30 configured as described above will be described. When the system power supply is turned on, a signal corresponding to the mode register set command is accidentally generated at the input pins P1 to P4, and any of the first to third normal operation test modes is input to the input pins PA7 to PA11. When a signal corresponding to the illegal pattern is generated, the test mode determination circuit 31 latches the H-level determination signal SGX. At this time, the mode register 15 is also in the normal operation test mode. Then, the mode register 15 outputs a test mode signal corresponding to the illegal pattern.

Therefore, when the normal operation test mode is, for example, a high load test of a cell plate, the SDRA
M1 performs a normal operation based on each command and address signal from an external device in a state where a high voltage is applied to the counter electrode of the memory cell.

When a read command is input from an external device, the test mode determination circuit 31 outputs the latched H-level determination signal SGX to the test mode control circuit 3.
2 and the timer circuit 51. Then, the test mode determination circuit 31 eliminates the H-level determination signal SGX in response to the time-up signal STP output from the timer circuit 51 after a predetermined time has elapsed. This H level judgment signal SGX
In response to the disappearance of the test mode, the mode register 15 resets the previously set test mode. Therefore, SDRA
When a predetermined time elapses after the output of the H-level determination signal SGX, the test mode of M1 is released, and the mode shifts to the normal operation mode.

Next, the SDRAM 1 configured as described above
Are described below. (1) In the present embodiment, even if the SDRAM 1 enters a normal operation test mode in which a normal operation is performed by a command and an address signal accidentally generated at power-on or the like, the SDRAM 1 is forcibly activated after a predetermined time has elapsed. The test mode is released and normal operation can be restored.

Therefore, the user is prevented from continuing the operation in the test mode of the high load test of, for example, the cell plate, which has occurred accidentally, without turning off the system power supply once and restarting or restarting the system. As a result, the life of the memory cell 21 is not shortened because the memory cell 21 is continuously used without being noticed while the high voltage is applied between the opposed electrodes of the memory cell 21.

(2) In the present embodiment, the test mode control circuit 32 operates in response to the H-level determination signal SGX as in the first embodiment. Therefore, similarly to the first embodiment, the user easily recognizes that the content is different from the expected content, and operates in an abnormal state for some reason (operates in the test mode of the high load test of the cell plate). Can be more easily recognized.

In the present embodiment, the first to third normal operation test modes, that is, a plurality of types of test modes are detected. However, even if the test is performed in one predetermined normal operation test mode. Good.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIGS. The present embodiment is characterized in that even if the mode register set command and the address signal of the illegal pattern which accidentally enter the normal operation test mode are generated, it is difficult to enter the test mode.

Note that this embodiment is also similar to the second embodiment,
The number of normal operation test modes is three, and whether the test mode is the first to third normal operation strike modes is determined based on the memory address signals A9 to A11 based on the memory address signals A7 and A8. It will be described as an example.

FIG. 8 shows a block circuit showing the configuration of the SDRAM 1 of the present embodiment. In FIG. 8, a test mode determination circuit 31 outputs a chip select signal /
CS, a row address strobe signal / RAS, a column address strobe signal / CAS and a write enable signal / WE, that is, an external command are supplied. The test mode determination circuit 31 is supplied with the external memory address signals A7 to A11 among the external memory address signals A0 to An from the external device as in the second embodiment.

As shown in FIG. 9, the test mode decision circuit 31 has a first decision circuit section 31a and a fourth decision circuit section 31d.
have. The first determination circuit unit 31a of the present embodiment includes:
It has the same configuration as that of the first determination circuit unit 31a of the first and second embodiments. Only when an external command is input and the external command is a mode register set command, the H-level first determination signal SGX1 is determined by the fourth determination. Output to the circuit section 31d.

The fourth determination circuit section 31d receives the first determination signal SG
X1 and external memory address signals A7 to A11 are input. FIG. 10 is a circuit diagram for explaining the fourth determination circuit unit 31d. As shown in FIG. 10, the fourth determination circuit unit 31d of the present embodiment is different from the third determination circuit unit 31c described in the second embodiment in that the inverter circuit 77 and the fourth transfer gate 78 are omitted, and the NOR circuit The only difference is that 70 is replaced with a NAND circuit 80.

Therefore, the fourth determination circuit unit 31 of the present embodiment
As for d, the output of the NAND circuit 80 becomes L level only when all of the first to third latch circuits 67 to 69 are at H level. At this time, the inverter circuit 76 outputs the H level output signal (H level determination signal SGX) to the mode register 15.
And output to the timer circuit 51. On the other hand, when at least one of the first to third latch circuits 67 to 69 is at the L level, the output of the NAND circuit 80 remains at the H level. That is, the inverter circuit 76 outputs an L-level output signal to the mode register 15 and the timer circuit 51.

Here, the first to third latch circuits 67 to 69
Latches the contents of all H levels when all of the first to third NAND circuits 61 to 63 of the determination unit 56 have attained the L level at least once. That is, first to first
When all the test modes (first to third normal operation test modes) corresponding to the third NAND circuits 61 to 63 are all input, all the contents of the first to third latch circuits 67 to 69 are set to the H level. Become. More specifically, the fact that all the contents of the first to third latch circuits 67 to 69 are at the H level means that
The illegal patterns of the first to third normal operation test modes must be generated at least once at the input pins PA7 to PA11.

In other words, the external memory address signal A7
Even if any one of the illegal patterns in the first to third normal operation test modes created in steps A to A11 may occur accidentally, a plurality of types thereof, that is, first to third
Means that all illegal patterns in the normal operation test mode are not generated.

This means that even when an illegal pattern in the first normal operation test mode is accidentally generated when the power supply is turned on, for example, the remaining second and third latch circuits 6
That is, the contents of 8 and 69 are not at the H level, the output of the NAND circuit 80 remains at the H level, and the inverter circuit 76 does not output the determination signal SGX at the H level.

Therefore, when the probability of occurrence by accident is even lower, for example, when all of the illegal patterns in the first to third normal operation test modes have occurred, the fourth determination circuit unit 31d outputs the H-level determination signal. SGX is mode register 1
5 and the timer circuit 51.

The timer circuit 51 is the same as the timer circuit 51 of the second embodiment. The timer circuit 51 responds to the H-level determination signal SGX and outputs a one-pulse time-up signal after a predetermined time has elapsed.
The STP is stored in each of the latch circuits 67 to 69 of the fourth determination circuit unit 31d.
Output to Therefore, the fourth determination circuit unit 31d causes the determination signal SGX at the H level to disappear to the L level in response to the time-up signal STP.

The mode register 15 sets various test modes in the register based on the mode register command from the command decoder 11 and the address buffer / register & bank select circuit 12 and the illegal pattern as in the second embodiment. It has become. At this time, the mode register 15 sets the test mode register when the H level judgment signal SGX is input, and does not set the test mode register when the H level judgment signal SGX is not output. It has become.

The mode register 15 resets the test mode when the judgment signal SGX at the H level disappears to the L level while the register of the test mode is set. Therefore, even if a normal operation test mode in which the probability of accidentally occurring is extremely low occurs, the mode register 15 resets the normal operation test mode after a lapse of a predetermined time.

Next, features of the SDRAM 1 according to the third embodiment configured as described above will be described below. (1) According to the present embodiment, the test mode determination circuit 31
And a fourth determination circuit unit 31d for setting various test modes (first to third normal operation test modes) which are illegal patterns that do not occur at the same time and in which a normal operation is performed. The patterns are detected by the corresponding first to third NAND circuits 61 to 63, and the detection results are respectively detected by the first to third latch circuits 6.
The signal is output to the NAND circuit 80 through 7 to 69.

Then, the first to third latch circuits 67 to 69
Is latched, that is, all the NAND circuits 6
The NAND circuit 80 determines whether 1 to 63 have detected the occurrence of the corresponding illegal patterns. Then, when all the illegal patterns occur, an H-level determination signal SGX is output. That is, even if a mode register set command and one illegal pattern (for example, an illegal pattern for the first normal operation test mode) are accidentally generated, the test mode determination circuit 31 sends the first register to the mode register 15. The normal operation test mode is not set.

Therefore, even if the command and the address signal accidentally generated when the power supply of the SDRAM 1 is turned on are in the normal operation test mode, the SDRAM 1 does not shift to the test mode. As a result, the operation in the test mode of the high load test of, for example, the cell plate which is accidentally generated is avoided, and the memory cell 21 is continuously used without being noticed while the high voltage is applied between the opposite electrodes of the memory cell 21. It is no longer possible to shorten the life of 21.

(2) In the present embodiment, even if the SDRAM 1 is set to the normal operation test mode by a command and an address signal accidentally generated when the power is turned on or the like,
After a lapse of a predetermined time, the test mode is forcibly canceled and the operation can be returned to the normal operation.

Therefore, the user is prevented from continuing the operation in the test mode of, for example, the high load test of the cell plate, which occurred accidentally, without turning off the system power supply once and then restarting or restarting the system. As a result, the life of the memory cell 21 is not shortened because the memory cell 21 is continuously used without being noticed while the high voltage is applied between the opposed electrodes of the memory cell 21.

The embodiments of the present invention are not limited to the above embodiments, but may be implemented as follows. The test mode control circuit 32 of the first and second embodiments
Are input pins PA0 to PAn and address buffer / register &
It is provided on a signal line wired between the bank select circuit 12. This may be provided on a signal line from which the internal memory address signal output from the address buffer / register & bank select circuit 12 is output. Further, it may be provided on a signal line between an input buffer provided for each address signal in the address buffer / register & bank select circuit 12 and a latch circuit. It can be made anywhere as long as it can be changed from.

In the test mode control circuit 32 of the first and second embodiments, two address signals are switched between each other. However, the number of address signals is not limited to two, and three or more are switched between each other. May be.

The test mode control circuit 32 of the first and second embodiments specifies a memory cell different from the specified memory cell by switching the address signal between each other, and reads the contents thereof. This stops switching the address signal between each other and outputs the output data signal DQ.
0 to DQn may be output from a different output pin without being output from the corresponding output pin, and may be changed from the normal operation.

That is, the test mode control circuit 32 sets the I / O
It is provided on the output side signal line or the input side signal line of the O data buffer / register 13 and implemented. Of course, the test mode control circuit 32 may be provided on a signal line between the output buffer in the I / O data buffer / register 13 and its latch circuit.

The test mode control circuit 32 of the first and second embodiments may be implemented as a circuit for changing the content of an external command. That is, as shown in FIG. 11, the first transfer gate 81 is provided on the signal line Lw that supplies the write enable signal / WE to the command decoder 11. Further, a series circuit of the second transfer gate 82 and the inverter circuit 83 is connected in parallel to the first transfer gate 81. Then, the gate of the PMOS transistor of the first transfer gate 81 and the second
The determination signal SGX is input to the gate of the NMOS transistor of the transfer gate 82. Further, the determination signal SGX is input to the gate of the NMOS transistor of the first transfer gate 81 and the gate of the PMOS transistor of the second transfer gate 82 via the inverter circuit 84.

With this configuration, FIG.
The test mode control circuit 32 shown in FIG.
When SGX is output, the first transfer gate 81 turns off and the second transfer gate 52 turns on. Then, the write enable signal / WE input from the write enable signal input pin P4 is inverted via the inverter circuit 83 and input to the command decoder 11.

Therefore, a command different from the external command input from the external device is input to the command decoder 11. That is, a read command is input despite a write command being input from an external device. As a result, the user can easily recognize that the operation is different from the expected operation.

It is to be noted that the present invention may be implemented by inverting a signal constituting an external command such as a chip select signal / CS. Of course, at least one of the address signals A0 to An
One of the input / output data signals DQ0 to DQn may be inverted.

In the test mode control circuit 32 of the first and second embodiments, the content of the latency is changed, that is, the first data is read or written from the input of the read command or the write command in the normal read and write operations. The circuit may be configured to change the number of clocks (access time) up to this point. In this case, in the normal operation test mode, since the latency is changed, the user can easily recognize that the operation is different from the expected operation.

The test mode control circuit 32 of the first and second embodiments is configured to change the content of the burst length, that is, to change the data length that is read continuously or the data length that is written continuously in normal read and write operations. The present invention may be applied to a circuit that changes the circuit. In this case, in the normal operation test mode, since the latency is changed, the user can easily recognize that the operation is different from the expected operation.

In each of the above embodiments, the normal operation test mode in which the normal operation can be executed is determined, and the test mode control circuit 32, the timer circuit 51, and the mode register 15 are controlled. This may be performed by determining all test modes other than the normal operation test mode in which normal operation can be performed, such as an address counter test, and controlling the test mode control circuit 32, the timer circuit 51, and the mode register 15. Good.

The test mode determination circuit 31 of the first and second embodiments receives a determination signal when a read command is input.
SGX output. When a write command or other command is input instead of a read command, the judgment signal
You may implement so that SGX may be output. In other words, the test mode determination circuit 31 is enabled by the write command to determine the determination signal SG.
When X is output, data is written to a memory cell different from the memory cell at the designated address.

Therefore, in an operation of writing data to a memory cell at a specified address and then reading data written to a memory cell at the specified address, the memory at the address previously written at the time of the read operation is specified. Since there is nothing, it can be more easily recognized that the data is different.

When the test mode determination circuit 31 determines a write command and outputs a determination signal SGX,
The test mode control circuit 32 may be implemented in each of the different examples described above. At this time, when the test mode control circuit 32 is provided in the I / O data buffer / register 13, it is provided on a signal line between the input buffer and its latch circuit.

The test mode determination circuit 3 of the first embodiment
1, the external command is directly input from the input pins P1 to P4. However, as shown in FIG. 12, an internal command from the command decoder 11 may be input to determine the mode register set command. Of course, the present invention may be applied to the test mode determination circuit 31 of the second and third embodiments.

The test mode determination circuit 3 of the first embodiment
1, input external memory address signals A0-An directly from input pins PA0-PAn, but input internal memory address signals A0-An output from address buffer / register & bank select circuit 12 as shown in FIG. Then, the test mode may be determined. Of course, the second and third
It may be applied to the test mode determination circuit 31 of the embodiment.

The test mode determination circuit 31 of the first and second embodiments outputs the H-level determination signal SGX latched based on the generation of the H-level second determination signal SGX2. Alternatively, the determination signal SGX at the H level may be output based on the generation of the one determination signal SGX1, and may be implemented.

In the second and third embodiments, the first to third
The time during which the timer circuit 51 outputs the time-up signal STP is the same as in the normal operation test mode. The time for outputting the time-up signal STP may be changed for each of the first to third normal operation test modes. In this case, the timer circuit 51 is provided for each of the latch circuits 67 to 69, and the output of the H level of each of the latch circuits 67 to 69 is directly output to the corresponding timer circuit as a signal for starting the timing operation. Becomes

In the second and third embodiments, the test mode of the mode register 15 is reset when the determination signal SGX at the H level disappears. This may be done by resetting the test mode of the mode register 15 based on the time-up signal STP.

In the second and third embodiments, the timer circuit 51 is provided. However, a self-refresh counter provided in the SDRAM 1 may be used as the timer circuit 51. In this case, the counting operation is performed until the value reaches a predetermined value in response to the determination signal SGX at the H level. At this time, the count value may be appropriately changed depending on the type of the test mode as described above.

In the third embodiment, the timer circuit 5 is used to forcibly cancel the normal operation test mode after a predetermined time.
Although 1 is provided, the test mode may be forcibly canceled without the timer circuit 51.

In the second embodiment, the test mode control circuit 32 is provided. However, the test mode control circuit 32 is omitted, and the timer circuit 51 only forcibly cancels the normal operation test mode after a predetermined time. May be implemented.

In the third embodiment, the test mode control circuit 32 is not provided unlike the first and second embodiments.
This may be implemented in the third embodiment by providing the test mode control circuit 32 as in the first and second embodiments. In this case, for example, it is preferable to provide the second determination circuit unit 31b of the test mode determination circuit 31 as in the first and second embodiments. The fourth ON / OFF operation based on the second determination signal SGX2 from the second determination circuit 31b described in the third determination circuit unit 31c of the second embodiment.
Preferably, a transfer gate similar to the transfer gate 78 is provided in the fourth determination circuit unit 31d (the output terminal side of the inverter circuit 76).

In each of the above embodiments, the present invention is embodied in the SDRAM. However, other various RAMs such as FCRAM, ROM,
The present invention may be embodied in a semiconductor storage device such as an EEPROM. In each of the above embodiments, the present invention is embodied in a semiconductor memory device, but may be embodied in a semiconductor device such as a signal processing device or the like having a test mode.

[0156]

According to the first to tenth aspects of the present invention,
When the test mode is erroneously entered, there is an excellent effect that the user can easily recognize the test mode.

According to the invention described in claims 11 to 15 and 21, there is an excellent effect that the test mode can be canceled even if the test mode is erroneously entered. According to the invention of claim 15, there is an excellent effect that the user can easily recognize when the test mode is erroneously entered.

According to the inventions described in the sixteenth to twentieth and twenty-second aspects, there is an excellent effect that a test mode can be made difficult to enter. Claim 17-
According to the invention described in Item 20, in addition, there is an excellent effect that even if the test mode is erroneously entered, the test mode can be canceled. Further, according to the twentieth aspect, there is an excellent effect that the user can easily recognize when the test mode is erroneously entered.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram illustrating a test mode detection circuit according to a first embodiment.

FIG. 2 is a circuit diagram illustrating a test mode determination circuit according to the first embodiment.

FIG. 3 is a circuit diagram illustrating a test mode control circuit according to the first embodiment.

FIG. 4 is a block circuit diagram illustrating a configuration of the SDRAM according to the first embodiment.

FIG. 5 is a block circuit diagram illustrating a test mode detection circuit according to a second embodiment.

FIG. 6 is a block circuit diagram illustrating a configuration of an SDRAM according to a second embodiment.

FIG. 7 is a block circuit diagram illustrating a third determination circuit unit according to the second embodiment.

FIG. 8 is a block circuit diagram illustrating a configuration of an SDRAM according to a third embodiment;

FIG. 9 is a block circuit diagram illustrating a test mode determination circuit according to a third embodiment.

FIG. 10 is a circuit diagram illustrating a fourth determination circuit unit according to the third embodiment.

FIG. 11 is a block circuit diagram illustrating another example of the test mode control circuit.

FIG. 12 is a block circuit diagram for explaining another example of the test mode determination circuit.

[Explanation of symbols]

1 SDRAM 11 Command Decoder 12 Address Buffer / Register & Bank Select Circuit 13 I / O Data Buffer / Register 15 Mode Register 30 Test Mode Detection Circuit 31 Test Mode Judgment Circuit 31a First Judgment Circuit 31b Second Judgment Circuit 31c 3 determination circuit section 31d fourth determination circuit section 32 test mode control circuits 41 to 44 first to fourth transfer gates 51 timer circuit 61 to 63 NAND circuit 80 NAND circuit

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yoshiharu Kato 2-844-2 Kozoji-cho, Kasugai-shi, Aichi F-term within Fujitsu VSI Ltd. 5L106 AA01 DD11

Claims (22)

[Claims] 1. A determination circuit for detecting that a test mode has been entered, and a value or an access time of at least one operation of the test mode based on detection of a test mode entry by the determination circuit. And a control circuit for changing the operation of the semiconductor device. 2. A determination circuit for detecting entry into a test mode in which an operation mode including address input, access to a memory cell from a decoder, and data input / output is executable, and a test mode entry by the determination circuit. And a control circuit for changing a value or an access time of at least one of the operation modes from a normal operation based on the detection. 3. The semiconductor device according to claim 2, wherein said determination circuit has entered a test mode capable of executing an operation mode including address input, access to a memory cell from a decoder, and data input / output. Detecting a command signal relating to at least one operation of the operation mode after detecting the operation mode, the control circuit outputs at least one of the operation modes in response to the determination signal. A semiconductor device characterized by changing its value or access time from normal operation. 4. The semiconductor device according to claim 2, wherein the control circuit changes a memory address signal to another memory address signal. 5. The semiconductor device according to claim 2, wherein the control circuit changes the input data to another input data or the output data to another output data. apparatus. 6. The semiconductor device according to claim 2, wherein the control circuit changes a command signal to another command signal. 7. The semiconductor device according to claim 2, wherein the control circuit changes the number of clocks until the first output data is read or the number of clocks until the first input data is fetched. A semiconductor device characterized by the following. 8. The semiconductor device according to claim 2, wherein the control circuit changes a length of continuously output output data or a length of continuously input data. A semiconductor device characterized by the following. 9. The semiconductor device according to claim 2, wherein the control circuit supplies a signal supplied to a signal line to another signal line. 10. The semiconductor device according to claim 2, wherein the control circuit inverts a signal supplied to a signal line. 11. A determination circuit for detecting entry into a test mode in which an operation mode including an address input, access to a memory cell from a decoder, and data input / output is executable, and a test mode entry by the determination circuit. A semiconductor device, comprising: a timer circuit that starts a timekeeping operation in response to detection, ends the test mode, and measures a time for shifting to a normal operation mode. 12. The semiconductor device according to claim 11, wherein said determination circuit has entered a test mode capable of executing an operation mode including an address input, access to a memory cell from a decoder, and data input / output. Detecting a command signal related to at least one operation in the operation mode after detecting the operation signal, and the timer circuit starts a timing operation in response to the determination signal. A semiconductor device comprising: 13. The semiconductor device according to claim 11, wherein the timer circuit measures time for shifting to a different normal operation mode according to a type of a test mode. . 14. The semiconductor device according to claim 11, wherein said timer circuit is a self-refresh counter. 15. The semiconductor device according to claim 11, further comprising a control circuit for the semiconductor device according to claim 2, wherein the control circuit includes a timer. A semiconductor device wherein the changed state is returned to a normal operation based on a time-up signal of a circuit. 16. A plurality of predetermined combinations of illegal patterns for a plurality of test modes capable of executing an operation mode including address input, access to a memory cell from a decoder, and data input / output. A semiconductor device, comprising: a determination circuit for determining and entering a test mode in which the operation mode can be executed when all of a plurality of illegal patterns in a predetermined combination are detected. 17. The semiconductor device according to claim 16, wherein when the determination circuit enters a test mode in which an operation mode can be executed, a timing operation is started, the test mode is ended, and a transition is made to a normal operation mode. Semiconductor device, comprising a timer circuit for measuring time for the operation. 18. The semiconductor device according to claim 17, wherein the timer circuit is the timer circuit of the semiconductor device according to claim 13 or 14. 19. The semiconductor device according to claim 16, further comprising a control circuit of the semiconductor device according to claim 2. Description: 20. The semiconductor device according to claim 17, further comprising a control circuit of the semiconductor device according to claim 1, wherein a time-up of the timer circuit with respect to the control circuit is provided. A semiconductor device wherein the changed state is returned to a normal operation based on a signal. 21. A judgment circuit for detecting that the test mode has been entered, and a timer operation is started in response to the detection of the test mode entry by the judgment circuit, and the test mode is ended and shifted to the normal operation mode. And a timer circuit for measuring a time for the semiconductor device. 22. A plurality of illegal patterns in a plurality of predetermined combinations for a plurality of test modes are individually determined, and when all of the plurality of illegal patterns in a predetermined combination are detected, the test mode is entered. 1. A semiconductor device, comprising: