JP2008192309A - Semiconductor integration circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integration circuit device provided with a BIST (Built-In Self Test) controller. <P>SOLUTION: A command decode part can receive not only an external command but also an internal command, a BIST controller 6 has a command generating part 11 and an address generating part 12, the command decode part sends out a start instruction signal indicating check to the BIST controller when an external entry command is decoded, the command generating part 11 of the BIST controller sends out an operation mode signal indicating check to an error detecting circuit when the start instruction signal is received, while makes the address generating part 12 generate successively addresses in accordance with operation timing of the operation mode signal and supplies them to a memory array. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device including a memory device having a super self-refresh mode. The present invention also relates to a semiconductor integrated circuit device including a memory device having a BIST (BUILT-IN SELF TEST) mode.

  The present invention basically relates to a memory device using DRAM (Dynamic Random Access Memory) cells (for example, a clock synchronous DRAM: SDRAM (Synchronous Dynamic Random Access Memory)). Is a refresh operation that reads and rewrites the charge information before the charge of the DRAM cell disappears, and is a super self-refresh operation that is a longer cycle refresh operation than a normal self-refresh operation. Is done.

  Patent Document 1 discloses a configuration of an SDRAM incorporating such a Super Self-Refresh mode. In particular, FIG. 1 of Patent Document 1 shows first to fourth ECCs (Error Correcting Codes) − corresponding to the first to fourth banks of the SDRAM in order to achieve the Super Self-Refresh mode. A codec-decoder (CODEC) circuit is provided in the SDRAM as the first to fourth encoding / decoding circuits, and the first to fourth ECC-CODEC circuits are connected to the control logic (CONTROL LOGIC) of the SDRAM (that is, An example of connection to a control circuit) is disclosed. Further, in FIG. 2 of Patent Document 1, in order to achieve the Super Self-Refresh mode, one common ECC-CODEC circuit is provided in the SDRAM for the first to fourth banks of the SDRAM. An example in which an ECC-CODEC circuit is connected to a control logic (ie, control circuit) of an SDRAM is disclosed.

  Further, the paragraphs [0005] and [0006] of Patent Document 1 describe that “when the dynamic RAM enters an operation mode in which only the data holding operation is performed, a plurality of data is processed using the ECC-CODEC circuit. A check bit for error detection and correction is generated and stored, and a refresh operation is performed by extending the refresh cycle within an allowable range of error generation by the error correction operation using the check bit (that is, the refresh operation of this long cycle is performed). The error bit is corrected using the data and check bits by the ECC-CODEC circuit before performing a self-refresh operation) and returning to the normal operation from the data holding operation. .

JP 2002-056771 A (see claims, paragraphs [0005] and [0006], etc.).

  However, Patent Document 1 does not disclose the BIST (BUILT-IN SELF TEST) operation of the SDRAM.

  Therefore, an object of the present invention is to provide a semiconductor integrated circuit device having a BIST controller, and when a command decode unit decodes a BIST entry command as an external command, a start command signal indicating a check is sent to the BIST controller. Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit device capable of performing a self-test operation.

  Other objects of the invention will become apparent as the description proceeds.

  The semiconductor integrated circuit device according to the present invention is as follows.

(1) A semiconductor integrated circuit device having a dynamic RAM, the dynamic RAM having a memory array, a RAM control unit, an error detection circuit, and a BIST (BUILT-IN SELF TEST) controller, In the semiconductor integrated circuit device, the RAM control unit includes a command decoding unit that receives an external command from the outside of the dynamic RAM and decodes the external command.
The command decoding unit can also accept internal commands generated by the BIST controller, and can also decode the internal commands.
The BIST controller has a command generation unit and an address generation unit,
When the command decode unit decodes the BIST entry command as the external command, the command decode unit sends a start command signal indicating a check to the BIST controller,
Upon receiving the activation command signal, the command generation unit of the BIST controller sends an operation mode signal indicating the check to the error detection circuit, and also transmits the operation mode signal to the address generation unit of the BIST controller. Sequentially generate an address corresponding to the operation timing of and supply to the memory array,
When the error detection circuit receives the operation mode signal, the error detection circuit generates write data in accordance with sequentially generated addresses, writes the generated write data to a predetermined area or all areas of the memory array, and then sequentially generates the write data. Expected value data is generated according to the address, compared with the information data read from the memory array, an error in the information data is detected, and when the error detection is completed, the BIST controller uses the end signal as the internal command Output to command decode section
The semiconductor integrated circuit device, wherein when the command decoding unit receives and decodes the end signal as the internal command, the transmission of the operation mode signal is stopped.

(2) In the semiconductor integrated circuit device described in (1) above,
The semiconductor integrated circuit device according to claim 1, wherein the BIST entry command is input to the dynamic RAM by a user.

  According to the present invention, in a semiconductor integrated circuit device including a BIST controller, when a command decode unit decodes a BIST entry command as an external command, a start command signal indicating a check is sent to the BIST controller, thereby A semiconductor integrated circuit device capable of performing a test operation can be obtained.

  Next, embodiments of the present invention will be described with reference to the drawings.

  Super Self-Refresh (long cycle self-refresh) operation targeted by the present invention is not normal refresh, and does not perform memory operation in order to thoroughly reduce the current consumed by the refresh operation of the memory device. When a long-term shutdown state is entered (when such a command is set for the memory device), the power supply of the memory device is switched to a specific part (for example, the counter electrode potential of the memory cell capacity: cell plate: or the control circuit or counter of the refresh unit) To reduce the number of refreshes within a unit period, for example, by extending the DRAM cell refresh interval to several tens of times (10 seconds, etc.). The current is reduced.

  In this Super Self-Refresh, by reducing the number of refreshes per unit time, charge is lost for a small number of cells (for example, appearance probability: 0.0037%: about spilled or defective bit: Tail-bit :). However, the cell information may be broken, but a memory device having this Super Self-Refresh mode has ECC (Error Correcting Code) − for restoring (error correcting) the information to these cells. It is premised on having a CODEC (Coder-Decoder) circuit.

  In other words, Super Self-Refresh is an ultra-low current consumption by providing such an ECC-CODEC circuit to provide a long refresh stop period, and during the refresh stop period, the internal power supply is reduced to 0V. Is a self-refresh control characterized by realizing

  Referring to FIG. 1, the semiconductor integrated circuit device on which the present invention is based has a 64 Mb SDRAM 10 incorporating a Super Self-Refresh mode. The SDRAM 10 incorporating the Super Self-Refresh mode is a semiconductor dynamic memory that outputs and inputs data in synchronization with the external input clock CLK, and includes first to fourth memory arrays (first to fourth banks # 0). Have ~ # 3). For convenience, among the first to fourth banks # 0 to # 3, the second and third banks # 1 and # 2 are not shown, but the second and third banks # 1 and # 2 are also the first and first banks. This is the same configuration as banks # 0 and # 3. In this semiconductor integrated circuit device, CLK (clock), CKE (clock enable), CS (chip select), WE (write enable), CAS (column address enable), RAS (row address enable) clock terminals and Control system signal terminals, A0-A11 (memory array address), BA0-1 (bank address) address system signal terminals, DQM (data mask signal), DQ0-7 (data input / output signal) data input / output system Has a signal terminal.

  Although not shown, this semiconductor integrated circuit device has Vcc and Vss (GND) terminals as external power supply terminals.

  The semiconductor integrated circuit device further includes a control logic (CONTROL LOGIC) 209 of the SDRAM 10 and an ECC-CODEC circuit 7 provided in common for the first to fourth banks # 0 to # 3 of the SDRAM 10. And an ECC controller 6 that is connected between the control logic 209 and the ECC-CODEC circuit 7 and controls the ECC-CODEC circuit 7 under the control of the control logic 209.

  The control logic 209 receives an external command based on a combination of CS (chip select), WE (write enable), CAS (column address enable), and RAS (row address enable) signals, and decodes the command. (COMMAND DECODE) 8 The input buffer circuit (COMMAND DECODE) 8 can accept the end signal (READY) from the ECC controller 6 and the internal operation command 2 as an internal command, and can also decode the internal command.

  Under the control of the input buffer circuit (COMMAND DECODE) 8 of the control logic 209, the ECC controller 6 controls the ECC-CODEC circuit 7 as follows and performs a Super Self-Refresh operation.

  A super self-refresh operation of the semiconductor integrated circuit device of FIG. 1 will be briefly described with reference to FIG.

  In this semiconductor integrated circuit device, an input buffer circuit (COMMAND DECODE) 8 of a control logic (CONTROL LOGIC) 209 of the SDRAM 10 decodes a command from the outside by a combination of signals of CKE, CS, WE, CAS, and RAS. When a Self-Refresh entry command (SSELF: see External Operation on the third line in FIG. 2) is obtained, a start (START) command signal (ENCODE) is sent as a control signal 1 to the ECC controller 6. The start command signal (ENCODE) is shown as a portion rising on the fourth line in FIG. When the input buffer circuit (COMMAND DECODE) 8 obtains a Super Self-Refresh entry command (SSELF), the SDRAM 10 is stopped from supplying an external clock (CLK: see the second line in FIG. 2). When receiving the start command signal (ENCODE), the ECC controller 6 is supplied with an internal clock (ICLK: refer to the sixth line in FIG. 2). The ECC controller 6 is supplied with the internal clock and sends the encoding as the operation mode signal 4 to the ECC-CODEC circuit 7.

  When the ECC-CODEC circuit 7 receives the encoding as the operation mode signal 4, the ECC-CODEC circuit 7 starts the encoding operation. In other words, the ECC-CODEC circuit 7 generates parity data (check bits for error detection / correction) based on the information data of each bank of the memory, and the generated data is stored in the parity memory area (PARITY) of each bank of the memory. (Parity Generation with Refresh: Refer to Internal Operation of the 10th line (last line) in FIG. 2).

  When the generation of parity data by the ECC-CODEC circuit 7 and the writing of the generated data to the parity memory area (PARITY) are completed, the ECC controller 6 sends an end signal (READY: refer to the ninth line in FIG. 2) to the internal command 2 To the input buffer circuit (COMMAND DECODE) 8.

  When the input buffer circuit (COMMAND DECODE) 8 receives and decodes the end signal (READY) as the internal command 2, the input buffer circuit (COMMAND DECODE) 8 stops the supply of the start command signal (ENCODE: the fourth line in FIG. 2) to the ECC controller 6. The ECC controller 6 also stops supplying an internal clock (ICLK: sixth line in FIG. 2).

  When the input buffer circuit (COMMAND DECODE) 8 receives and decodes the end signal (READY) as the internal command 2, the self-refresh control circuit 9 of the control logic (CONTROL LOGIC) 209 of the SDRAM 10 is appended to the top of FIG. Start Super Self-Refresh operation. In this Super Self-Refresh operation, the internal power is turned off (Power OFF: POFF: see Internal Operation in the last line in Fig. 2), the long-term stop state is maintained (for example, 10 seconds), and the internal power is turned on (Power ON: PON: Fig. No. 2 last line Internal Operation), normal refresh (Burst-Refresh: See Last Line Internal Operation in FIG. 2: All cells are performed in burst. No error correction based on parity data is performed.), POFF, PON , Repeat Burst-Refresh any number of times.

  After that, the input buffer circuit (COMMAND DECODE) 8 of the control logic (CONTROL LOGIC) 209 of the SDRAM 10 decodes a command from the outside by a combination of signals of CKE, CS, WE, CAS, RAS, and a Super Self-Refresh exit command. When (SSELFX: see External Operation on the third line in FIG. 2) is obtained, a stop (STOP) command signal (DECODE) is sent to the ECC controller 6 as a control signal 1. The stop command signal (DECODE) is shown as a portion rising on the fifth line in FIG. When receiving the stop command signal (DECODE), the ECC controller 6 is supplied with an internal clock (ICLK: the sixth line in FIG. 2). The ECC controller 6 is supplied with the internal clock, and sends the decode as the operation mode signal 4 to the ECC-CODEC circuit 7.

  When the ECC-CODEC circuit 7 receives the decoding as the operation mode signal 4, the ECC-CODEC circuit 7 starts the decoding operation. That is, the ECC-CODEC circuit 7 reads out the parity data and corrects and rewrites the error of the information data based on the data and the information data of the memory (Correct with Refresh: Internal of the last line in FIG. 2). Operation). This error correction and rewriting are performed for all the cells in the memory area.

  When error correction and rewriting by the ECC-CODEC circuit 7 are completed, the ECC controller 6 outputs an end signal (READY) to the input buffer circuit (COMMAND DECODE) 8 as an internal command 2.

  When the end buffer (READY) is received and decoded as the internal command 2, the input buffer circuit (COMMAND DECODE) 8 stops the supply of the stop command signal (DECODE: the fifth line in FIG. 2) to the ECC controller 6. The ECC controller 6 also stops supplying an internal clock (ICLK: sixth line in FIG. 2).

  This exits the Super Self-Refresh mode and returns to the normal operation (in the illustrated case, the normal Self-Refresh operation). This normal self-refresh operation is also terminated by an external self-refresh exit command (SELFX: see External Operation on the third line in FIG. 2).

  That is, this semiconductor integrated circuit device enters ENTRY-TIME appended to the top of FIG. 2 when a Super Self-Refresh entry command (SSELF) is obtained from the outside. In this entry-time, parity bits are generated and written while all bits are read. Subsequently, the process proceeds to Super Self-Refresh (long-cycle self-refresh) appended to the top of FIG. 2, and the refresh is performed in a long cycle that exceeds the ability of normal refresh, and the generated error is left unattended.

  Furthermore, when the Super Self-Refresh exit command (SSELFX) is obtained from the outside, this semiconductor integrated circuit device enters EXIT-TIME appended at the top of FIG. In this EXIT-TIME, all bits are read and parity bits are used to correct and rewrite error data generated during a long cycle refresh.

  As shown in FIG. 1, this semiconductor integrated circuit device includes an ECC controller 6 and an ECC-CODEC circuit (a Coder circuit that generates a parity bit from original memory data and its parity bit for the Super Self-Refresh operation. 7 is simply added to the SDRAM 10 and the circuit of the DRAM 10 is hardly changed. The ECC controller 6 independently issues an internal command 2 and an internal address 3 to the SDRAM 10, and the input buffer circuit (COMMAND DECODE) 8 is not only an external command (that is, an external command) but also an internal command (that is, an internal command). ) 2 is also accepted. The ECC controller 6 issues a CODEC operation mode 4 as a control instruction to the ECC-CODEC circuit 7, receives an error detection (ERROR) / error position detection (LOCATION) signal 5 from the ECC-CODEC circuit 7, and efficiently Performs parity bit generation / writing and error correction operations.

  Referring to FIG. 3, the ECC controller 6 includes a command generation unit (COMMAND-GENERATOR) 11, an address generation unit (ADDRESS-GENERATOR) 12, and register circuits 13 to 17. The command generator 11 and the address generator 12 are both single-phase synchronous circuits. The ECC controller 6 includes control signals (ENCODE = start command signal, DECODE = stop command signal, MODE = operation mode designation signal) 1 generated from the control logic (CONTROL LOGIC) 209 (FIG. 1) in the SDRAM 10 (FIG. 1). In response to a control signal 5 generated from the ECC-CODEC circuit 7 (ERROR and LOCATION = error generation and error position signal used for error correction), the CODEC operation mode signal 4 is determined, an internal command 2, an internal address 3 Is generated. Some signals are output to the outside of the ECC controller 6 via the register circuits 14 to 17. Each of the register circuits 13 to 17 includes an input terminal IN, an output terminal OUT, a terminal CLK supplied with an internal clock (ICLK), a terminal CLRB supplied with a reset signal RST, and the like.

  4A shows an FF (flip-flop) circuit used as each of the register circuits 13 to 17, and FIG. 4B shows an internal configuration of the FF circuit.

  4A, this FF circuit receives a signal at an input terminal IN and receives a switch 41 controlled by clocks CLK and CLKB, and a switch 42 which receives an output signal from the switch 41 and is controlled by clocks CLK and CLKB. And a switch 43 that receives the output signal of the switch 42 and is controlled by the clocks CLK and CLKB, and a switch 44 that receives the output signal of the switch 43 and is controlled by the clocks CLK and CLKB. The output signal of the switch 44 is sent to the output terminal OUT. The FF circuit further includes a NAND gate 45 that receives the output signal of the switch 41 and the signal of the terminal CLRB, an inverter 46 that inverts the output signal of the NAND gate 45 and sends it to the switch 43 as an input signal, and the output signal of the switch 43 A NAND gate 47 that receives a signal from the terminal CLRB, and an inverter 48 that inverts an output signal from the NAND gate 47 and sends the inverted signal to the output terminal OUT. The output signal of the NAND gate 47 is sent to the output terminal OUTB.

  4A and 4B, the terminal CLKB is a terminal to which a clock obtained by inverting the clock of the terminal CLK is supplied, as is apparent from FIG. FIG. 5 shows an operation example of the FF circuit.

  Returning to FIG. 3, the ECC controller 6 outputs an end signal (READY) of the output signals to the control logic (CONTROL LOGIC) 209 (FIG. 1) in the SDRAM 10 (FIG. 1). The end signal (READY) is used when the generation and writing of parity data (Parity Generation with Refresh: the last line in FIG. 2) is completed and the error correction and rewriting of information data (Correct with Refresh: FIG. Output when the last line (2) is completed.

  CODECE (CODEC Enable), SYNDROME, PARITY, CORRECT, and INIT are used in the ECC-CODEC circuit 7 as the CODEC operation mode signal 4, and various operations associated with ECC (activation of the CODEC and memory circuit, generation of parity data, Writing, generation of error correction data and writing thereof).

  IRAS, ICAS, and IWE are control signals for the internal memory, and correspond to RAS, CAS, and WE in the SDRAM 10. In FIG. 3, IA (0) to IA (12), IA (13), IBA (0), and IBA (1) correspond to the internal row / column address (multiplex signal) and bank address, respectively. To do. FIGS. 3A and 3B are examples of applying 256 Mb SDRAM as shown in FIGS. 17 and 18 to be described later and adding parity bits in the Row direction. IA (13) is an extended Row address signal for selecting parity bits. (It does not exist as an external address signal).

  The ECC controller 6 in FIG. 3 will be described in more detail.

  3, the ECC controller 6 includes the command generation unit 11, the address generation unit 12, and the output register circuits (flip-flop circuits) 13 to 17, as described above, and the SDRAM T10 (FIG. 1) and the ECC-CODEC circuit ( The purpose is to operate a parity-generation and correct operation (see FIG. 2) by operating the encoding / decoding circuit) 7 (FIG. 1) from the inside.

  The Super Self-Refresh mode is an operation that can be operated by an external command, as described in Patent Document 1 described above. In the present invention, a circuit called an ECC controller 6 is provided and operates in a self-contained manner by an internal operation, so that the user need only control the entry / exit commands (SSELF and SSELFX in FIG. 2), and the burden on the user is reduced. There is also a purpose to reduce.

  The command generator 11 and the address generator 12 are single-phase synchronous sequential circuits composed of combination circuits such as NAND and NOR and flip-flop circuits, and can be designed with a logic synthesis tool (existing or simple). It is.

  Further, the output signals of the command generator 11 and the address generator 12 are output to the ECC-CODEC circuit 7 and the input buffer circuit (COMMAND DECODE) 8 of the control logic 209 of the SDRAM 10 through the output register circuits 14 to 17, and the internal synchronous clock. The delay time from the signal (ICLK) is minimized to achieve synchronous operation with a sufficient operating margin. Control signals sent from the command generator 11 to the address generator 12 are also sent through the output register circuit 13 to ensure a sufficient operating margin. Other exchanges of data through similar register circuits are also performed.

  An error detection signal (ERROR, LOCATION) 5 returned from the ECC-CODEC circuit 7 to the command generation unit 11 is also transmitted through an output register circuit (78 in FIG. 22 shown later), and further, an MA (main amplifier) output ( ECC-CODEC is output in the same manner as when the output data is temporarily buffered in the output register (Data Output Register: FIG. 1 and FIG. 17 and FIG. 18 shown later) and then externally output from the data output buffer circuit (DQ). The output data (MA output signal) input to the circuit 7 is once buffered in the output register circuit (shown later by “FF” in FIG. 30). Conversely, input data from the data input buffer circuit (DQ) is temporarily buffered in an input register (Data Input Register: see FIG. 1 and FIG. 17 and FIG. 18 shown later), and then sent to a WB (write buffer). Similarly, the parity bit output from the ECC-CODEC circuit 7 may be temporarily buffered in the output register circuit and then sent to the WB and written to the memory cell (strictly, whether the register is necessary or not is Depending on the operating speed of the clock, it is not necessary when the speed is low (not shown in FIGS. 30 and 31 shown later).

  As will be described below, the meaning of inserting the register circuit is slightly different depending on the circuit.

  Since the command generation unit 11 and the address generation unit 12 are large-scale sequential circuits, a hazard is generated in the output signal, which causes a malfunction. Also, the output delay time varies greatly depending on the operation timing. In order to eliminate these operating margin reduction factors, the output register circuit is inserted.

  The arrangement of the ECC-CODEC circuit 7 is far from the ECC controller 6, and the delay time generated in its output and error detection signals (ERROR, LOCATION) cannot be ignored. Error detection / correction triggers interrupt operations such as stopping internal command generation and error correction write operations, so the delay time must be as small as possible (must be within one clock), but an output register circuit is inserted. Otherwise, the SYNDROME calculation time in the ECC-CODEC circuit 7 also appears in the delay time, and the synchronization operation with the ECC controller 6 becomes difficult. That is, the output register circuit is inserted in order to minimize the delay of the error detection signal by buffering the register circuit once.

  The DQ input / output register circuit is provided to accommodate CAS latency and burst operation (this is an existing configuration), but the register circuit between the ECC-CODEC circuit 7 and the MA / WB is the same.

  Here, input / output signals of the ECC controller in FIG. 3 will be described below.

  ENCODE: Parity-Generation start / stop signal. Command generator input signal ETRIG.

            As shown in FIG. 2, when this signal becomes HIGH, the parity generation operation is started in synchronization with the internal synchronization clock (ICLK). When it becomes LOW, it resets (initializes) itself and stops operation.

  DECODE: Correct operation start / stop signal. Input signal DTRIG for command generator.

            As shown in FIG. 2, when this signal becomes HIGH, the correct operation is started in synchronization with the internal synchronous clock (ICLK). When it becomes LOW, it resets (initializes) itself and stops operation.

  MODE ... ECC controller operation mode signal. For example, there are the following.

            4B, 2B, 1B, HB, QB ... Corresponds to PASR (Partial Array Self-Refresh) mode, and changes the coding area (access area).

            4B: For 4 banks (all bits). Default state. 2B: Targets two banks, Bank0 and 1. 1B: Targets one bank of Bank0. HB: Only for Bank0 1/2 (X address lower). QB: Only for Bank0 1/4 (X address lower).

            PASR mode is a mode that reduces the data retention current by narrowing the self-refresh area.

            SSROP: Change whether internal operations are performed simultaneously for 4 banks or for each bank. In the case of the configuration of FIG. 1 (and also in the case of FIG. 17 shown later), since the ECC-CODEC circuit is arranged for each IO line, only the operation for each bank can be selected. As in the case of 18, the ECC-CODEC circuit can be selected for each MA / WB of each bank. The simultaneous operation of 4 banks increases current consumption, but the encoding / decoding time can be shortened to 1/4.

            CODE1, CODE2: When the product code is two codes, only one of the codes is operated. In the default, both codes are operated, but in the case of a probe test, the correction capability is lowered by the operation of only one of them, so that the missed correction can be efficiently repaired redundantly.

  ERROR ... Error detection signal. After the SYNDROME calculation in ECC-CODEC, it is HIGH when there is an error, and LOW when there is no error.

            When ERROR = HIGH (with error), shift to error position detection operation.

  LOCATION: Error position detection signal. If an error position is hit in the error position detection operation, it becomes HIGH and a correction WRITE operation is performed.

  ICLK: Internal synchronous clock signal. All Parity-Generation / Correct operations are based on this clock.

  RST ... Reset signal. A pulse signal is sent to all chips when the power is turned on or when the <MRS> command input is started up.

  READY... As shown in FIG. 2, when the parity-generation / correct operation is completed, a pulse signal is output.

  CODECE, SYNDROME, PARITY, CORRECT, INIT ... ECC-CODEC circuit operation mode signals (see also Fig. 6).

            The operation mode is switched according to each operation timing of Parity-Generation / Correct.

            CODECE: When this signal is HIGH, CCLK / CCLK2 is generated based on ICLK and input to the ECC-CODEC circuit. That is, when this signal is HIGH, the ECC-CODEC circuit can perform a cyclic shift operation (see FIG. 25 shown later).

            SYNDROME: When this signal is HIGH, output bits can be sequentially fetched from the MA one by one to perform syndrome calculations and parity bit calculations (the shift register performs forward and cyclic shifts).

            PARITY: When this signal is HIGH, the calculated parity bits (bits of each shift register) can be sequentially output to the WB bit by bit. At that time, the shift register is sequentially reset (the shift register is a forward / cyclic shift).

            CORRECT: When this signal is HIGH, data is not input / output from / to the outside, and reverse / cyclic shift operation (error position detection operation) can be performed using only the shift register.

            INIT: When this signal is HIGH, the shift register is reset while cyclically shifting.

  IRAS, ICAS, IWE ... Internal command signal. The specifications are the same as external commands. There is no CS in the internal operation because it is unnecessary.

            A command corresponding to the timing of Parity-Generation / Correct operation is output.

  IA (0) to IA (12), IA (13), BA (0), BA (1) ... Internal address, internal bank address.

            An address corresponding to the timing of Parity-Generation / Correct operation is output.

  Referring to FIG. 6, an ECC-CODEC circuit 7 used in the semiconductor integrated circuit device of FIG. 1 is shown. The ECC-CODEC circuit 7 is formed by combining a Coder circuit (encoder) and a Decoder circuit (decoder).

  When this ECC-CODEC circuit 7 is operated as a Coder circuit, read data (that is, original memory data) from the main amplifier MA (or Data Output Register storing read data from the memory) is a SYNDROME signal. Circuit that is composed of left-right shift type feedback shift registers (FSR) S0 to S15 and an EX-OR circuit via an AND gate 71 controlled by the signal and an EX-OR (exclusive OR) circuit 72 ahead of the AND gate 71 73, and after a logical operation, the data is output to the write buffer WB (or Data Input Register) as parity data via the switch 74 controlled by the PARITY signal, and written to the memory or the parity data storage unit. Written as garbage data.

  Referring to FIGS. 7 and 8, Example 1 of the internal operation of Super Self-Refresh performed in the ECC-CODEC circuit 7 of FIG. 6 is shown. FIG. 7 shows Parity-Generation (1) (parity bit calculation) of Example 1 of the internal operation of Super Self-Refresh, and FIG. 8 shows Parity-Generation (2) of Example 1 of the internal operation of Super Self-Refresh. (Parity bit write). Memory activation (ACTV) and read operation (READ) commands are executed in synchronization with the internal clock (Internal CLK) in the device. At the same time, a Row address (XA) and a Column address (YA) are fetched, and based on these addresses, 1024 bits of memory data are read out to the main amplifier MA while incrementing the Column, and this read data is shown in FIG. After being taken into the shift register (S0 to S15) of the circulation circuit 73 and being subjected to the operation, parity data based on the original memory data is generated, and sequentially output to the write buffer WB bit by bit in the following cycle. At this time, the memory activation (ACTV) and write operation (WRIT) commands are executed in synchronization with the internal clock (Internal CLK) in the device, and at the same time, the Row address (XA) corresponding to the parity bit area and A column address (YA) is taken in, and a 16-bit parity bit is written into the memory cell while incrementing the column based on the address (corresponding to the Hamming code [1040, 1024] although not described in detail). .

  In FIG. 6, this read data is taken into the shift registers (S0 to S15) of the circulation circuit 73, and after operation is performed, parity data based on the original memory data is generated and output to the write buffer WB. .

  When this ECC-CODEC circuit 7 is operated as a Decoder circuit, the parity data is similarly sent from the main amplifier MA via the AND gate 71 controlled by the SYNDROME signal and the EX-OR circuit 72 and the shift register (S0 to S0). S15) and an EX-OR circuit, and the circuit 73 is shifted in the reverse direction to perform a logical operation and the OR circuit 75 outputs the OR logic of the outputs of the shift registers (S0 to S14). Then, from the output of the final stage shift register (S15), information on the position (LOCATION) where the memory data is defective is generated, and EX of the position (LOCATION) information and the memory data read out on the main amplifier MA is generated. The -OR logic is taken by the EX-OR circuit 76 to generate data in which the defect is corrected, and output to the write buffer WB as error-corrected data via the switch 77 controlled by the CORRECT signal.

  Referring to FIGS. 9 and 10, Example 2 of the internal operation of Super Self-Refresh performed in the ECC-CODEC circuit 7 of FIG. 6 is shown. FIG. 9 shows Correct (1) (syndrome calculation) of Example 2 of the internal operation of Super Self-Refresh, and FIG. 10 shows Correct (2) of Example 2 of the internal operation of Super Self-Refresh (error position detection Correction writing). The original memory data and parity data are read in the manner shown in FIGS. 7 and 8 in synchronization with the internal clock (Internal CLK) in the device. A reverse shift and a logical operation are performed in the circulation circuit 73 of FIG. 6 to detect a defective address. Based on the defective address, commands for memory activation (ACTV) and read operation (READ) are executed in synchronization with the internal clock (Internal CLK) in the device. Since the read data appearing on the main amplifier MA is erroneous information, the data is inverted and output to the write buffer WB. At the same time, a write command (WRIT) is generated and corrected data is stored in the memory. Writing is performed at the corresponding address. Thereafter, the same operation is repeated, and error data correction processing is performed for all bits.

  Here, the Super Self-Refresh mode / Parity Generation operation will be described in more detail with reference to FIGS. 2, 7, and 8.

  (1) After the entry of Super Self-Refresh, the input buffer circuit (COMMAND DECODE) 8 of the control logic 209 of the SDRAM 10 sets the ENCODE signal to High. At the same time, the oscillation operation of the internal synchronous clock signal ICLK is started (the flip-flop circuit in the ECC controller 6 is initialized at the stage of the SDRAM 10 startup operation).

  (2) The ECC controller 6 receives the ENCODE signal and starts an internal operation of Parity-Generation (encoding). In the following, the (1040, 1024) code (information bits 1024, parity bits 16) will be described as an example.

(3) After the INIT signal is set to HIGH (CODEC initialization mode), CODECE (CODEC enable) is set to HIGH for 16 cycles, and the shift register (S _{0 to} S ₁₅ ) in the ECC-CODEC circuit 7 is initialized. (See FIG. 6). After completion, return the CODEC mode signal to LOW.

  (4) After the SYNDROME signal is set to HIGH (CODEC syndrome mode), as shown in FIGS. 7 and 8, issuance of internal operation commands <ACTV> <READ>. Performs 1024-bit READ operation while performing X scan at 32. At this time, in accordance with the output timing of the read data, the CODECE signal is set to HIGH, and the 1024-bit data is sequentially fetched bit by bit into the CODEC while cyclically shifting the shift register. As a result, the parity bit for the 1024 information bits is calculated and the result remains in the 16-bit shift register. This is a 16-bit parity bit. After completion, return the CODEC mode signal to LOW.

  (5) After the PARITY signal is set to HIGH (CODEC parity mode), an internal operation command <ACTV> <WRIT>... <PRE> is issued, and writing to the memory cell is performed with a burst length of 16. At this time, in accordance with the output timing of the write data, the CODECE signal is set to HIGH, and 16-bit data is sequentially output bit by bit from the CODEC while cyclically shifting the shift register. At the same time, the shift register is reset sequentially (the circuit configuration saves the initialization work).

  (6) The above (4) syndrome mode and (5) parity mode are repeated to generate parity bits for all bits.

  (7) When the parity bit generation of all bits is completed, a READY signal (1 clock pulse) is output, and the operation of the ECC controller 7 is completed. In response to the READY signal, the input buffer circuit (COMMAND DECODE) 8 of the control logic 209 of the SDRAM 10 lowers the ENCODE signal to LOW and shifts to the long cycle self-refresh control.

  Here, the Super Self-Refresh mode / Correct operation will be described in more detail with reference to FIGS. 2, 9, and 10.

  (1) Upon receiving the Super Self-Refresh exit command (SSELFX), the input buffer circuit (COMMAND DECODE) 8 of the control logic 209 of the SDRAM 10 sets the DECODE signal to High. At the same time, the internal synchronous clock signal ICLK starts oscillating.

  (2) The ECC controller 6 receives the DECODE signal and starts an internal operation of Correct (decoding). In the following, the (1040, 1024) code (information bits 1024, parity bits 16) will be described as an example.

(3) After the INIT signal is set to HIGH (CODEC initialization mode), CODECE (CODEC enable) is set to HIGH for 16 cycles, and the shift register (S _{0 to} S ₁₅ ) in the ECC-CODEC circuit 7 is initialized. (See FIG. 6). After completion, return the CODEC mode signal to LOW.

  (4) After the SYNDROME signal is set to HIGH (CODEC syndrome mode), as shown in FIGS. 7 and 8, issuance of internal operation commands <ACTV> <READ>. While performing the X scan at 32, a READ operation of 16 bits of parity bits is performed following the information bits of 1024 bits (a READ operation of 1040 bits of code word is performed). At this time, in accordance with the output timing of the read data, the CODECE signal is set to HIGH, and 1040-bit data is sequentially fetched bit by bit into the CODEC while cyclically shifting the shift register. As a result, the syndrome pattern for this code word is calculated and the result remains in the 16-bit shift register. After completion, return the CODEC mode signal to LOW.

  (5) When all the syndrome patterns are 0, it is determined that there is no error in the code word, and the operation of (3) and (4) described above is performed in order to perform the syndrome calculation of the next code word. If the syndrome pattern is not all zero, it is determined that there is an error in the code word, and the operation proceeds to an error position detection operation. As shown in FIG. 6, the error detection signal ERROR becomes LOW when all the syndrome patterns are 0, and becomes HIGH otherwise, and the presence / absence of an error is transmitted to the ECC controller 7.

(6) After the CORRECT signal is set to HIGH (CODEC correct mode), as shown in FIGS. 9 and 10, the CODECE signal is set to HIGH without issuing an internal operation command, and only the (reverse) cyclic shift of the shift register is performed. Run repeatedly. However, the generation of the internal address corresponds to the (reverse) cyclic shift of the shift register, and is executed in reverse as compared with the syndrome calculation. At this time, when the first (reverse) cyclic shift corresponds to the syndrome pattern of the first bit (the last bit taken in), only the most significant bit (S ₁₅ ) is 1 and all the remaining bits are 0 , It is determined that the bit is incorrect. When “only the most significant bit (S ₁₅ ) is 1 and all the remaining bits are 0”, the (reverse) cyclic shift is repeated. If an error bit is detected, CODECE is lowered to LOW, the (reverse) cyclic shift is stopped, and an internal command <ACTV><READ><WRIT><PRE> is issued as shown in FIGS. Issued and reversed (corrected) writing is performed.

As shown in FIG. 6, when “only the most significant bit (S ₁₅ ) is 1 and all the remaining bits are 0”, the error position detection signal LOCATION becomes HIGH, and otherwise becomes LOW. In the CORRECT mode, if LOCATION is HIGH, inverted data of the read data is sent to WB.

  When this interrupt process is completed, a cyclic shift is performed again (reverse) to the end of the code word. When the above processing is completed for one codeword (1040 bits), the CODEC mode signal is returned to LOW, and the processing proceeds to (3) for processing the next codeword.

  (7) The above steps (3), (4), (5), and (6) are repeated, and error correction processing is performed on all bits. When finished, a READY signal (one clock pulse) is output, and the operation of the ECC controller 7 is finished. In response to the READY signal, the input buffer circuit (COMMAND DECODE) 8 of the control logic 209 of the SDRAM 10 lowers the DECODE signal to LOW and shifts to normal self-refresh control.

  Next, the operation of the ECC controller 6 will be described with reference to FIGS. 2, 7, 8, 9, and 10.

  In the Super Self-Refresh mode, the ECC controller 6 outputs an internal command / address to the SDRAM 10 side and a control signal to the ECC-CODEC circuit 7 in a single-phase synchronization in order to realize parity bit generation and error correction operation. . The SDRAM 10 is operated by the controller 6 alone.

  The operation of FIG. 2 has been described above, but will be further supplemented here. When the Super Self-Refresh entry command (SSELF) is generated from normal operation and the super self-refresh mode is entered, the ENCODE signal is generated and parity data is generated (processing associated with writing new data to the memory circuit). Writes the data to the parity data area of the memory (Parity Generation with Refresh) (the above operation is ENTRY-TIME). After that, super self-refresh is performed with the power off operation. In accordance with the internal signal GENOFF, most of the internal power supply (cell array section and internal power generation circuit to the peripheral circuit section) is turned off (= 0v) and enters a long-term PAUSE state (waiting when internal power supply 0v is stopped). An internal signal GSTATE is generated, indicating that the internal power supply is completely up.

  When this signal rises during the Super Self-Refresh period, that is, when the power is turned on again, Burst-Refresh operation is performed to continuously refresh all cells. However, in this refresh operation, error correction of the memory cell is not performed.

  After repeating this internal power OFF, long-term PAUSE, internal power ON, and Burst-Refresh operation any number of times (the above is Super Self-Refresh operation), the Super Self-Refresh exit command (SSELFX) is generated and Super Self-Refresh is generated. -Refresh ends and corrects memory cell data errors caused by the effect of long-term refresh stop and executes rewrite (Correct with Refresh) (the above operation is EXIT-TIME).

  Finally, exit refresh mode (Exit2) and return to normal operation.

  The effects of the above-described semiconductor integrated circuit device as the basis of the present invention will be described.

  [1] By adopting the above configuration, it is possible to avoid complicated circuit design with an optimum circuit scale.

  [2] The output register circuit makes it possible to eliminate the output delay of each block and eliminate the hazard.

  [3] A logic synthesis tool can be applied to the command / address generator by adopting a single-phase synchronous circuit and output shaping in [2] above.

  That is, the semiconductor integrated circuit device which is the basis of the present invention has an ECC controller 6, which is at least connected to the ECC-CODEC circuit 7 and the control logic 209 of the SDRAM 10.

  This control circuit uses external specifications (that is, command signals input from the outside: RAS, CAS, WE and command system address signals {not functioning as addresses for designating conventional access addresses, but for determining operation modes in a time-sharing manner). Based on the logical level of the address signal that functions as a command signal), in the same manner as the operation mode in the device is determined, an internally generated command signal {FIG. 3: IRAS-IWE} and a command system address signal {FIG. : IA (0) -IBA (1)} is generated. The signal is latched to the external clock (or the internal clock resulting from it) in single-phase synchronization (single-phase synchronization: synchronized to either the clock rise or fall), and the operation mode for Super Self-Refresh is changed. It works to generate. Preferably, the command / address signal inputted from the outside or the internally generated command / address signal is selectively fetched in the input buffer portion of the SDRAM, and the operation in the device is determined as described above. The ECC controller 6 includes at least a command generator 11, an address generator (conventional address and command system address are generated in a time division manner) 12, and output register circuits (latches or FFs) 14 to 17 in terms of circuit configuration. Consists of including.

  In this way, the ECC controller 6 is configured and connected to the ECC-CODEC circuit 7 and SDRAM (control logic) to control Super Self-Refresh. As shown in the above [1], in particular, in the part that determines the operation mode by latching the external command signal and address signal (command system address), the “command / address signal is selectively selected” provided in the conventional SDRAM. By diverting the circuit for “capturing and determining the operation in the device”, an optimum circuit scale can be realized, and complicated circuit design can be avoided.

  Also, as shown in FIG. 3 and [2] above, register circuits 13 to 17 are provided to generate output data in synchronization with the internal clock, so that the output delay of each block cannot be seen, and the internal signal Hazard caused by the delay in the period can be eliminated.

  Further, if the processing is performed by the single-phase synchronization described above, the control method is simplified, and a specific circuit configuration of the command signal generation unit and the address signal generation unit in the ECC controller 6 is obtained using a logic synthesis tool. There is an effect that can be designed.

  Referring to FIG. 11, there is shown an ECC controller 6 'used in place of the ECC controller 6 in the semiconductor integrated circuit device of FIG. Since this ECC controller 6 'does not have the register circuit 16 of the ECC controller 6 of FIG. 3, the IRAS, ICAS, and IWE signals are one cycle faster than the ECC controller of FIG. Is output. Except for this point, the ECC controller 6 'is the same as the ECC controller 6 of FIG.

  FIG. 12 is a diagram used for explaining a semiconductor integrated circuit device according to an embodiment of the present invention. The BIST (BUILT-IN SELF TEST) used in place of the ECC controller 6 in the semiconductor integrated circuit device of FIG. : Self-diagnostic test with built-in device) Controller 6 ". In the case of the semiconductor integrated circuit device according to one embodiment of the present invention, an error is substituted for the ECC-CODEC circuit 7 in the semiconductor integrated circuit device of FIG. A detection circuit (shown later) is provided, and the ECC-CODEC circuit 7 of FIG.

  This BIST controller 6 ″ is similar to the ECC controller 6 ′ of FIG. 15 and 17, but differs from the ECC controller 6 'shown in FIG. 11 in the following points.

  That is, the BIST controller 6 ″ receives a control signal (CHECK = start command signal, MODE = operation mode designation signal) 1 generated from the control logic (CONTROL LOGIC) 209 (FIG. 1) in the SDRAM 10 (FIG. 1). , BIST (BUILT-IN SELF TEST: device built-in self-diagnostic test) related signals (BISTR, BISTW, TPH, DCKE, ECKE) as operation mode signal 4 (instead of ECC-CODEC circuit 7 in FIG. 1) ) Outputs to error detection circuit and generates internal addresses IXA (0) to IXA (12), IYA (0) to IYA (8), internal bank addresses IBA (0) and IBA (1) as internal address 3 To do.

  FIG. 13 shows an operation sequence related to the BIST function of the BIST controller 6 ″ of FIG.

  Referring to FIG. 13, the SELF-TEST operation when the BIST controller 6 ″ of FIG. 12 is provided in the semiconductor integrated circuit device of FIG. 1 will be briefly described.

  In this semiconductor integrated circuit device, an input buffer circuit (COMMAND DECODE) 8 of a control logic (CONTROL LOGIC) 209 of the SDRAM 10 decodes a command from the outside by a combination of CS, WE, CAS, and RAS signals, and a BIST entry command. (BIST: Refer to the External Operation in the second line in FIG. 13) When a start (START) command signal (CHECK) is sent as a control signal 1 to the BIST controller 6 ". The start command signal (CHECK) is 13 is shown as a portion rising on the fourth line in Fig. 13. The SDRAM 10 receives an external clock (CLK: Fig. 13) when the input buffer circuit (COMMAND DECODE) 8 obtains a BIST entry command (BIST). When the BIST controller 6 ″ receives the start command signal (CHECK), the internal clock (ICLK: fifth clock in FIG. 13) is stopped. Down reference) is supplied with. The BIST controller 6 ″ is supplied with an internal clock and sends a check as an operation mode signal 4 to the error detection circuit (instead of the ECC-CODEC circuit 7 in FIG. 1).

  When the error detection circuit (instead of the ECC-CODEC circuit 7 in FIG. 1) receives the check as the operation mode signal 4, the error detection circuit starts the check operation. That is, the error detection circuit generates parity data (check bits for error detection and correction) based on the information data of each bank of the memory, and writes the generated data to the parity memory area of each bank of the memory (SELF -TEST: Refer to Internal Operation on line 11 (last line) in FIG. After this, some test disturb may be implemented.

  Subsequently, the error detection circuit reads out the parity data and detects an error in the information data based on the data and the information data stored in the memory (see SELF-TEST: Internal Operation of Last Line in FIG. 13). This error detection is performed for all the cells in the memory area.

  As described above, when the BIST command is executed, an operation for detecting an error in the memory data is performed. When an error is detected, an ERROR signal (ERROR: refer to the sixth line in FIG. 13) is generated. Although not shown, error position detection and correction operations are performed.

  When the above self test (SELF-TEST) is completed in the error detection circuit, the BIST controller 6 ″ uses the end signal (READY: see the 10th line in FIG. 13) as an internal command 2 as an input buffer circuit (COMMAND DECODE). 8 is output.

  When the input buffer circuit (COMMAND DECODE) 8 receives and decodes the end signal (READY) as the internal command 2, the input buffer circuit (COMMAND DECODE) 8 stops supplying the start command signal (CHECK: the fourth line in FIG. 13) to the BIST controller 6 ″. The BIST controller 6 ″ also stops supplying the internal clock (ICLK: the fifth line in FIG. 13).

  As a result, the SELF-TEST TIME is exited, and the process is terminated by an external BIST exit command (BISTX: see the second line External Operation in FIG. 13).

  Here, the input / output signals of the BIST controller 6 ″ of FIG. 12 will be described below.

  BISTR, BISTW, TPH, DCKE, ECKE ... Operation mode signals for error detection circuit (an example is shown in Fig. 14).

            BISTR: READ mode. When this signal is HIGH, MA output data is taken in and comparison (error determination) with an expected value according to the operation timing (internal address) becomes possible.

            BISTW: WRITE mode. When this signal is HIGH, input data (expected value) corresponding to the operation timing (internal address) is output to WB, and writing to the memory cell is performed.

            TPH: 0/1 switching of expected value data (write data, read data). For example, when it is LOW, it becomes 0 data.

            DCKE: When this signal is HIGH, DCLK is generated from ICLK and the expected value is sent to the error decision circuit.

            ECKE: When this signal is HIGH, ECLK is generated from ICLK, and the judgment result is recorded in the error recording circuit (if ECLK always operates, the wrong judgment result is taken in).

  IXA (0) to IXA (12), IYA (0) to IYA (8), IBA (0), IBA (1) ... Internal address (each output X / Y), internal bank address.

            An address corresponding to the timing of the expected value WRITE / READ operation is output.

  Referring to FIG. 14, it is a diagram used for explaining the semiconductor integrated circuit device according to the above embodiment of the present invention, and is an error detection circuit 7 ′ that can be used in place of the ECC-CODEC circuit 7 in the semiconductor integrated circuit device of FIG. It is shown.

  The error detection circuit 7 ′ includes a data scrambler 21 having an EX-OR circuit, a two-stage clock (CL) adjusting flip-flop circuit 23 connected to the output of the data scrambler 21, and an EX-OR circuit. And an error recording circuit 24 having a two-stage flip-flop circuit.

  The error determination circuit 22 compares the read data {DOUT (I)} from the memory with error-free data output through two stages of the flip-flop circuit 23. When an error is detected, the error determination circuit 22 becomes H level. A signal is output. This signal is further passed through two stages of flip-flop circuits in the error recording circuit 24 and is held at the H level in a DC manner, and is output through the switch as an error state signal ESTATE (see the ninth line in FIG. 13).

  FIG. 15 shows the semiconductor integrated circuit device of FIG. 1 in which the error recording circuit 24 described above is added to the ECC-CODEC circuit 7, and in particular, the H level output of the ERROR signal is held in a DC manner. . Since ECC-CODEC performs an error detection operation in the correct operation, this is a circuit in which this is applied to the BIST operation. ECLK performs a clocking operation of one clock in an error determination cycle (a cycle in which syndrome calculation for one code word is finished and an error determination is output), and the error recording circuit holds the ERROR signal as an ETRIG signal. When the ETRIG signal transitions from LOW to HIGH, the error recording signal ESTATE is set to HIGH, and the state is maintained unless the RESET signal is input. That is, if there is an error in even one bit in the data read by the correct operation, the error recording signal ESTATE becomes HIGH and is held. When the BIST operation ends, the result ESTATE (see the ninth line in FIG. 13) is read from the error recording circuit 24 by a BIST exit command (BISTX: see the second line in FIG. 13) from the outside.

  FIG. 16 shows a circuit applied to the BIST operation by adding an error detection circuit to the ECC controller 6 (FIG. 3) or the ECC controller 6 '(FIG. 11). When the ECC controller 6 or 6 'shown in FIG. 16 finds an error, the ECC controller 6 or 6' shifts to an error position detection operation, and the CORRECT signal output to the ECC-CODEC circuit 7 becomes H level. A D-flip flop circuit 25 is added to hold it in a DC manner. The D-flip flop circuit 25 maintains the H level in a DC manner, and the matching between the ECC-CODEC circuit 7 and the ECC controller 6 'accompanying the BIST operation is improved.

  That is, the CORRECT signal of the ECC controller 6 'becomes HIGH only when there is an error as a result of the Syndrome calculation, and thereafter, the operation shifts to detection and correction of the error position. This is an example of detecting whether or not the CORRECT signal has become HIGH even once using the characteristic of becoming HIGH only when there is an error. In this case, it is not necessary to change the ECC-CODEC circuit 7 side.

  With the above configuration, the BIST exit command (BISTX: refer to the second line in Fig. 13) can be applied to the BIST circuit by using the memory data error detection / correction function provided in the Super Self-Refresh function. Is executed, an operation for detecting an error in the memory data is performed by the self-test (SELF-TEST: see the last line in FIG. 13). When an error is detected, an ERROR signal is generated and not shown. However, error position detection and correction operations can be performed, and a self-diagnosis test can be performed.

  Here, with reference to FIG. 1, the SDRAM 10 is an example of 64 Mb SDRAM, x8 (word configuration). The X address (including bank address) has a total of 14 bits, and the Y address has a total of 9 bits. A parity bit storage area is expanded in the Y direction of each bank. Because of the access to the parity bit storage area, 9 bits are not sufficient for the Y address, and 10 (= 9 + 1) bits. In accordance with this, a Y address register, a Y address wiring, a Y (COLUMN) decoder, a sense amplifier (SENSE AMPLIFIERS) and the like are added.

  In the ECC-CODEC circuit 7, ECC-CODEC is arranged for each IO wiring. In this example, the internal I / O is 8 bits, and eight CODECs are arranged in the ECC-CODEC circuit 7. When there is a solid defect in the parity bit, redundant relief is performed in the same manner as the normal bit.

  The location of the ECC-CODEC circuit 7 may be anywhere on the internal IO bus, and there is a degree of freedom in layout and the effect of suppressing the chip size overhead.

  Referring to FIG. 17, there is shown another semiconductor integrated circuit device on which the present invention is based. In this semiconductor integrated circuit device, the SDRAM 10 is an example of 256 Mb SDRAM, × 16 (word configuration). The X address (including bank address) has a total of 15 bits and the Y address has a total of 9 bits. A parity bit storage area is expanded in the X direction of each bank. Due to access to the parity bit storage area, 15 bits are not sufficient for the X address, and 16 bits (= 15 + 1). In accordance with this, an X address register, an X address wiring, an X (ROW) decoder, a word driver, and the like are added.

  The refresh cycle is normally 8192 cycles, but is 8192 + P cycles. For example, when the (1040, 1024) code is applied, the parity bit is 4M bits (8192 × 128 × 4 banks), and the refresh cycle is 8320 (8192 + 128) cycles.

  In the ECC-CODEC circuit 7, ECC-CODEC is arranged for each IO wiring. In this example, the internal I / O is 16 bits, and 16 CODECs are arranged in the ECC-CODEC circuit 7. The location of the ECC-CODEC circuit 7 may be anywhere on the internal IO bus, and there is a degree of freedom in layout and the effect of suppressing the chip size overhead.

  Referring to FIG. 18, still another semiconductor integrated circuit device on which the present invention is based is shown. This semiconductor integrated circuit device is an example of 256 Mb SDRAM, × 16 (word configuration) as in FIG. 17, but is an example in which the ECC-CODEC circuit 7 is arranged for each I / O of each memory bank. In this case, 16 ECC-CODECs are arranged in each ECC-CODEC circuit 7. That is, a total of 64 ECC-CODECs, 16 units / bank, are arranged, which is disadvantageous in terms of chip size overhead. There is no degree of freedom in layout, and ECC-CODEC must be arranged near each MA (main amplifier) and WB (write buffer).

  However, by performing simultaneous memory access for four banks, there is a merit that processing of encoding (Parity-Generation) and decoding (Correct) operations can be performed in ¼ time compared to FIG. In terms of current consumption for encoding (Parity-Generation) and decoding (Correct) operations, memory access at the same time for four banks is more than doubled, which is a disadvantage, but which one to choose is a trade-off with processing time. Determined by. The speed of the internal clock may be adjusted. The encoding (Parity-Generation) processing time is the ENTRY time to the Super Self-Refresh mode, but this time is not visible to the user. Even if an EXIT instruction is input during processing, the data is not corrupted, so it can be shifted to the normal state without doing anything. That is, since it is not necessary to shorten it, memory access for each bank may be performed.

  On the contrary, the processing time of decoding (Correct) is the EXIT time of Super Self-Refresh mode, and this time appears to the user. Of course, if the broken data is not corrected, the normal state cannot be restored, and the user must wait until the processing is completed. Therefore, the shorter the decoding time, the better, and it is worth performing memory access for four banks simultaneously.

  Although this configuration is disadvantageous in terms of chip size, it has the flexibility to select the exit time and current consumption (in actual use, the waiting time in the data holding state is overwhelmingly long, so ENTRY / EXIT The current consumption of the battery does not affect the battery life.)

  Referring to FIG. 19, Example 1 (burst length 1, no error) of the SELF-TEST operation of the BIST controller 6 ″ of FIG. 12 is shown. Referring to FIG. 20, the BIST controller 6 ″ of FIG. Example 2 of the SELF-TEST operation (burst operation, error, reading of the result) is shown. Here, with reference to FIGS. 19 and 20, the operation of the BIST controller 6 ″ in FIG. 12 will be supplementarily described.

  When the input buffer circuit (COMMAND DECODE) 8 of the control logic (CONTROL LOGIC) 209 of the SDRAM 10 in FIG. 1 receives the SELF-TEST entry command (BIST), the activation signal CHECK is set to HIGH. The BIST controller 6 ″ in FIG. 12 responds to the start signal CHECK HIGH and accesses all bits while outputting internal operation commands, addresses, and expected values as shown in FIGS. 19 and 20. The test contents are selected by the MODE signal entering the BIST controller 6 ″, and the address pattern and data pattern such as X-MARCHING (10N) are determined. In FIG. 14, the expected value to be issued is selected as 0/1 (LOW / HIGH) by the data scrambler 21 and TPH, and is matched with the timing of read data by DCLK (so that it can cope with CAS latency). )

  In FIG. 14, the read data is compared with an expected value (Expectation-Data → Comparion-Data), and the comparison result ERROR is recorded in the error recording circuit 24 including a flip-flop circuit by ECLK. Further, the error detection record continues to be held unless it is erased by the RESET signal.

  The input buffer circuit (COMMAND DECODE) 8 of the control logic (CONTROL LOGIC) 209 of the SDRAM 10 in FIG. 1 outputs a pulse of the RESET signal when the series of SELF-TEST operations is completed, and lowers the start signal CHECK to LOW. Commands can be accepted.

  When the input buffer circuit (COMMAND DECODE) 8 of the control logic (CONTROL LOGIC) 209 of the SDRAM 10 in FIG. 1 receives the SELF-TEST exit command (BISTX in FIG. 13), the COMOPARE signal becomes HIGH, and in FIG. Is output from the output buffer. In this example, the error is HIGH and the error is LOW.

  Needless to say, the effect of BIST as described above is that a screening test can be performed with an inexpensive apparatus, and the test cost can be greatly reduced.

  In addition to FIG. 19, in the case of a WRITE operation, BISTW is set to HIGH and the calculated expected value (Expectation-Data) is sent to the WB (write buffer). In the case of a READ operation, BISTR is set to HIGH, and the read data is The error detection circuit takes it in and compares it with the expected value, but BISTW and BISTR are the same signal, and during SELF-TEST, even if HIGH, there is no problem in operation.

  The read data is compared with the expected value, but it matches the expected value and no error is recorded.

  As a supplement to FIG. 20, the expected value is issued in accordance with the <READ> command, and the timing adjustment with the read data is performed by DCLK. The comparison result ERROR with the read data is taken in by ECLK and becomes an ETRIG signal. If the ETRIG signal becomes HIGH even once, the error detection record ESTATE becomes HIGH and is not erased unless it is reset. In this example, since there is data different from the expected value at the fourth bit of the read data, ESTATE is recorded as HIGH (with an error). Finally, the COMPARE signal becomes HIGH and the ESTATE is read out.

  Referring to FIGS. 21 and 22, a specific example of the ECC-CODEC circuit 7 shown in FIG. 6 is shown. The ECC-CODEC circuit 7 shown in FIGS. 21 and 22 includes the circulation circuit 73 and the EX-OR circuit 76 described in the ECC-CODEC circuit 7 of FIG. In the ECC-CODEC circuit 7 shown in FIGS. 21 and 22, three stages of register circuits 78 are inserted in the output path of the error position detection signal (LOCATION).

  23A, 23B, and 23C, the left and right shift type shift registers 731, 732, and 733 in the circulation circuit 73 of the ECC-CODEC circuit 7 shown in FIG. Is shown in

  24 specifically shows the EX-OR circuit 734 in the circulation circuit 73 of the ECC-CODEC circuit 7 shown in FIG.

  In the ECC-CODEC circuit 7 shown in FIGS. 21 and 22, the ECC controller 6 (FIG. 3) is a single-phase synchronous circuit using an internal clock ICLK, a register circuit is inserted in the output, and an error position By inserting one stage of the register circuit 78 in the output path of the detection signal (LOCATION), the response to the real-time error position detection signal (L0 in FIG. 22) is delayed by 3 clocks. Therefore, it is necessary to store the detection result three clocks before by the three-stage register circuit 78 and perform an error correction operation.

  Referring to FIG. 25, a circuit (CODEC-CLK GENERATOR circuit) for supplying clocks (CCLK, CCLKB, CCLK2, CCLK2B) to the ECC-CODEC circuit 7 shown in FIGS. 21 and 22 is shown. The circuit shown in FIG. 25 has a delay circuit DL1 composed of two stages of inverters and a delay circuit DL2 composed of four stages of inverters, and delays the clock operations of CCLK and CCLKB and the clock operations of CCLK2 and CCLK2B. The operation margin of the left / right shift type register circuit shown in FIG. 23 is ensured. This operation margin will be described with reference to FIG. The left and right shift type register circuit performs a shift operation by using control clocks CCLK2 and CCLK2B for opening and closing the left and right two latch circuits and control clocks CCLK and CCLKB for copying data of the latch circuit to the adjacent latch circuit. First, when CCLK first transitions from LOW to HIGH, the data in the left and right latch circuits become the same. If CCLK2 transitions from LOW to HIGH after a delay, the result is not affected. The next time CCLK returns from HIGH to LOW, if CCLK2 returns from LOW to HIGH with a delay, the right latch circuit is closed and the left latch circuit is open, so the data is latched from the right latch circuit to the left of the next shift register. The data is copied to the circuit and the data flows from right to left. In other words, there is no forward shift. If CCLK2 returns from LOW to HIGH first, the right latch circuit is open and the left latch circuit is closed, so the data is copied from the left latch circuit of the adjacent shift register to the right latch circuit, and forward shift is performed. Can do. In the reverse shift operation, CCLK and CCLKB and CCLK2 and CCLK2B are operated in reverse phase, but similarly, the clock operation of CCLK2 and CCLK2B must be performed first.

  In FIG. 25, CODECE (i) is a CODEC enable signal transmitted from the ECC controller 6 (FIG. 3) for each bank. Note that i means a bank address (i = 0, 1, 2, 3).

  BAE (j) is a bank enable signal transmitted from the input buffer circuit (COMMAND DECODE) 8 of the control logic (CONTROL LOGIC) 209 of the SDRAM 10 of FIG. 1 to each bank. Corresponding to the PASR mode, the bank that can be activated is HIGH. Here, j means a bank address. (j = 0,1,2,3).

  For example, when the PASR mode is 4 banks (full bank, default), all BAE (0) to BAE (3) are HIGH. If there are two banks, only BAE (0) and BAE (1) are HIGH. When BAE (j) is LOW, CCLK to the ECC-CODEC circuit 7 (FIGS. 21 and 22) is not supplied.

  This circuit generates four clock signals (CLK, CLKB, CLK2, CLK2B) to be supplied from the internal clock ICLK to the ECC-CODEC circuit 7 (FIG. 21 and FIG. 22), and sends them to a plurality of ECC-CODEC circuits 7. Output. In the SYNDROME mode, CLK and CLK2 operate in the same phase, but in the CORRECT mode, CLK and CLK2 operate in the opposite phase. The ECC-CODEC circuit 7 (FIGS. 21 and 22) enables forward / reverse operation of the shift register by switching the in-phase / reverse phase operation.

  Referring to FIG. 26, another Super Self-Refresh operation sequence (Entry / Exit Scheme) of the semiconductor integrated circuit device shown in FIG. 1 is shown.

  In the entry / exit method of the Super Self-Refresh operation sequence shown in FIG. 2, a command for “Super Self-Refresh” (Super Self-Refresh entry command (SSELF) and Super Self-Refresh exit command (SSELFX)) is not a general method such as putting it in the input buffer circuit (COMMAND DECODE) 8 of the control logic (CONTROL LOGIC) 209 of the SDRAM 10 in FIG. In other words, the user must develop a control method (chip set or software) different from the general-purpose SDRAM, and sacrifices in terms of development cost and period in order to use the Super Self-Refresh mode.

  On the other hand, the entry / exit system shown in FIG. 26 is an example in which a user of a general-purpose SDRAM can cope. There is no command for “Super Self-Refresh”, and the normal Self-Refresh command (Self-Refresh entry command (SELF: see External Operation in the third line in FIG. 26)) and Self-Refresh exit command (SELFX: FIG. 26). (See External Operation in the third line))), and the Entry / Exit method is basically the same as the Self-Refresh command.

  However, after the Exit command (SELFX) is input, the distributed refresh operation that is generally performed during the defined EXIT-TIME (time until the correct operation ends) (in the case of 256MbSDRAM, the refresh cycle is 8k cycles (8192 cycles)) Therefore, in order to satisfy the refresh standard of 64ms, only the <REF> command is input at a cycle of about 7.8μsec). Since the internal command issued from the ECC controller is accepted during the correct operation, the <REF> command input from the outside is ignored. When the correct operation is completed, the Idle state is restored, and the refresh operation is performed in response to the <REF> command input from the outside. As a result, the correct operation time (EXIT-TIME), which fluctuates due to the error rate of the pause failure that occurs in the long-cycle refresh operation, can be absorbed, and the normal memory access operation can be performed while maintaining the corrected data.

  In the Exit method shown in FIG. 2, since the time required for the correct operation varies and is not fixed, the self-refresh mode is automatically shifted to after the correct operation ends. The self-refresh mode is the distributed refresh operation described above. Is merely an operation that is automatically performed internally, and FIG. 26 is effectively the same. Which method to select depends on the user.

  EXIT-TIME also exists in the case of normal Self-Refresh, and the time is about 100 ns. In this case, the time until the end of the correct operation is about several hundred ms. In general, when an SDRAM is used, a distributed refresh operation is always performed, and a desired operation command is input between the <REF> commands. That is, although the Exit method of FIG. 26 has a long EXIT-TIME, it is not a special operation and is basically the same as normal Self-Refresh.

  The Entry / Exit command may be the same as the Self-Refresh command, and the meaning of the command may be switched between “Super Self-Refresh” and normal Self-Refresh depending on the MRS or EMRS setting.

  Although it has been written that “the time required for correct operation varies”, in the case of the method of FIGS. 2 and 26, since the internally generated ICLK is operated as a synchronous clock, there is a manufacturing variation in the cycle, and the ENTRY time ( The time required for Parity-Genetation is not exactly visible to the outside. Although not shown in the figure, during the Entry / Exit period, CLK may be received from the outside and the Entry / Exit time may be defined by the number of cycles.

  State transition diagrams corresponding to the methods of FIGS. 2 and 26 are shown in FIGS. These are examples in which Super Self-Refresh mode is added based on the state transition diagram of Mobile RAM.

  The state transition diagram of FIG. 27 corresponds to the method of FIG. 2, and when the user inputs a Super Self-Refresh Exit (SSR EXIT), it shifts to the Correct state (ERROR CORRECTION) and automatically when it is finished. Transition to Self-Refresh state. Here, the Exit is completed only when the Self-Refresh Exit (SR EXIT) is input.

  The state transition diagram of FIG. 28 corresponds to the method of FIG. 26, and as a command for “Super Self-Refresh”, Super Self-Refresh Entry (SSR ENTRY) and Super Self-Refresh Exit (SSR EXIT) in FIG. Instead, Self-Refresh Entry (SR ENTRY) and Self-Refresh Exit (SR EXIT) are used. When the user inputs Self-Refresh Exit (SR EXIT), the state shifts to the Correct state (ERROR CORRECTION), and when it is finished, the exit is simply completed.

  As in the state transition diagram of FIG. 27, the state transition diagram of FIG. 29 transitions to the correct state (ERROR CORRECTION) when the user inputs a Super Self-Refresh Exit (SSR EXIT). When the correct state (ERROR CORRECTION) ends, the exit is simply completed.

  Referring to FIG. 30, the connection relationship between the ECC controller 6 and the ECC-CODEC circuit 7 configured as shown in FIG. 18 is shown in detail. The ECC controller 6 commonly supplies CODEC-MODE signals (INIT, PARITY, SYNDROME, CORRECT, CODECE) to 64 ECC-CODECs (FIGS. 21 and 22). From the ICLK-GENERATOR, the ECC controller 6 ( Alternatively, ICLK (internal synchronization clock signal) is commonly supplied to the control logic (CONTROL LOGIC) 209 of the SDRAM. The ICLK-GENERATOR receives an oscillation start command (ICLKON is HIGH) from the control logic (CONTROL LOGIC) 209 of the SDRAM and starts oscillation. On the contrary, the oscillation is stopped by receiving the oscillation stop command (ICLKON is LOW). The clock signal to the ECC-CODEC is converted into four synchronous clocks (CCLK, CCLKB, CCLK2, CCLK2B) through the CCLK-GENERATOR (FIG. 25), and is supplied in common to four ECC-CODECs. That is, since 16 ECC-CODECs per bank, four CCLK-GENERATORs (FIG. 25) are arranged. The clock signal to the ECC-CODEC is output when the CODECE (codec enable) signal is HIGH, but there are four clock signals for each bank. The ECC controller 6 controls each as necessary, so that each bank unit can control each ECC-CODEC. Operation is also possible. MA (main amplifier) output has two systems, a normal path and an output path to ECC-CODEC, and can be switched according to the normal mode and the super self-refresh mode. The data read in the normal mode passes through the common I / O-BUS via the normal path, and is buffered to the DATA-OUTPUT-REGISTER and output externally. Data read out in the Parity-Generation or Correct operation in Super Self-Refresh mode passes through the output path to ECC-CODEC, is buffered in the register circuit (FF in FIG. 30), and then shifts in ECC-CODEC It is sequentially taken into the register. WB (write buffer) also has two systems, a normal path and an input path from ECC-CODEC, which are switched according to a normal mode and a super self-refresh mode. In normal mode, externally input write data is buffered in DATA-INPUT-REGISTER, passed through the common I / O-BUS, and input from the normal path to WB (write buffer). In Parity-Generation in the Super Self-Refresh mode, the parity bits output from the ECC-CODEC are input to the WB (write buffer) through the input path from the ECC-CODEC. Although not shown in FIGS. 30 and 31, as in the normal mode, the parity bit may be input after being buffered in the register circuit. From the ECC-CODEC, the error position detection signal LOCATION and the error detection signal ERROR are supplied to the ECC controller 6, but the output of the 16 ECC-CODECs in one bank is ORed, and finally the error position for each bank. Detection signal LOCATION and error detection signal ERROR. The position detection signal LOCATION is simply ORed with four banks of LOCATION signals, and one LOCATION signal is input to the ECC controller 6, but the error detection signal ERROR is activated according to the PASR (partial self-refresh) mode. After ANDing with the bank enable signal BAE (j) to be converted, it becomes one ERROR signal and is input to the ECC controller 6. For example, when the PASR mode is 2 banks, the bank enable signals BAE (0) and BAE (1) are HIGH, otherwise, the error detection signal ERROR is ORed only for the ERROR signals from banks 0 and 1. Input to the ECC controller 6. As a result, since the ERROR signals of the banks 2 and 3 outside the operation guarantee can be ignored, the ECC controller 6 can omit the useless internal command issue and operation of the correct operation.

  Next, with reference to FIG. 32 and FIG. 33, it supplements regarding the Correct operation | movement of FIG.9 and FIG.10. FIGS. 32 and 33 are diagrams from syndrome calculation to error position detection in the Super Self-Refresh operation when the ECC controller 6 ′ shown in FIG. 11 and the specific ECC-CODEC circuit 7 shown in FIGS. 21 and 22 are used. The left half and the right half of the detailed operation (corresponding to the Correct operation in FIGS. 9 and 10) are shown.

  Since the output of the ECC controller 6 ′ is performed via the register circuits 14, 15, and 17, the outputs of the command generator 11 and the address generator 12 are output with a delay of one cycle by the register circuits 14, 15, and 17. . First, in the syndrome calculation shown in FIG. 9, since the data flow is one direction from the ECC controller to the control logic and the ECC-CODEC circuit, the output of the ECC controller is one cycle from the output of the command generator and the address generator. It is the same as FIG. 9 only with a delay. The four clocks CCLK, CCLKB, CCLK2, and CCLK2B supplied from the clock supply circuit (CCLK-GENERATOR) in FIG. 25 are delayed by the delay circuit DL1 (FIG. 25) from the clocks CCLK and CCLK2B. The operation margin is set to ensure the operation margin of the cyclic shift operation of the ECC-CODEC circuit. If this delay relationship is reversed, the shift register destroys the data. The command generator receives the error detection signal ERROR (ERROR Detect) after completing the issuance of the syndrome calculation command, but the margin for the delay time to reach the ECC controller through OR processing from 64 ECC-CODEC circuit outputs Wait with. In the example of FIGS. 32 and 33, ERROR is accepted in the third cycle after the last <PRE> command is issued. When ERROR is HIGH, the ECC controller proceeds to an error position detection operation as follows. First, the CORRECT signal is raised to HIGH, and CCLK and CCLKB are inverted and output regardless of ICLK. With this operation, the data stored in the shift register circuit (FIG. 23) is copied from the data stored in the left latch circuit to the right latch circuit, and the data in the left and right latch circuits are the same. In the next cycle, the SYNDROME signal is lowered to LOW, and the four clocks CCLK, CCLKB, CCLK2, and CCLK2B are inverted, and at the same time, the CORRECTB is inverted to perform one-bit backward / cyclic shift. Again, the CCLK and CCLKB clocks are operated slower than the CCLK2 and CCLK2B clocks to ensure an operating margin for the shift operation. This is ensured by the delay circuit DL2 of the clock supply circuit (CCLK-GENERATOR) of FIG. This delay relationship is always maintained by the delay circuit DL1 of the clock supply circuit (CCLK-GENERATOR) in FIG. 25 even in the subsequent clocking operation. Further, the ECC-CODEC circuit changes from the SYNDROME mode to the CORECT mode by controlling the SYNDROME and CORRECT signals. CCLK and CCLKB and CCLK2 and CCLK2B are reverse phase clocks, and reverse and cyclic shift operations are possible. By this 1-bit shift, a syndrome pattern corresponding to the bit read from the memory cell at the end of the syndrome operation appears in a 16-bit shift register in the ECC-CODEC. Here, when only the most significant bit is HIGH and the other bits are LOW, the error position detection signal LOCATION becomes HIGH, and the ECC controller detects that the bit is in error. In order to determine the error of the subsequent read bit, the CODECE (codec enable) signal is set to HIGH and 4 clocks CCLK, CCLKB, CCLK2, and CCLK2B are supplied from the clock supply circuit (CCLK-GENERATOR) in FIG. The error determination of the subsequent read bit is performed. In parallel with this, the address generator reverses the internal address, but the address backward starts three cycles after the CODECE (codec enable) signal is set to HIGH. When the error position detection signal LOCATION becomes HIGH as a result of the backward shift and cyclic shift of the subsequent shift register, the ECC controller receives it, lowers the CODECE signal to LOW, and stops the operation of the ECC-CODEC circuit. A cyclic shift is performed in the cycle of receiving the LOCATION signal. Furthermore, since the output of the command generator is output via the register circuit, the stop of the ECC-CODEC circuit is delayed by one cycle. Further, since the error position detection signal LOCATION is also output through the register, it is output with a delay of one cycle from the ECC-CODEC circuit, and the determination result one bit before is seen. That is, error position detection is delayed by three cycles. Therefore, the ECC-CODEC circuit (FIGS. 21 and 22) has three registers for storing the LOCATION signal and stores up to the value (L3) three cycles before, and the rewrite data is inverted by the value (FIG. 22). 76). This is why the address generation unit delays the internal address backward operation by three cycles. When the ECC controller receives HIGH of the error position detection signal LOCATION, the ECC-CODEC circuit stops the backward movement of the address generation unit, and issues an internal command for rewriting the error bit, but by the delay control, The error judgment and address of the bit match, and correct error correction operation becomes possible. The ECC controller finishes issuing the internal command and starts the backward / cyclic shift of the ECC-CODEC circuit and the backward of the address generation unit for the next error position detection operation. However, the delay relationship of the three cycles is maintained. Be drunk.

1 is a block diagram of a semiconductor integrated circuit device on which the present invention is based. FIG. 2 is a waveform diagram showing a Super Self-Refresh operation sequence (Entry / Exit Scheme) of the semiconductor integrated circuit device shown in FIG. 1. FIG. 2 is a block diagram of an ECC controller of the semiconductor integrated circuit device shown in FIG. 1. (A) is a figure which shows FF (flip-flop) circuit used as each of the register circuit of the ECC controller shown in FIG. 3, (B) is a figure which shows the internal structure of the FF circuit. FIG. 5 is a waveform diagram illustrating an operation example of the FF circuit illustrated in FIG. 4. FIG. 2 is a block diagram of an ECC-CODEC circuit of the semiconductor integrated circuit device shown in FIG. 1. It is the figure which showed Parity-Generation (1) (parity bit calculation) of the example 1 of Super Self-Refresh internal operation performed in the ECC-CODEC circuit shown in FIG. FIG. 7 is a diagram showing Parity-Generation (2) (parity bit writing) of Example 1 of Super Self-Refresh internal operation performed in the ECC-CODEC circuit shown in FIG. 6. FIG. 7 is a diagram showing Correct (1) (syndrome calculation) of Example 2 of the internal operation of Super Self-Refresh performed in the ECC-CODEC circuit shown in FIG. 6. FIG. 7 is a diagram showing Correct (2) (error position detection / correction writing) in Example 2 of the internal operation of Super Self-Refresh performed in the ECC-CODEC circuit shown in FIG. 6. 2 is a block diagram showing an ECC controller 6 'used in place of the ECC controller 6 in the semiconductor integrated circuit device of FIG. FIG. 2 is a block diagram showing a BIST controller 6 ″ used in place of the ECC controller 6 in the semiconductor integrated circuit device of FIG. 1 for use in explaining a semiconductor integrated circuit device according to an embodiment of the present invention. It is. 13 shows an operation sequence related to the BIST function of the BIST controller 6 ″ shown in FIG. FIG. 2 is a diagram used for explaining the semiconductor integrated circuit device according to the embodiment of the present invention, and showing an error detection circuit 7 ′ that can be used in place of the ECC-CODEC circuit 7 in the semiconductor integrated circuit device of FIG. 1. . 2 is a block diagram showing an example in which an error recording circuit 24 is added to the ECC-CODEC circuit 7 in the semiconductor integrated circuit device of FIG. It is the figure which showed the example in which the error detection circuit was added to the ECC controller 6 or the ECC controller 6 '. It is a block diagram of another semiconductor integrated circuit device on which the present invention is based. It is a block diagram of still another semiconductor integrated circuit device on which the present invention is based. FIG. 13 is a diagram showing an example 1 (burst length 1, no error) of the SELF-TEST operation of the BIST controller 6 ″ of FIG. FIG. 13 is a diagram illustrating a SELF-TEST operation example 2 (burst operation, error present, result reading) of the BIST controller 6 ″ of FIG. 12; It is the figure which showed the left half of the specific example of the ECC-CODEC circuit 7 shown by FIG. It is the figure which showed the right half of the specific example of the ECC-CODEC circuit 7 shown by FIG. FIG. 23 is a diagram specifically showing left and right shift type shift registers 731, 732, and 733 in the circulation circuit 73 of the ECC-CODEC circuit 7 shown in FIG. 22. FIG. 23 is a diagram specifically showing an EX-OR circuit 734 in the circulation circuit 73 of the ECC-CODEC circuit 7 shown in FIG. 22. FIG. 23 is a diagram showing a circuit for supplying a clock to the ECC-CODEC circuit 7 shown in FIGS. 21 and 22. FIG. 6 is a waveform diagram showing another Super Self-Refresh operation sequence (Entry / Exit Scheme) of the semiconductor integrated circuit device shown in FIG. 1. It is the figure which showed the state transition diagram corresponding to the system of FIG. It is the figure which showed the state transition diagram corresponding to the system of FIG. It is the figure which showed the same state transition diagram as the state transition diagram of FIG. It is the figure which showed the left half of the detail of the connection relation of the ECC controller 6 of the semiconductor integrated circuit device shown in FIG. 18, ECC-CODEC circuit 7, etc. FIG. FIG. 19 is a diagram showing the right half of the details of the connection relationship between the ECC controller 6 and the ECC-CODEC circuit 7 of the semiconductor integrated circuit device shown in FIG. 18. The left side of the detailed operation from the syndrome calculation to the error position detection in the Super Self-Refresh operation when the specific ECC controller 6 ′ shown in FIG. 11 and the specific ECC-CODEC circuit 7 shown in FIGS. 21 and 22 are used. It is a figure which shows a half. The right side of the detailed operation from syndrome calculation to error position detection in the Super Self-Refresh operation when the specific ECC controller 6 ′ shown in FIG. 11 and the specific ECC-CODEC circuit 7 shown in FIGS. 21 and 22 are used. It is a figure which shows a half.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Control signal 2 Internal command 3 Internal address 4 Operation mode signal 5 Error detection / error position detection signal 6 ECC controller 6 'ECC controller 6 "BIST controller 7 ECC-CODEC circuit 7' Error detection circuit 8 Input buffer circuit 9 Self Refresh control circuit 10 SDRAM
11 Command Generator 12 Address Generator 13 Register Circuit 14 Register Circuit 15 Register Circuit 16 Register Circuit 17 Register Circuit 209 Control Logic

Claims (5)

A semiconductor integrated circuit device having a dynamic RAM, wherein the dynamic RAM includes a memory array, a RAM control unit, an error detection circuit, and a BIST (BUILT-IN SELF TEST) controller. In the semiconductor integrated circuit device having a command decoding unit that receives an external command from the outside of the dynamic RAM and decodes the external command,
The command decoding unit can also accept internal commands generated by the BIST controller, and can also decode the internal commands.
The BIST controller has a command generation unit and an address generation unit,
When the command decode unit decodes the BIST entry command as the external command, the command decode unit sends a start command signal indicating a check to the BIST controller,
Upon receiving the activation command signal, the command generation unit of the BIST controller sends an operation mode signal indicating the check to the error detection circuit, and also transmits the operation mode signal to the address generation unit of the BIST controller. Sequentially generate an address corresponding to the operation timing of and supply to the memory array,
When the error detection circuit receives the operation mode signal, the error detection circuit generates write data in accordance with sequentially generated addresses, writes the generated write data to a predetermined area or all areas of the memory array, and then sequentially generates the write data. Expected value data is generated according to the address, compared with the information data read from the memory array, an error in the information data is detected, and when the error detection is completed, the BIST controller uses the end signal as the internal command Output to command decode section
The semiconductor integrated circuit device, wherein when the command decoding unit receives and decodes the end signal as the internal command, the transmission of the operation mode signal is stopped. The semiconductor integrated circuit device according to claim 1,
The semiconductor integrated circuit device according to claim 1, wherein the BIST entry command is input to the dynamic RAM by a user. The semiconductor integrated circuit device according to claim 1,
The BIST controller further includes a register circuit, and holds the result of the error detection in the register circuit.
2. The semiconductor integrated circuit device according to claim 1, wherein when the command decode unit receives a read command as the external command, the BIST controller causes the register circuit to output the error detection result externally. The semiconductor integrated circuit device according to claim 1,
The error detection circuit further includes a register circuit, and holds an error detection signal of the error detection circuit as an error detection result in the register circuit,
The semiconductor integrated circuit device, wherein the error detection circuit causes the register circuit to output the error detection result externally when the command decoding unit receives a read command as the external command. The semiconductor integrated circuit device according to claim 1,
The BIST controller further includes a register circuit, and the register circuit holds an error position detection command of the BIST controller as an error detection result.
The semiconductor integrated circuit device, wherein the BIST controller causes the register circuit to output the error detection result externally when the command decode unit receives a read command as the external command.

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