JP2015207333A - Semiconductor device and information processing system including the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a malfunction of a data bus inversion function.SOLUTION: A semiconductor device includes: a data bus inversion circuit 70 that inverts read data DQ according to the read data DQ which is read from a memory cell array 11; a data input/output terminal 21 that outputs, if a first operation mode is specified, the read data DQ which is output from the data bus inversion circuit 70 and that outputs, if a second operation mode is specified, test data DQ which is output from a multi-purpose register 20; and a data bus inversion terminal 32 that outputs, if the first operation mode is specified, a data bus inversion signal DBI indicating whether or not inversion by the data bus inversion circuit 70 is performed, and that is fixed at a predetermined level if the second operation mode is specified. According to the present invention, the test data DQ is not inverted erroneously on a controller side.

Description

  The present invention relates to a semiconductor device and an information processing system including the same, and more particularly to a semiconductor device having a data bus inversion function and an information processing system including the same.

  A function called a data bus inversion function is defined in the DDR4 (Double Data Rate 4) standard, which is the next generation standard of DRAM (Dynamic Random Access Memory). The data bus inversion function is a function that reduces current consumption associated with data transfer by inverting the logical levels of read data and write data that are input / output simultaneously when a predetermined condition is satisfied (patent) Reference 1).

  The DDR4-type DRAM is provided with a register called a multi-purpose register provided separately from the memory cell array. At the initial setting after power-on, the read timing is finely adjusted by performing a training operation using a multi-purpose register.

JP 2011-187153 A

  However, when the data bus inversion function is enabled, there is a risk that data is erroneously inverted on the controller side during training using the multi-purpose register.

  A semiconductor device according to an aspect of the present invention includes a memory cell array, a multi-purpose register provided separately from the memory cell array, and a plurality of read data read from the memory cell array according to a plurality of read data patterns. A data bus inversion circuit that inverts part or all of the read data of the read data, a mode register that specifies a plurality of operation modes including the first and second operation modes, and the first operation mode are specified. In this case, the plurality of read data output from the data bus inversion circuit are output, and when the second operation mode is designated, the plurality of test data output from the multipurpose register is output. A data input / output terminal and the data bus when the first operation mode is designated A data bus inversion signal indicating whether or not inversion by the inversion circuit has been performed, and a data bus inversion terminal fixed to a predetermined level when the second operation mode is designated; It is characterized by providing.

  A semiconductor device according to another aspect of the present invention includes a first operation mode in which read data read from a memory cell array is output from a data input / output terminal, and test data read from a multipurpose register as the data input / output. A second operation mode output from a terminal, a third operation mode in which part or all of the read data is inverted according to the data pattern of the read data, and the read data regardless of the data pattern of the read data. Data indicating whether or not the read data is inverted when the first operation mode is designated and the third operation mode is designated. The bus inversion terminal is output from the data bus inversion signal, the second operation mode is designated, and the previous If the third operation mode is designated, characterized in that for fixing the data bus inversion signal to a predetermined value.

  An information processing system according to the present invention includes the semiconductor device described above and a controller connected to the data input / output terminal and the data bus inversion terminal.

  According to the present invention, the data bus inversion terminal is fixed at a predetermined level during training using the multipurpose register, so that the data is not erroneously inverted on the controller side.

1 is a block diagram showing an overall structure of a semiconductor device 10 according to a preferred embodiment of the present invention. 1 is a block diagram showing a configuration of a data processing system 200 including a semiconductor device 10. 4A and 4B are diagrams for explaining the function of the data bus inversion circuit 70. FIG. 5A shows the value of read data DQ input to the data bus inversion circuit 70, and FIG. The values of the read data DQ and the data bus inversion signal DBI that are output are shown. 2 is a block diagram showing a main part of a part related to a read operation in the semiconductor device 10; FIG. 3 is a circuit diagram showing a part of an inversion control circuit 72 included in a data bus inversion circuit 70. FIG. 7 is a table for explaining the operation of a control circuit 73. FIG. 6 is a timing diagram for explaining the operation of the semiconductor device 10 during training. It is a timing chart for explaining operation at the time of training of a semiconductor device by a reference example.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing the overall structure of a semiconductor device 10 according to a preferred embodiment of the present invention.

  The semiconductor device 10 according to the present embodiment is a DRAM integrated on one semiconductor chip, and includes a memory cell array 11 divided into n + 1 banks as shown in FIG. A bank is a unit capable of executing commands individually, and basically non-exclusive operations are possible between banks.

  The memory cell array 11 is provided with a plurality of word lines WL and a plurality of bit lines BL intersecting with each other, and memory cells MC are arranged at the intersections thereof. Selection of the word line WL is performed by the row decoder 12, and selection of the bit line BL is performed by the column decoder 13. Each bit line BL is connected to a corresponding sense amplifier SA in the sense circuit 14, and the bit line BL selected by the column decoder 13 is connected to the data controller 15 via the sense amplifier SA. The data controller 15 includes an amplifier circuit and a data bus inversion circuit, which will be described later, and is connected to the data input / output circuit 17 via the FIFO circuit 16. The data input / output circuit 17 is a circuit block that inputs and outputs data via the data input / output terminal 21.

  In addition, the semiconductor device 10 includes a multipurpose register 20 provided separately from the memory cell array 11. The multi-purpose register 20 is a circuit for storing test data used at the time of initial setting after the power is turned on. When the multipurpose register 20 is enabled, a read operation and a write operation are performed on the multipurpose register 20 instead of the memory cell array 11. The test data DQ output from the multipurpose register 20 via the data input / output terminal 21 is used for the training operation, and thereby fine adjustment of the read timing is performed.

  In addition to the data input / output terminal 21, the semiconductor device 10 includes strobe terminals 22 and 23, clock terminals 24 and 25, a clock enable terminal 26, an address terminal 27, a command terminal 28, an alert terminal 29, a power supply terminal 30, 31, a data bus inversion terminal 32, an ODT terminal 33, and the like are provided.

  The strobe terminals 22 and 23 are terminals for inputting / outputting external strobe signals DQST and DQSB, respectively. The external strobe signals DQST and DQSB are complementary signals and define the input / output timing of data input / output via the data input / output terminal 21. Specifically, at the time of data input, that is, at the time of write operation, external strobe signals DQST and DQSB are supplied to the strobe circuit 18, and the strobe circuit 18 controls the operation timing of the data input / output circuit 17 based on them. . As a result, the write data DQ input via the data input / output terminal 21 is taken into the data input / output circuit 17 in synchronization with the external strobe signals DQST and DQSB. On the other hand, at the time of data output, that is, at the time of read operation, the operation of the strobe circuit 18 is controlled by the strobe controller 19. As a result, the data input / output circuit 17 outputs the read data DQ in synchronization with the external strobe signals DQST and DQSB.

  The clock terminals 24 and 25 are terminals to which external clock signals CK and / CK are input, respectively. The input external clock signals CK and / CK are supplied to the clock generator 40. In this specification, a signal having “/” at the head of a signal name means a low active signal or an inverted signal of the corresponding signal. Therefore, the external clock signals CK and / CK are complementary signals. The clock generator 40 is activated based on the clock enable signal CKE input via the clock enable terminal 26, and generates the internal clock signal ICLK. The external clock signals CK and / CK supplied via the clock terminals 24 and 25 are also supplied to the DLL circuit 41. The DLL circuit 41 is a circuit that generates an output clock signal LCLK whose phase is controlled based on the external clock signals CK and / CK. The output clock signal LCLK is used as a timing signal that defines the output timing of read data by the data input / output circuit 17.

  The address terminal 27 is a terminal to which an address signal ADD is supplied. The supplied address signal ADD is supplied to the row control circuit 50, the column control circuit 60, the mode register 42, the command decoder 43, and the like. The row control circuit 50 is a circuit block including an address buffer 51 and a refresh counter 52, and controls the row decoder 12 based on the row address. The column control circuit 60 is a circuit block including an address buffer 61 and a burst counter 62, and controls the column decoder 13 based on the column address. If the entry is made in the mode register set, the address signal ADD is supplied to the mode register 42, whereby the contents of the mode register 42 are updated.

  Information indicating the operation mode of the semiconductor device 10 is set in the mode register 42. Information set in the mode register 42 includes at least information indicating whether or not to use the multipurpose register 20 and information indicating whether or not to enable the data bus inversion function.

  When the first operation mode that does not use the multipurpose register 20 is designated, the read operation and the write operation are performed on the memory cell array 11. On the other hand, when the second operation mode using the multipurpose register 20 is designated, the read operation and the write operation are performed on the multipurpose register 20. Therefore, the second operation mode is designated during the training operation.

  When the third operation mode for enabling the data bus inversion function is designated, the logical level of the read data DQ is set using the data bus inversion signal DBI output from the data bus inversion terminal 32. Informs the controller whether or not it is reversed. On the other hand, when the fourth operation mode for disabling the data bus inversion function is designated, the logical level of the read data DQ is not inverted, and therefore the data bus inversion signal DBI is invalid.

  The first and second operation modes are exclusive, and which operation mode is designated is indicated by the mode signal MODE1 / 2 output from the mode register 42. Similarly, the third and fourth operation modes are exclusive, and which operation mode is designated is indicated by the mode signal MODE3 / 4 output from the mode register 42.

  The command terminal 28 is a terminal to which a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, a parity signal PRTY, a reset signal RST, and the like are supplied. These command signals CMD are supplied to the command decoder 43, and the command decoder 43 generates an internal command ICMD based on these command signals CMD. The internal command signal ICMD is supplied to the control logic circuit 44. The control logic circuit 44 controls operations of the row control circuit 50, the column control circuit 60, the data controller 15 and the like based on the internal command signal ICMD.

  The command decoder 43 includes a verification circuit (not shown). The verification circuit verifies the address signal ADD and the command signal CMD based on the parity signal PRTY. As a result, if there is an error in the address signal ADD or the command signal CMD, the verification circuit passes through the control logic circuit 44 and the output circuit 45. To output an alert signal ALRT. The alert signal ALRT is output to the outside via the alert terminal 29.

  The power supply terminals 30 and 31 are terminals to which power supply potentials VDD and VSS are supplied, respectively. The power supply potentials VDD and VSS supplied via the power supply terminals 30 and 31 are supplied to the power supply circuit 46. The power supply circuit 46 is a circuit block that generates various internal potentials based on the power supply potentials VDD and VSS. The internal potential generated by the power supply circuit 46 includes a boosted potential VPP, a power supply potential VPERI, an array potential VARY, a reference potential VREF, and the like. The boosted potential VPP is generated by boosting the power supply potential VDD, and the power supply potential VPERI, the array potential VARY, and the reference potential VREF are generated by stepping down the external potential VDD.

  The boosted voltage VPP is a potential mainly used in the row decoder 12. The row decoder 12 drives the word line WL selected based on the address signal ADD to the VPP level, thereby turning on the cell transistor included in the memory cell MC. The internal potential VARY is a potential mainly used in the sense circuit 14. When the sense circuit 14 is activated, the read data read out is amplified by driving one of the bit line pairs to the VARY level and the other to the VSS level. The power supply voltage VPERI is used as an operating potential for most peripheral circuits such as the row control circuit 50 and the column control circuit 60. By using the power supply potential VPERI having a voltage lower than the power supply potential VDD as the operating potential of these peripheral circuits, the power consumption of the semiconductor device 10 is reduced. The reference potential VREF is a potential used in the data input / output circuit 17.

  The data bus inversion terminal 32 is a terminal from which a data bus inversion signal DBI is output. The ODT terminal 33 is a terminal to which the termination signal ODT is supplied. The termination signal ODT is supplied to the data input / output circuit 17. The termination signal ODT is a signal that is activated when the output buffer included in the data input / output circuit 17 is used as a termination resistor.

  The above is the overall structure of the semiconductor device 10 according to the present embodiment.

  FIG. 2 is a block diagram illustrating a configuration of a data processing system 200 including the semiconductor device 10.

  A data processing system 200 shown in FIG. 2 includes a semiconductor device 10 and a controller 210 that controls the semiconductor device 10. The semiconductor device 10 includes a data bus inversion circuit 70 that inverts a part or all thereof according to the data pattern of the read data DQ output from the memory cell array 11. The read data DQ that has passed through the data bus inversion circuit 70 is output to the controller 210 via the output buffer 91. A data bus inversion signal DBI indicating whether or not the read data DQ is inverted is output to the controller 210 via the output buffer 92.

  The controller 210 includes a data bus inversion circuit 212 that receives the read data DQ and the data bus inversion signal DBI via the receiver circuits 213 and 214, and a main circuit 211 that receives the read data DQ restored by the data bus inversion circuit 212. With. When the data bus inversion signal DBI is activated, the data bus inversion circuit 212 restores the original read data DQ by inverting the logic level of the read data DQ. Here, the receiver circuit 214 that receives the data bus inversion signal DBI is activated when the data bus inversion function is enabled.

  3A and 3B are diagrams for explaining the function of the data bus inversion circuit 70. FIG. 3A shows the value of the read data DQ input to the data bus inversion circuit 70, and FIG. 3B shows the data bus inversion circuit 70. The values of the read data DQ and the data bus inversion signal DBI output from the version circuit 70 are shown. In the example shown in FIG. 3, the number of bits (m) of the data input / output terminal 21 is 8 bits, and the burst length (n) is 8 bits.

  As shown in FIG. 3B, the data bus inversion signal DBI is assigned one bit for each burst output timing. Therefore, in this example, the data bus inversion signal DBI has an 8-bit configuration. Then, all the logic levels of the 8-bit read data DQ corresponding to the burst output timing at which the data bus inversion signal DBI is at the active level (low level in this example) are inverted. In the example shown in FIG. 3B, the bits corresponding to the burst output timings D0 to D4 are inactive level (high level), and the bits corresponding to the burst output timings D5 to D7 are active level (low level). . As a result, it can be seen that the logical level of the read data at the burst output timings D5 to D7 shown in FIG. 3A is inverted in FIG. 3B.

  Hereinafter, the semiconductor device 10 according to the present embodiment will be described in more detail with a focus on portions related to the read operation.

  FIG. 4 is a block diagram illustrating a main part of a part related to the read operation in the semiconductor device 10.

  As described above, when the number of bits (m) of the data input / output terminal 21 is 8 bits and the burst length (n) is 8 bits, the data wiring DB1 that connects the memory cell array 11 and the data controller 15 is shown in FIG. As shown in FIG. The data controller 15 includes an amplifier circuit 47 and a data bus inversion circuit 70. The amplifier circuit 47 and the data bus inversion circuit 70 are connected via a data wiring DB2 having a 64-bit configuration.

  The data bus inversion circuit 70 generates a data bus inversion signal DBI by analyzing the data pattern of the read data DQ, and an inversion that inverts the read data DQ based on the data bus inversion signal DBI. And the control circuit 72, and the mode signal MODE3 / 4 supplied from the mode register 42 designates the third operation mode, that is, the operation mode in which the data bus inversion function is enabled. Activated. The read data DQ output from the inversion control circuit 72 is output via the 64-bit data wiring DB3 and supplied to the parallel-serial conversion circuit 81 included in the FIFO circuit 16. The data bus inversion signal DBI generated by the analysis circuit 71 is output via an 8-bit data bus inversion wiring DBIB3 and supplied to the parallel-serial conversion circuit 82 included in the FIFO circuit 16.

  FIG. 5 is a circuit diagram showing a part of the inversion control circuit 72 included in the data bus inversion circuit 70.

  As shown in FIG. 5, the inversion control circuit 72 includes inversion control circuits 110 to 117 connected between the data wiring DB2-i and the data wiring DB3-i (i = 0 to 7), respectively. These inversion control circuits 110 to 117 invert or non-invert the read data DQ0 input from the data wiring DB2-i and output to the data wiring DB3-i, respectively, and write data input from the data wiring DB3-i. This circuit inverts or non-inverts the data DQ0 and outputs it to the data wiring DB2-i.

  Specifically, the inversion control circuit 110 includes exclusive OR circuits XNOR1 and XNOR2 that receive the data bus inversion signal DBI0. If the data bus inversion signal DBI0 is at a high level, the inversion control circuit 110 and the data lines DB2-0 and data The wiring DB3-0 has the same logic level, and if the data bus inversion signal DBI0 is at a low level, the data wiring DB2-0 and the data wiring DB3-0 have opposite logic levels.

  Data bus inversion signals DBI0 to DBI7 are assigned one bit to a plurality of read data and write data that are input / output simultaneously. The read data DQ0 supplied to the data wirings DB2-0 to DB2-7 is 8-bit read data to be burst output, that is, read data to be output at different timings. Similarly, the data wiring DB3- The write data DQ0 supplied to 0 to DB3-7 is 8-bit write data input in bursts, that is, write data input at different timings. Therefore, as shown in FIG. 5, individual data bus inversion signals DBI0 to DBI7 are assigned to the data wirings DB2-0 to DB2-7 (data wirings DB3-0 to DB3-7), respectively.

  Returning to FIG. 4, the parallel-serial conversion circuit 81 performs parallel-serial conversion on the read data DQ supplied via the 64-bit data wiring DB3 and serially outputs it to the 8-bit data wiring DB4. The read data DQ transferred via the data wiring DB4 is supplied to the output buffer 91, and is output from the data input / output terminal 21 when driven by the output buffer 91. Similarly, the parallel-serial conversion circuit 82 performs parallel-serial conversion on the data bus inversion signal DBI (DBI0 to DBI7) supplied via the data bus inversion wiring DBIB3 having an 8-bit configuration, and data bus-in having a 1-bit configuration. Serially output to the version wiring DBIB4. The data bus inversion signal DBI transferred via the data bus inversion wiring DBIB4 is supplied to the output buffer 92, and is output from the data bus inversion terminal 32 by being driven by the output buffer 92.

  As shown in FIG. 4, the mode signal MODE1 / 2 is supplied from the mode register 42 to the multipurpose register 20. When the mode signal MODE1 / 2 designates the second operation mode, that is, when the mode signal MODE1 / 2 is an operation mode using the multipurpose register 20, the multipurpose register 20 is activated.

  The test data DQ read from the multi-purpose register 20 is supplied to the buffer circuit BF1 via the 64-bit data wiring MPRB. The buffer circuit BF1 is activated in response to the enable signal EN1 output from the control circuit 73, and its output is supplied to the data line DB3. Therefore, when the enable signal EN1 is activated, the test data DQ read from the multipurpose register 20 appears in the data wiring DB3 instead of the read data DQ read from the memory cell array 11.

  On the other hand, a buffer circuit BF2 is connected to the data bus inversion wiring DBIB3. When the buffer circuit BF2 is activated by the enable signal EN1, the buffer circuit BF2 supplies the data bus inversion signal DBI fixed to a predetermined value (high level) to the data bus inversion wiring DBIB3. Therefore, when the enable signal EN1 is activated, all the 8-bit data bus inversion wirings DBIB3 are fixed at a high level.

  The control circuit 73 receives the mode signals MODE1 / 2 and MODE3 / 4 supplied from the mode register 42 and the read enable signal READ supplied from the control logic circuit 44 shown in FIG. 1, and based on these, the enable signal EN1. Activate ~ EN3. The read enable signal READ is a signal that is activated at a predetermined timing when a read command is issued from the controller 210.

  More specifically, the operation of the control circuit 73 will be described with reference to FIG. 6. As indicated by the condition A, the mode signal MODE1 / 2 indicates a second operation mode, that is, an operation mode using the multipurpose register 20. In addition, when the mode signal MODE3 / 4 indicates the third operation mode, that is, the operation mode using the data bus inversion function, the control circuit 73 responds to the read enable signal READ to enable the enable signal EN1. Activate ~ EN3. As a result, the test data DQ is output from the data input / output terminal 21 and the data bus inversion terminal 32 is fixed at a high level.

  As indicated by condition B, the mode signal MODE1 / 2 indicates the first operation mode, that is, the operation mode in which the multipurpose register 20 is not used, and the mode signal MODE3 / 4 indicates the third operation mode. That is, when the operation mode using the data bus inversion function is indicated, the control circuit 73 activates the enable signals EN2 and EN3 in response to the read enable signal READ. As a result, the read data DQ is output from the data input / output terminal 21 and the data bus inversion signal DBI is output from the data bus inversion terminal 32.

  Further, as indicated by the condition C, the mode signal MODE1 / 2 indicates the first operation mode, that is, the operation mode not using the multi-purpose register 20, and the mode signal MODE3 / 4 is the fourth operation mode. That is, when the operation mode not using the data bus inversion function is indicated, the control circuit 73 activates the enable signal EN2 in response to the read enable signal READ. As a result, the read data DQ is output from the data input / output terminal 21 and the data bus inversion terminal 32 is in a high impedance state.

  As indicated by condition D, the mode signal MODE1 / 2 indicates the second operation mode, that is, the operation mode using the multipurpose register 20, and the mode signal MODE3 / 4 indicates the fourth operation mode. In other words, in the case of the operation mode not using the data bus inversion function, the control circuit 73 activates the enable signals EN1 and EN2 in response to the read enable signal READ. As a result, the test data DQ is output from the data input / output terminal 21 and the data bus inversion terminal 32 is in a high impedance state.

  FIG. 7 is a timing chart for explaining the operation during training of the semiconductor device 10 according to the present embodiment.

  In the example shown in FIG. 7, the mode register set command MR is issued at time t1 in synchronization with the external clock signal CK, thereby switching the data bus inversion function from disabled to enabled. That is, the fourth operation mode is switched to the third operation mode.

  Next, a mode register set command MR is issued at time t2, thereby switching to an operation mode using the multipurpose register. That is, the first operation mode is switched to the second operation mode. Therefore, this state is the state of condition A shown in FIG.

  In this state, when the read command RD is issued at time t3, the multipurpose register 20 is accessed instead of the memory cell array 11. Since the enable signal EN1 is activated, the test data DQ held in the multipurpose register 20 is read out to the data wiring DB3. On the other hand, the data bus inversion wiring DBIB3 is all fixed at a high level by the buffer circuit BF2.

  As a result, when the enable signals EN2 and EN3 are subsequently activated, the test data DQ is burst output from the data input / output terminal 21, and the data bus inversion terminal 32 is fixed at a high level.

  At time t4, the mode register set command MR is issued, and the operation mode is switched to the operation mode that does not use the multi-purpose register. That is, the operation mode is switched from the second operation mode to the first operation mode, and the state returns to the time t1 to t2.

  FIG. 8 is a timing chart for explaining the operation during training of the semiconductor device according to the reference example.

  In the example shown in FIG. 8, the types of commands issued at times t1 to t4 are the same as in the example shown in FIG. 7, but the semiconductor device according to the reference example does not include the buffer circuit BF2. In the case of the condition A in which the second and third operation modes are selected at the same time, the enable signal EN3 is not activated. In this case, as shown in FIG. 8, the data bus inversion terminal 32 is not driven to a high level in synchronization with the burst output of the test data DQ, and remains in a high impedance state.

  Even in such a case, the data bus inversion terminal 32 normally shows a high level. This is because, even when the output buffer 92 corresponding to the data bus inversion terminal 32 is in a high impedance state, the data bus inversion terminal 32 is generally pulled up via a termination resistor existing in the transmission line. That's why.

  However, in general, the pull-up capability via the termination resistor is weak, so that the level of the data bus inversion terminal 32 may fluctuate due to the influence of noise. For this reason, if noise is superimposed on the transmission line, there is a possibility that the low-level data bus inversion signal DBI is transmitted to the controller 210 side. In this case, erroneous data inversion is performed by the data bus inversion circuit 212. It will be broken. This is because when the third operation mode is designated, the receiver circuit 214 included in the controller 210 is activated regardless of whether the first operation mode is designated or the second operation mode is designated. Because there is a possibility that. If wrong data inversion is performed, the training operation naturally becomes an error. Such a problem also occurs when the transmission line is terminated at an intermediate level.

  In contrast, in the semiconductor device 10 according to the present embodiment, the data bus inversion terminal 32 is fixed at a high level in the case of the condition A in which the second and third operation modes are selected at the same time. There is no problem, and the training operation can be performed correctly.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Memory cell array 12 Row decoder 13 Column decoder 14 Sense circuit 15 Data controller 16 FIFO circuit 17 Data input / output circuit 18 Strobe circuit 19 Strobe controller 20 Multipurpose register 21 Data input / output terminals 22 and 23 Strobe terminals 24 and 25 Clock Terminal 26 Clock enable terminal 27 Address terminal 28 Command terminal 29 Alert terminal 30, 31 Power supply terminal 32 Data bus inversion terminal 33 ODT terminal 40 Clock generator 41 DLL circuit 42 Mode register 43 Command decoder 44 Control logic circuit 45 Output circuit 46 Power supply circuit 47 Amplifier circuit 50 Row control circuit 51 Address buffer 52 Refresh counter 60 Column controller Circuit 61 Address buffer 62 Burst counter 70 Data bus inversion circuit 71 Analysis circuit 72 Inversion control circuit 73 Control circuits 81 and 82 Parallel serial conversion circuits 91 and 92 Output buffers 110 to 117 Inversion control circuit 200 Data processing system 210 Controller 211 Main circuit 212 Data bus inversion circuit 213, 214 Receiver circuit BF1, BF2 Buffer circuit BL Bit line DB1-DB4 Data wiring DBIB3, DBIB4 Data bus inversion wiring MC Memory cell MPRB Data wiring SA Sense amplifier WL Word line XNOR1, XNOR2 Exclusive logic Sum circuit

Claims (10)

A memory cell array;
A multipurpose register provided separately from the memory cell array;
A data bus inversion circuit that inverts part or all of the plurality of read data according to a data pattern of the plurality of read data read from the memory cell array;
A mode register for designating a plurality of operation modes including a first operation mode and a second operation mode;
The plurality of read data output from the data bus inversion circuit is output when the first operation mode is designated, and the multipurpose is outputted when the second operation mode is designated. A data input / output terminal for outputting a plurality of test data output from the register;
When the first operation mode is designated, a data bus inversion signal indicating whether or not inversion by the data bus inversion circuit has been performed is output, and the second operation mode is designated. A data bus inversion terminal which is fixed to a predetermined level in some cases, and a semiconductor device. Data wiring connecting the data bus inversion circuit and the data input / output terminal;
A data bus inversion wiring connecting the data bus inversion circuit and the data bus inversion terminal;
A first buffer circuit for transferring the plurality of test data output from the multipurpose register to the data wiring;
A second buffer circuit for supplying a predetermined value to the data bus inversion wiring, and
The first and second buffers are deactivated when the first operation mode is designated, and activated when the second operation mode is designated. The semiconductor device according to claim 1.   The plurality of operation modes further include a third operation mode for activating the data bus inversion circuit and a fourth operation mode for deactivating the data bus inversion circuit. 3. The semiconductor device according to 1 or 2.   The data bus inversion terminal is fixed to the predetermined level when the second operation mode is designated and the third operation mode is designated. The semiconductor device described.   5. The semiconductor device according to claim 4, wherein the data bus inversion terminal is in a high impedance state when the fourth operation mode is designated. A first operation mode for outputting read data read from the memory cell array from a data input / output terminal;
A second operation mode for outputting test data read from a multipurpose register from the data input / output terminal;
A third operation mode for inverting part or all of the read data in accordance with a data pattern of the read data;
A fourth operation mode that does not invert the read data regardless of the data pattern of the read data,
When the first operation mode is designated and the third operation mode is designated, a data bus inversion terminal indicating whether or not the read data is inverted is output from a data bus inversion signal. ,
A semiconductor device characterized in that, when the second operation mode is designated and the third operation mode is designated, the data bus inversion signal is fixed to a predetermined value.   The semiconductor device according to claim 6, wherein when the fourth operation mode is designated, the data bus inversion terminal is set to a high impedance state.   An information processing system comprising: the semiconductor device according to claim 3; and a controller connected to the data input / output terminal and the data bus inversion terminal.   The controller includes a first receiver circuit that receives the plurality of read data and a second receiver circuit that receives the data bus inversion signal, and the third operation mode is designated for the semiconductor device. 9. The information processing system according to claim 8, wherein the second receiver circuit is activated. When the third operation mode is designated for the semiconductor device, the controller
The information processing system according to claim 9, wherein the second receiver circuit is activated regardless of whether or not the second operation mode is designated.

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