JP2015149107A - Semiconductor device and semiconductor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve the high accuracy of a command decoder of a semiconductor device.SOLUTION: A first decode circuit 50 of a semiconductor device 10 includes: a plurality of input terminals that receive a plurality of internal command signals, respectively; a plurality of output terminals that correspond to the plurality of input terminals, respectively; and latch units 54 that are provided between the plurality of input terminals and the plurality of output terminals. The latch unit 54 includes: a latch circuit 56a of a type that is connected with one of the input terminals and one of the output terminals; and a latch circuit 56b of a type that is connected with two or more of the input terminals and two or more of the output terminals.

Description

  The present invention particularly relates to a semiconductor device and a semiconductor system having a function of generating an internal command from an external command by a command decoder.

  As represented by DRAM (Dynamic Random Access Memory), many semiconductor devices include a command decoder that generates an internal command signal by decoding a command signal supplied from the outside. The internal command signal is supplied to each circuit block in the semiconductor device, and various processes are executed. Usually, a command decoder incorporates a plurality of latch circuits corresponding to a plurality of internal command signals (see Patent Document 1).

JP 2009-20953 A

  In order to reduce the size of the semiconductor device, it is preferable to reduce the area of the region where the latch circuit is disposed. However, the layout of the latch circuit is limited because it is necessary to arrange the latch circuit so as not to cause a timing shift due to the internal command signal.

  A semiconductor device according to the present invention is provided between a plurality of input terminals receiving each of a plurality of internal command signals, a plurality of output terminals corresponding to each of the plurality of input terminals, and the plurality of input terminals and the plurality of output terminals. And a signal holding circuit. The signal holding circuit includes a first latch circuit connected to one input terminal and one output terminal, and a second latch circuit connected to two or more input terminals and two or more output terminals.

  A semiconductor system according to the present invention includes a semiconductor device including a command decoding unit that generates a plurality of internal command signals from a plurality of external command signals, a signal holding circuit that holds the internal command signals, and a plurality of external command signals. And a controller for supplying the semiconductor device. The signal holding circuit is provided between a plurality of input terminals receiving each of the plurality of internal command signals and a plurality of output terminals corresponding to the plurality of input terminals, and is connected to one input terminal and one output terminal. And a second latch circuit connected to two or more input terminals and two or more output terminals.

  A semiconductor device according to the present invention includes a first command decoder that converts an external command signal into a first internal command signal, a second command decoder that converts a first internal command signal into a second internal command signal, A state detection circuit that transmits a state signal designating any one of a plurality of types of control states to the second command decoder. The second command decoder selectively generates a plurality of types of second internal command signals from the first internal command signal according to the control state indicated by the state signal.

  According to the present invention, the number of latch circuits included in the command decoder of the semiconductor device can be reduced, and the layout of the latch circuit can be facilitated to prevent problems such as erroneous latches, thereby improving the accuracy of the command decoder. Is realized.

1 is a block diagram illustrating an overall configuration of a semiconductor device according to an embodiment of the present invention. FIG. 4 is an enlarged block diagram of a part of the semiconductor device. 6 is a table showing internal command signals output by latch signals L1 to L3 corresponding to the state of the semiconductor device. It is a circuit diagram of a 1st decoding circuit. It is a circuit diagram of a bank state circuit. It is a circuit diagram of a bank activation detection circuit. It is a circuit diagram of a 2nd decoding circuit. It is a sequence diagram which shows the process in which the 2nd decoding circuit changes the interpretation of internal command L2 according to a status signal. 1 is a system configuration diagram of a semiconductor system including a semiconductor device and a controller.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing the overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention.

  The semiconductor device 10 according to the present embodiment is a DDR3 (Double Data Rate 3) type DRAM integrated on a single semiconductor chip, and is mounted on the external substrate 2. The external substrate 2 is a memory module substrate or a mother board, and is provided with an external resistor Re. The external resistor Re is connected to the calibration terminal 8 of the semiconductor device 10, and its impedance is used as the reference impedance of the calibration circuit 38. In the present embodiment, the ground potential VSS is supplied to the external resistor Re.

  As shown in FIG. 1, the semiconductor device 10 has a memory cell array 11. Memory cell array 11 includes memory banks BANK0-7, and each memory bank BANK0-7 is selected by bank addresses BA0-2 (part of address signal ADD) received by address input circuit 31. Each memory bank BANK includes a plurality of word lines and a plurality of bit lines, and memory cells are arranged at intersections thereof. Selection of the word line is performed by the row decoder 12, and selection of the bit line is performed by the column decoder 13.

  Further, the semiconductor device 10 is provided with an address terminal 21, a command terminal 22, a clock terminal 23, a data terminal 24, power supply terminals 25 and 26, and a calibration terminal 8 as external terminals. Further, the semiconductor device 10 may be provided with a test input / output terminal and a reset terminal.

  An address signal ADD is supplied to the address terminal 21, and an external command signal COM is supplied to the command terminal 22. The address signal ADD is latched by the address latch circuit 32 via the address input circuit 31. The address latch circuit 32 supplies the internal address signal IADD to the row decoder 12, the column decoder 13, and the mode register 14. The mode register 14 is a circuit in which a parameter indicating the operation mode of the semiconductor device 10 is set. Of the address signal ADD, a bank address BA that designates a bank is also supplied to a command decode circuit 33 (Command Decoder).

  The external command signal COM is supplied to the command decoding circuit 33 via the command input circuit 42. The command decode circuit 33 generates various internal command signals by decoding the external command signal COM. As internal command signals, an internal active signal IACT, an internal operation command signal INOP, an internal read command signal IREAD, an internal precharge command signal IPRE, an internal calibration command signal IZQ, an internal write command signal IWRT, an internal mode register There is a set command signal IMRS. The command decode circuit 33 supplies the status signal C 1 to the internal clock generation circuit 35, and the command input circuit 42 supplies the clock enable signal CKE to the internal clock generation circuit 35.

  The internal active signal IACT is issued when the external command signal COM indicates a row access (active command). In row access, the word line corresponding to the internal address signal IADD is selected in the row decoder 12 of the bank designated by the bank address signals BA0 to BA2 latched in the address latch circuit 32.

  The internal read command signal IREAD and the internal write command signal are issued when the external command signal COM indicates column access. In the column access, a bit line corresponding to the internal address signal IADD is selected in the column decoder 13 of the bank designated by the bank address signals BA0 to BA2 latched in the address latch circuit 32.

  Therefore, when the internal active command signal IACT and the row address are issued, and then the internal read command signal IREAD and the column address are issued, read data is read from the memory cell specified by the row address and the column address. Read data is output from the data terminal 24 to the outside via the bus MIOT / B via the read / write amplifiers RWAMP 0 to 7 and the input / output circuit 16.

  If an internal active command signal IACT and a row address are issued, then an internal write command signal WRT and a column address are issued, and then write data is input to the data terminal 24, the write data is sent to the input / output circuit 16 and the read / write amplifier RWAMP. And supplied to the memory cell array 11 and written in the memory cell specified by the row address and the column address.

  The internal refresh command signal IREF is supplied to the refresh circuit 40. The refresh circuit 40 controls the row decoder 12 to activate a predetermined word line included in the memory cell array 11 and execute a refresh operation.

  The internal mode register set command signal IMRS is supplied to the mode register 14. When the internal mode register set command signal IMRS is activated, the set value of the mode register 14 is rewritten by the set value input from the address terminal 21. The internal knock command signal INOP does not instruct special processing. Internal precharge command signal IPRE instructs precharging of the word line. The internal calibration command signal IZQ instructs the calibration circuit 38 to perform calibration. The calibration will be described later.

  External clock signals CK and / CK are input to the clock terminal 23. The external clock signal CK and the external clock signal / CK are complementary signals, and both are supplied to the clock input circuit 34. The external clock signals CK and / CK input to the clock input circuit 34 are supplied to the internal clock generation circuit 35 as the internal clock signal ICLK, thereby generating the internal clock signal LCLK. The internal clock signal ICLK is also supplied to the timing generator 36, whereby various internal clock signals are generated. Various internal clock signals generated by the timing generator 36 are supplied to circuit blocks such as the address latch circuit 32 and define the operation timing of these circuit blocks.

  The power supply terminal 25 is a terminal to which power supply potentials VDD and VSS are supplied. The power supply potentials VDD and VSS supplied to the power supply terminal 25 are supplied to an internal circuit (not shown) and also supplied to the internal power supply generation circuit 37. The internal power supply generation circuit 37 generates various internal power supply potentials VPP, VOD, VARY, VPERI and a reference potential ZQVREF based on the power supply potentials VDD and VSS. Internal power supply potential VPP is, for example, a potential used to drive a word line in row decoder 12, and internal power supply potentials VOD, VARY are potentials used in a sense amplifier in memory cell array 11, and internal power supply The potential VPERI is a potential used in many other circuit blocks. On the other hand, the reference potential ZQVREF is a reference potential used in the calibration circuit 38.

  The power supply terminal 26 is a terminal to which power supply potentials VDDQ and VSSQ are supplied, and is supplied to the output circuit in the input / output circuit 16.

  The calibration terminal 8 is connected to the calibration circuit 38. When activated by the internal calibration command IZQ, the calibration circuit 38 performs a calibration operation based on the impedance of the external resistor Re and the reference potential ZQVREF. The impedance code ZQCODE obtained by the calibration operation is supplied to the input / output circuit 16, whereby the impedance of the output circuit included in the input / output circuit 16 is adjusted.

  FIG. 2 is a block diagram corresponding to region 6 (address input circuit 31, command input circuit 42, clock input circuit 34, command decode circuit 33) in FIG. The command input circuit 42 is supplied with a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, and a chip select signal CSB as external command signals. In response to these external command signals, the command decode circuit 33 causes the internal knock command signal INOP, the internal active command signal IACT, the internal read command signal IREAD, the internal refresh command signal IREF, the internal precharge command signal IPRE, and the internal calibration command signal IZQ. The internal write command signal IWRT and the internal mode register set command signal IMRS are selectively activated. For example, when RASB = L, CASB = H, WEB = H, and CSB = L are input, the command decode circuit 33 activates the active command ACT.

  The command decode circuit 33 includes a first decode circuit 50 (first command decoder), a second decode circuit 60 (second command decoder), an address decode circuit 70, a bank state circuit 80, and a bank activation detection circuit 90 (state detection). Circuit). The decoding of the external command signal, that is, the conversion from the external command signal to the internal command signal is performed in two stages of the first decoding circuit 50 and the second decoding circuit 60.

  The first decode circuit 50 decodes the external command signal, and the internal clock signal ICLK in the latch circuit corresponding to the decoded internal command signal IACT, internal knock command signal INOP, and intermediate command signals L1, L2, and L3, respectively. Latch in sync with.

  The second decode circuit 60 receives either the internal read command signal IREAD or the internal refresh command signal IREF, which is an internal command signal (second internal command signal), from the intermediate command signals L1 to L3, and the internal precharge command signal IPREAD. One of the internal calibration command signal IZQ and one of the internal write command signal IWRT and the internal mode register set command signal IMRS is output. Thus, a total of eight types of internal commands can be generated together with the internal knock command signal INOP and the internal active command signal IACT. Details of the first decoding circuit 50 will be described later with reference to FIG. 4, and details of the second decoding circuit 60 will be described later with reference to FIG.

  FIG. 3 is a table showing which one of the internal commands L1 to L3 is output. Each of the memory banks BANK0 to 7 takes one of two control states of an active state and an idle state.

  The active state refers to a state where an internal active command IACT is issued in each memory bank and one of the word lines is activated. The idle state refers to an internal precharge command IPRE after the internal active command IACT. This indicates a state in which no word line is activated in any bank depending on whether it is received or an internal active command is not received.

  In the present embodiment, both the internal command signal issued in the active state and the internal command signal issued in the idle state are assigned to the intermediate command signals L1 to L3, respectively. Specifically, an internal read command IREAD issued in the active state and an internal refresh command signal IREF issued in the idle state are assigned to the intermediate command signal L1, and an internal command issued in the active state is assigned to the intermediate command signal L2. A precharge command IPRE and an internal calibration command signal IZQ issued in the idle state are assigned, and an internal write command IWRT issued in the active state and an internal mode register set command signal issued in the idle state are assigned to the intermediate command signal L3. IMRS is assigned.

  Returning to the description of FIG. The address decode circuit 70 decodes the bank address signals BA0 to BA2 in the address signal ADD, and designates any one bank corresponding to the bank address decode signals B0 to B7.

  In this embodiment, two types of internal command signals are assigned to the intermediate command signals L1 to L3 as described above. The active state and the idle state are switched by the internal active command signal IACT and the internal precharge command IPRE. Bank state circuit 80 receives bank address decode signals B0-B7, internal active command IACT and internal precharge command IPRE, and outputs bank state signals ACTB0-ACTB7 indicating the control state of each memory bank BANK. For example, when memory bank BANK0 is in an active state, bank state signal ACTB0 is activated. Details of the bank state circuit 80 will be described later with reference to FIG.

  Bank activation detection circuit 90 outputs a state signal C1 indicating the control state of memory bank BANK designated by bank state signals ACTB0 to ACTB7. The state signal C1 = L when in an idle state, and the state signal C1 = H when at least one bank is in an active state. Details of the bank activation detection circuit 90 will be described in detail with reference to FIG. The second decoding circuit 60 decodes the intermediate command signals L1 to L3 using the status signal C1.

  Note that the semiconductor device according to the present embodiment is configured to enter the power down mode when the clock enable signal CKE is deactivated.

  The internal clock generation circuit 35 stops the internal clock signal LCLK when entering the power down mode in the idle state (state signal C1 = L), and transitions into the power down mode when in the active state (state signal C1 = H). Sometimes the internal clock signal LCLK is not stopped. This is because in the active state, the internal clock signal LCLK needs to be maintained for a quick return from the power down mode.

  FIG. 4 is a circuit diagram of the first decoding circuit 50. The first decoding circuit 50 includes a decoding unit 52 and a latch unit 54 (signal holding circuit). The decode unit 52 decodes the external command signal and outputs one of the internal active command signal IACT, the internal knock command signal INOP, and the intermediate command signals L1 to L3. As described above, when RASB = L, CASB = H, WEB = H, and CSB = L are input, the internal active command signal IACT is output.

  The latch unit 54 includes five latch circuits 56a to 56e corresponding to the five types of internal command signals. Each latch circuit 56 latches the internal command signal in synchronization with the internal clock signal ICLK. In addition, a delay circuit DELAY for timing adjustment is provided in the preceding stage of each latch circuit 56.

  The latch circuit 56a (first latch circuit) corresponds to the internal active command signal IACT. One input terminal and one output terminal are provided. The latch circuit 56e corresponds to the internal knock command signal INOP and similarly includes one input terminal and one output terminal.

  On the other hand, the input terminal of latch circuit 56b (second latch circuit) corresponding to command L1 is connected to the output terminal of a NAND circuit having two input terminals that receive different internal command signals. Further, the output terminal of the latch circuit 56b is commonly connected to one input terminal of two NAND circuits as shown in the second decode circuit 60 of FIG. 7, and the two NAND circuits are different from each other in response to the state signal C1. An internal command signal is output to the output terminal. The same applies to the latch circuit 56c corresponding to the command L2 and the latch circuit 56d corresponding to the command L3.

  FIG. 5 is a circuit diagram of the bank state circuit 80. When a memory bank is designated by address signal ADD, one of bank address decode signals B0-B7 is activated. For example, when the memory bank BANK0 is selected, the bank address decode signal B0 = H. In the bank state circuit 80, SR latch circuits 82a to 82h are provided corresponding to the memory banks BANK0 to BANK7.

  When the bank address decode signal B0 = H and the internal active command signal IACT = H, the set signal S = L and the reset signal R = H of the SR latch circuit 82a are set, the SR latch circuit 82a is set, and the bank status signal ACTB0 = H. The other bank status signals ACTB1 to ACTB7 are all L.

  When the bank address decode signal B0 = H and the internal precharge command signal IPRE = H, since the reset signal R = L of the SR latch circuit 82a, the SR latch circuit 82a is reset and the bank state signal ACTB0 = L.

  FIG. 6 is a circuit diagram of the bank activation detection circuit 90. Bank activation detection circuit 90 outputs a status signal C1 = H when any of bank status signals ACTB0 to ACTB7 is activated. In other words, the state signal C1 = H is output when at least one memory bank BANK designated by the bank address signals BA0 to BA2 is in an active state, and the state signal C1 = L is output when all the memory banks BANK are in an idle state.

  FIG. 7 is a circuit diagram of the second decoding circuit 60. When the state signal C1 = H (active state), the intermediate command signal L1 is a terminal on the internal read command signal IREAD side, the intermediate command signal L2 is a terminal on the internal write command signal IWRT side, and the intermediate command signal L3 is an internal precharge. The signal is output to the terminal on the command signal IPRE side to serve as the above signal. When the state signal C1 = L (idle state), the intermediate command signal L1 is the internal refresh command signal IREF, and the intermediate command signal L2 is the internal mode. The register set command signal IMRS and the intermediate command signal L3 are respectively output to the terminals on the internal calibration command signal IZQ side and serve as the above signals.

  FIG. 8 is an operation explanatory diagram corresponding to the present embodiment. When the calibration command ZQ is issued from the outside when the memory banks BANK0 to 7 are in the idle state (state signal C1 = L), the intermediate command signal L2 is activated. Here, the intermediate command signal L2 is output to the terminal on the internal calibration command signal IZQ side of the two NAND circuits receiving the status signal C1 = L and receiving the intermediate command signal L2, and the terminal on the internal precharge command signal IPRE side. Is not output. A calibration command ZQ is executed by this control.

  When active command ACT is designated from the outside after designating memory bank BANK0, SR latch circuit 82a corresponding to bank state signal ACTB0 is set in bank state circuit 80. In response to this, the bank activation detection circuit 90 outputs the state signal C1 = H, and the memory bank BANK0 changes to the active state.

  Subsequently, when the precharge command PRE is designated from the outside after designating the memory bank BANK0, the intermediate command signal L2 is activated again. However, the intermediate command signal L2 is received by receiving the state signal C1 = H. Among the two NAND circuits, the intermediate command signal L2 is output to the terminal on the internal precharge command signal IPRE side, and is not output to the terminal on the internal calibration command signal IZQ side. By this control, the precharge command PRE is executed. Further, since the SR latch circuit 82a is reset, the bank state signal ACTB0 is inactivated. Corresponding to this, the bank activation detection circuit 90 outputs the state signal C1 = L, and the memory banks BANK0 to 7 shift to the idle state.

  FIG. 9 is a system configuration diagram of the semiconductor system 110 including the semiconductor device 10 and the controller 100. The controller 100 supplies the semiconductor device 10 with an address signal ADD (including a bank address signal BA), an external command signal COM, a write data signal DQ, and external clock signals CK and / CK, and also receives a read data signal from the semiconductor device 10. Read DQ.

  The controller 100 includes a command / address queue generator 102, an address output circuit 104, a command output circuit 106, and an input / output control circuit 108. The command / address queue generation unit 102 generates an address and a command based on information given from the external terminal INPUT, and performs control for arranging them in an appropriate order. The address output circuit 104 supplies an address signal ADD to the semiconductor device 10, and the command output circuit 106 supplies an external command signal COM to the semiconductor device 10. The input / output control circuit 108 supplies external clock signals CK and / CK to the semiconductor device 10 and transmits / receives data DQ.

  The semiconductor device 10 has been described above based on the embodiment. The semiconductor device 10 handles eight types of internal commands. In the first decoding circuit 50, two internal commands are associated with each of the commands L1 to L3 in a multiplexed manner. For this reason, the first decoding circuit 50 requires only five latch circuits 56 for eight types of internal commands. That is, the number of latch circuits 56 is reduced from eight to five by consolidating six internal commands into three commands L1 to L3.

  By reducing the number of latch circuits 56, the circuit area of the command decode circuit 33 can be reduced. The second decode circuit 60 is newly added. However, since the second decode circuit 60 is a simple circuit as shown in FIG. 7, the effect of reducing the number of latch circuits 56 is greater. Further, since the number of latch circuits 56 is reduced, the current consumption of the command decode circuit 33 is also reduced. Further, when the number of latch circuits 56 is reduced, the latch timings in all the latch circuits 56 are easily made uniform.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

2 External substrate 6 Area 8 Calibration terminal 10 Semiconductor device 11 Memory cell array 12 Row decoder 13 Column decoder 14 Mode register 16 Input / output circuit 21 Address terminal 22 Command terminal 23 Clock terminal 24 Data terminal 25 Power supply terminal 26 Power supply terminal 26 Power supply terminal 31 Address input circuit 32 Address latch circuit 33 Command decode circuit 34 Clock input circuit 35 Internal clock generation circuit 36 Timing generator 37 Internal power supply generation circuit 38 Calibration circuit 40 Refresh circuit 42 Command input circuit 50 First decode circuit 52 Decode unit 54 Latch unit 56 Latch circuit 60 Second decode circuit 70 Address decode circuit 80 Bank state circuit 82 SR latch circuit 90 Bank activity detection circuit 100 Controller 102 Command / address queue generator 104 Address output circuit 106 Command output circuit 108 Input / output control circuit 110 Semiconductor system IACT Internal active command signal ACTB Bank status signal INOP Internal knock command signal IREAD Internal read command signal IREF Internal refresh command signal IPRE Internal Precharge command signal IZQ Internal calibration command signal C1 Status signal CK External clock signal IWRT Internal write command signal IMRS Internal mode register set command signal ADD Address signal IADD Internal address signal ICLK Internal clock signal BA Bank address BANK Memory bank RWAMP Read / write amplifier CKE Clock enable signal COM Part command signal Re external resistor

Claims (7)

A plurality of input terminals each receiving a plurality of internal command signals;
A plurality of output terminals corresponding to each of the plurality of input terminals;
A signal holding circuit provided between the plurality of input terminals and the plurality of output terminals,
The signal holding circuit is
A first latch circuit provided between one of the input terminals and one of the output terminals;
And a second latch circuit provided between the two or more input terminals and the two or more output terminals respectively corresponding to the two or more input terminals. A memory bank including a plurality of memory cells;
The semiconductor device according to claim 1, wherein an active command for activating the memory bank is input to the first latch circuit.   The two or more input terminals connected to the second latch circuit include the input terminal that receives a first command issued on condition that the memory bank is in an active state, and the memory bank is inactive. The semiconductor device according to claim 1, further comprising: the input terminal that receives a second command issued on condition that the second command is issued.   4. The semiconductor device according to claim 1, wherein the first and second latch circuits latch the internal command in synchronization with an internal clock signal.   5. The semiconductor device according to claim 1, wherein a delay circuit is provided in front of the first and second latch circuits. A semiconductor device including a command decoding unit that generates a plurality of internal command signals from a plurality of external command signals, and a signal holding circuit that holds the internal command signals;
A controller for supplying the plurality of external command signals to the semiconductor device,
The signal holding circuit is provided between a plurality of input terminals receiving each of the plurality of internal command signals and a plurality of output terminals corresponding to the plurality of input terminals,
A first latch circuit connected to one of the input terminals and one of the output terminals;
And a second latch circuit connected to the two or more input terminals and the two or more output terminals. A first command decoder for converting an external command signal into a first internal command signal;
A second command decoder for converting the first internal command signal into a second internal command signal;
A state detection circuit that transmits a state signal designating any one of a plurality of types of control states to the second command decoder;
The second command decoder selectively generates a plurality of types of second internal command signals from the first internal command signal according to a control state indicated by the state signal. .

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