KR20070033094A - The flash memory and the driving method thereof - Google Patents

Abstract

A flash memory and an operation method thereof are provided to improve performance of a NOR type flash memory by reducing errors generated in an erase step of the NOR type flash memory. A gate oxide is formed in a fixed region on a device area of a semiconductor substrate. A floating gate is formed on the gate oxide. A dielectric film is formed on the floating gate. A control gate is formed on the dielectric film. Source and drain regions are injected with impurities on the device area of the semiconductor substrate. The generation rate of an erase error is reduced by decreasing the voltage of the floating gate and adjusting the width of the floating gate.

Description

Flash memory and its operation method {THE FLASH MEMORY AND THE DRIVING METHOD THEREOF}

1 is a flowchart of erasing from a flash memory.

FIG. 2 is a diagram illustrating cell voltages that change as the erase phase is performed in the flash memory.

3 is a diagram illustrating a voltage and capacitance relationship in a flash memory.

FIG. 4 is a graph showing cell erasure error versus cell voltage and gate width.

5 is a graph illustrating a change in source side resistance according to a gate width.

6 is a graph illustrating a change in cell current according to a gate width.

FIG. 7 is a graph illustrating an over time erasure error with respect to the cell voltage and the gate width.

8 and 9 are graphs showing changes in erase error before and after applying the present invention.

The present invention relates to a flash memory. More specifically, the present invention is to reduce an error occurring when erasing the NOR flash memory.

In general, flash memory starts with the purpose of simultaneously implementing the advantages of erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM). It is aimed at low manufacturing cost in terms of chip size.

In addition, the flash memory is a nonvolatile semiconductor memory that does not lose data even when the power supply is interrupted. However, since the flash memory is easily electrically programmed and erased in the system, it is a random access memory (RAM). It is used for the memory device which replaces the hard disk of a memory card or a portable office automation device.

The programming of data in such flash memory is by injection of hot electrons. In other words, when hot electrons are generated in a channel due to potential differences between a source and a drain, some of the electrons having energy above the potential barrier between the polycrystalline silicon forming the gate and the oxide layer are high at the control gate. It is moved and stored by the electric field to the floating gate.

Flash memory includes NAND flash memory and NOR flash memory. A NAND type flash memory is a flash memory having a structure in which memory cells are connected in series, and a NOR type flash memory is a flash memory having a structure in which memory cells are connected in parallel.

Compared to NAND flash memory, NOR flash memory has a short time for access (random access), but has a disadvantage of slow erasing.

Referring to FIGS. 1 and 2, an erase step of the NOR type flash memory will be described.

FIG. 1 is a flowchart illustrating erasing in a flash memory, and FIG. 2 is a diagram illustrating a cell voltage that changes as the erasing is performed in a flash memory.

In order to erase, the block is first pre-programmed (S1). Due to the preprogramming, the voltage of each cell in the black is high (see Fig. 2). Then proceed with the Erase phase. If so, the cell voltage is lowered. In the erase verify step, it is checked whether the cell voltage is lower than a predetermined value (dotted line in FIG. 2). In this case, if the cell voltage is higher than a predetermined value, the erase step is performed. If the cell voltage is too low, the erase step is corrected and then a post-program step is performed (S4). The program step changes the voltage value outside the normal range to the voltage value ② in the normal range as in ① of FIG.

The reason why the erase speed is slow in the NOR type flash memory is because erase is executed in units of blocks, and the erased cells and the programmed cells coexist in the block as shown in FIG. Pre-program phase, Erase phase, Erase verify phase, and post-program phase must be completed. If the verification phase does not fall below the cell voltage requested by Erase, This is because you have to repeat from the Erase step.

The technical problem to be achieved by the present invention is to eliminate the error occurring in the erasing (Erase) step in the NOR flash memory and to improve the speed.

In order to solve this problem, the present invention optimizes the cell voltage and the gate width.

Specifically, a flash memory according to the present invention may include a gate oxide film formed on a portion of an upper portion of an element region of a semiconductor substrate; A floating gate formed on the gate oxide layer; A dielectric layer formed on the floating gate; A control gate formed on the dielectric layer; In a NOR type flash memory including a source / drain region in which impurities are implanted in an element region of the semiconductor substrate, a voltage applied to the floating gate is lowered and a width of the floating gate is adjusted to reduce an erase error of the flash memory.

The voltage applied to the floating gate may cause the lowest voltage among the voltages of the floating gate in which the flash memory operates.

The voltage across the floating gate may be 3.5 × 10 ¹³ atoms / cm 2.

The width of the floating gate may be 0.230 to 0.255 μm.

The width of the floating gate may be 0.240 μm.

A flash memory operating method according to an exemplary embodiment of the present invention includes a gate oxide film formed on a portion of an upper portion of an element region of a semiconductor substrate, a floating gate formed on the gate oxide film, a dielectric film formed on the floating gate, a control gate formed on the dielectric film, and the semiconductor. In a method of operating a NOR type flash memory including a source / drain region in which impurities are implanted in a device region of a substrate, the lowest voltage among voltage values applied to the floating gate is applied when the flash memory is operated.

The voltage across the floating gate may be 3.5 × 10 ¹³ atoms / cm 2.

The width of the floating gate may be 0.230 to 0.255 μm.

The width of the floating gate may be 0.240 μm.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, the important factors related to erasing from the flash memory are extracted through the following process.

First, we analyzed the error caused by Inline Quality Control (IQC) and PCM (Process Control Monitoring) data, and analyzed the error. Based on the correlation analysis described above, it was confirmed that these factors are important factors. Hereinafter, the improvement direction of the erasing error of the NOR flash memory will be described based on the factors such as the cell voltage and the gate width. The cell voltage is a voltage applied to the floating gate, and the gate width refers to the width of the floating gate in the bit line direction (the direction from the source region to the drain region or vice versa). Hereinafter, it is expressed as a cell voltage or a gate width.

NOR-type flash memory accounts for about 42% of all errors that occur during erasure, and it is recognized as an important part to improve in NOR-type flash memory.

If you look at the types of errors that occur in the erasing phase, you can see the erasing errors caused by the cells not being erased and the over-erasing erasing errors that remain undeleted within a certain time due to the speed of erasing. There is this. These two types of errors exceed 50% of the errors that occur during erasing of NOR flash memory.

In the following, a method of improving the error will be described based on an erasure error and an overtime erasure error.

First, the Erase error is an error that occurs when the cell current flowing in the cell is not recognized as an Erase state. To improve this, it is necessary to increase the cell current, but to increase the cell current under the same conditions, it is necessary to reduce the resistance experienced by the cell current. Since the part of the cell current flows under the floating gate, the length of the part, that is, the gate width, is reduced to reduce the haptic resistance.

On the other hand, since the erase process means lowering the cell voltage to a predetermined level or less, as shown in FIG. 2, the higher the cell voltage, the greater the possibility of erasure error.

This is illustrated graphically in FIG. 4. 4 illustrates a cell erase error according to the cell voltage and the width of the gate. Here, the unit of the cell voltage is atoms / cm 2 to multiply the value by 10 ¹³ to become the corresponding value, and the unit of the gate width is μm.

As can be seen in FIG. 4, the larger the cell voltage, the greater the erasure error. That is, since the erase step is to lower the cell voltage below a certain level, the error increases as the cell voltage increases.

In addition, it can be seen that as the gate width increases, the cell erase error also increases. This is because the resistance value experienced by the cell current increases.

Looking at the graph of FIG. 4 in detail, it can be seen that the change of the cell erase error according to the gate width is larger than the change of the cell erase error according to the cell voltage. That is, it can be confirmed that the cell erase error is more dependent on the gate width than the cell voltage. In addition, as the gate width increases, the erasure error increases. In particular, the erasure error increases rapidly at 0.255 μm or more.

Meanwhile, the source side resistance Rs and the cell current according to the gate width are shown in FIGS. 5 and 6, respectively. Here, the X-axis unit of FIGS. 5 and 6 is μm, the Y-axis unit of FIG. 5 is Ω / cell, and the Y-axis unit of FIG. 6 is ㎂.

As can be seen in FIG. 5, as the gate width increases, the source side resistance Rs also increases. However, the source side resistor Rs is saturated in the 0.255 占 퐉 portion as the gate width increases, and the increase rate of the source side resistor Rs decreases sharply. Accordingly, as shown in FIG. 6, as the gate width increases, the source side resistance Rs increases to increase the resistance of the cell current, thereby decreasing the cell current.

5 and 6, the variation of the source side resistance (Rs) and the cell current according to the gate width can be seen. As a result, as shown in FIG. 4, the cause of the increase in the cell erasure error can be confirmed. have.

Hereinafter, an over time erasure error will be described in a NOR flash memory.

Over time erasure (Erase) error is an error that can not be erased within a certain time due to the slow erase speed.

The Erase rate is deeply related to the tunneling current through which electrons flow out or flow from the floating gate to the substrate, which is proportional to the voltage applied to the floating gate and the area of the tunnel oxide layer.

Reducing the voltage applied to the control gate when the coupling ratio between the control gate and the floating gate is constant increases the power applied to the floating gate, resulting in an increase in the tunneling current, resulting in fast transfer of electrons stored in the floating gate to the substrate. Tunneled. Therefore, the lower the cell voltage, the faster the erase rate and the less the overtime erase error.

In addition, when the gate width is large, the area overlapping with the tunnel oxide is relatively increased, so that more electrons in the floating gate can be tunneled to the substrate in unit time. Therefore, when the cell voltage is low and the gate width is large, the tunneling current is increased to increase the erase speed.

This is illustrated in FIG. 7. Here, the unit of the cell voltage is atoms / cm 2 to multiply the value by 10 ¹³ to become the corresponding value, and the unit of the gate width is μm.

As can be seen in FIG. 7, as the cell voltage increases, the erase speed is lowered, thereby increasing the overtime erase error. In particular, over 3.5 × 10 ¹³ atoms / cm 2 or more and 4.0 × 10 ¹³ atoms / cm 2 or less, the overtime erasure error rapidly increases, but it is found that the increase rate decreases over 4.0 × 10 ¹³ atoms / cm 2 or more.

On the other hand, as the gate width increases, the over time erasure error decreases with a constant slope as shown in FIG. 7.

Therefore, in order to reduce over time erasure error, the cell voltage is preferably low, and the gate width is preferably large.

Combining the results of FIG. 4 representing a cell erasure error and FIG. 7 representing an overtime erasure error are as follows.

In order to reduce the erasure error, as shown in FIG. 4, the cell voltage is preferably low and the gate width is narrow. However, in order to reduce the over time erasure error, as shown in FIG. 7, the cell voltage is preferably low and the gate width is large.

The lower the cell voltage, the lower the cell erasure error and the overtime erasure error, so set the cell voltage to have the lowest value. However, the gate width is trade-off in reducing both erasure and overtime erasure errors. That is, when the gate width is narrow, the erasure error is reduced, but the overtime erasure error is increased. Therefore, the gate width must be determined at a predetermined level. Referring to FIGS. 4 and 7, the following results can be inferred.

Looking at the cell erasure error rate according to the gate width in Figure 4 it can be seen that the error rate is rapidly increased at a value larger than this based on 0.255㎛, in Figure 7, it can be seen that the error rate is changed by a constant slope as a whole.

Therefore, in order to reduce both erasure error and overtime erasure error, it is desirable to be smaller than 0.255 mu m, but not too small. As a result of examining various gate widths based on these criteria, it was confirmed that it was most preferable to have a value of around 0.240 μm.

Therefore, it is desirable to change the cell voltage and gate width to have the values shown in Table 1 in order to reduce the erasure error of the NOR flash memory through this experiment.

As shown in Table 1, the results shown in FIGS. 8 and 9 can be obtained by using a cell voltage and a gate width different from those of the prior art.

As shown in FIG. 8, the erasure error rate is reduced overall by improving the cell voltage and the gate width, and the other error rate is also reduced by 6%, resulting in a large increase in the yield rate. You can see that the yield has improved by 39%.

Meanwhile, FIG. 9 illustrates an Erase error. As shown in FIG. 9, it can be seen that the overall erasure error rate is greatly reduced by improving the cell voltage and the gate width. In particular, when the total error rate before application is 100, the overall error rate after application is 18, which shows a result of reducing the error rate by 82%.

As described above, the erasing error of the NOR flash memory may be reduced by adjusting the cell voltage and the gate width.

In each case, the Erase error, which cannot be erased due to the low cell current, may be controlled by adjusting the cell current by adjusting the resistance of the source and the channel using the gate width. The cell voltage has a smaller effect on the cell erase error than the gate width. However, a lower cell voltage can reduce the erasure error.

In addition, the overtime erasure error, which is an error caused by a slow erase rate, controls the cell voltage and the gate width to increase the tunneling current to move the electrons stored in the floating gate to the substrate in a short time. Can be.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, the cell voltage and the gate width are adjusted to reduce the erasure error and the overtime erasure error, thereby reducing the error occurring in the erasing step in the NOR type flash memory. Can improve the performance.

Claims (9)

A gate oxide film formed on a portion of an upper portion of the device region of the semiconductor substrate; A floating gate formed on the gate oxide layer; A dielectric layer formed on the floating gate; A control gate formed on the dielectric layer; In the NOR-type flash memory including a source / drain region implanted with impurities in the device region of the semiconductor substrate, Flash memory to reduce the erase error of the flash memory by lowering the voltage applied to the floating gate and adjusting the width of the floating gate. In claim 1, And a voltage applied to the floating gate is the lowest voltage among the voltages of the floating gate in which the flash memory operates. In claim 2, And a voltage applied to the floating gate is 3.5 × 10 ¹³ atoms / cm 2. In claim 1, The width of the floating gate is 0.230 to 0.255㎛ flash memory. In claim 4, And a width of the floating gate is 0.240 μm. A gate oxide film formed on a portion of an upper portion of the semiconductor substrate, a floating gate formed on the gate oxide film, a dielectric film formed on the floating gate, a control gate formed on the dielectric film, and impurities are implanted in the device region of the semiconductor substrate In a method of operating a NOR type flash memory including a source / drain region, And operating the flash memory so that the lowest voltage among the voltage values applied to the floating gate is applied. In claim 6, And a voltage across the floating gate is 3.5 × 10 ¹³ atoms / cm 2. In claim 5, The width of the floating gate is 0.230 to 0.255㎛ operating method of the flash memory. In claim 8, Width of the floating gate is 0.240 μm.

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