JP4928019B2 - Method for forming a V-shaped floating gate for a floating gate memory cell - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile digital memory, and more particularly to a flash memory including a novel floating gate having a reduced lateral size.
[0002]
[Prior art]
Flash EPROM memory is a class of non-volatile storage integrated circuits. In general, flash EPROMs have the ability to electrically erase, program, or read memory cells on the chip. In general, a flash EPROM includes a control gate that forms an electrical connection with the footing gate. Flash EPROM operates by charging or discharging electrons in the floating gate of the memory cell in a capacitive manner. The floating gate is formed of a conductive material, typically polysilicon, insulated from the transistor channel by a layer of oxide or other insulating material, and from the transistor word line or control gate by a second layer of insulating material. Insulated.
[0003]
The operation of charging the floating gate is called Aprogram @ Step for the flash EPROM. The program step can be achieved by so-called hot electron injection by setting a large positive voltage between the control gate and the source. The operation of discharging the floating gate is called the erase @ function for the flash EPROM. The erase function is typically performed by an FN tunnel mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the substrate (channel erase).
[0004]
Due to the increasing demand for memory, there is a need to further reduce the size of memory devices such as flash memory. Reducing the cell size of the memory device increases performance and reduces power consumption.
[0005]
Several devices with reduced size have been developed. One such device is described in "High coupling ratio A low voltage operation flash memory cell using horn-shaped floating gate with fine HSG", Kitamura et al. @ 1998 Symposium VLSI Technical Paper Abstract. is there. Examples of other memory devices with reduced cell size are “A0.24-Fm cell process and 3D interpoly dielectric layer with 0.18-Fm width isolation for 1 GB flash memory”, Kobayashi et al. Some are described in IEEE 97-275 (1997).
[0006]
[Problems to be solved by the invention]
When the size of the memory cell is decreased, the memory cell becomes a memory cell having a defect including an excessive floating gate that deteriorates the tunnel oxide layer and an intermediate structure formed in manufacturing the floating gate. If sharp edges are formed in the floating gate, charge leakage occurs.
[0007]
[Means for Solving the Problems]
Embodiments of the present invention provide a floating gate memory cell in which the floating gate includes a first side end region and a second side end region. A central region is located in the central direction of the floating gate with respect to the first side end region and the second side end region. The thickness of the floating gate is continuously reduced from at least one first or second side edge region to the central region.
[0008]
Another embodiment of the present invention provides a floating gate of a floating gate memory cell. The floating gate includes a first polysilicon material deposited in a first manufacturing step to extend from a first side end to a second side end. A second polysilicon material is disposed on the first polysilicon material to form a first tapered sidewall near the first side end and to form a second tapered sidewall near the second side end. Is deposited. A third polysilicon material is deposited in a third manufacturing step so as to cover at least the first or second polysilicon material so as to extend from the first side end to the second side end.
[0009]
For any of the embodiments, the thickness of the floating gate is varied so as to be substantially symmetrical about the central region of the floating gate. The symmetrical distribution of thickness allows a three-dimensional contour that can constitute a floating gate with a minimum thickness centered with respect to the side edge with the maximum thickness.
[0010]
Another variation of the above embodiment is that the first polysilicon material is deposited in the first manufacturing step, the second polysilicon material deposited in the side edge region in the second manufacturing step, and the first polysilicon material deposited in the third manufacturing step. A floating gate formed from 3 polysilicon is provided. As will be further described, the third polysilicon material can be deposited to modify the contour formed from the polysilicon material deposited in the first and second steps.
[0011]
Other variations of the above embodiment include first and second side end regions that are to be formed from first, second, and third polysilicon materials, and a center that is to be published from the first and third polysilicon materials. Area and can be provided.
[0012]
Other variations of the above embodiments can provide first and second side end regions, each having a uniform thickness across the upper surface away from the underlying substrate. The first and second side end regions can also be formed as peaks.
[0013]
The floating gate of the above embodiment is provided in a floating gate memory cell. The floating gate memory cell is disposed on the substrate, the source and drain regions disposed on the substrate, the insulating layer disposed on the source and drain regions, and the insulating layer between the source and drain regions. And a floating gate.
[0014]
The invention also relates to a method of forming a contoured floating gate for use in a floating gate memory cell. One embodiment of the method forms a polysilicon structure between the first alignment structure and the second alignment structure, where the polysilicon structure has a first side region close to the first alignment structure and a second The polysilicon structure has a maximum thickness in the second side end region close to the alignment structure, and the polysilicon structure has a minimum thickness in a central region located between the first side end region and the second side end region. The method further includes forming a polysilicon layer on the polysilicon structure such that the polysilicon layer outlines the polysilicon structure.
[0015]
The method further deposits a first polysilicon layer on the substrate, and on the first polysilicon layer such that the second polysilicon layer has a maximum thickness in the first side edge region and the second side edge region. Forming a polysilicon structure between the first alignment structure and the second alignment structure by depositing a second polysilicon layer.
[0016]
In another embodiment, a first polysilicon layer is deposited on the substrate under the contoured floating gate between the first and second alignment structures, and the first alignment structure, the second alignment structure, And forming a second polysilicon layer over the topography defined by the first polysilicon layer. The method further removes the second polysilicon layer from the first and second alignment structures after depositing the second polysilicon layer on the topography, and the third polysilicon layer outlines the second layer. Forming a third polysilicon layer on the second polysilicon.
[0017]
The method further includes forming a polysilicon structure by removing a portion of the second polysilicon layer from the central region.
[0018]
Another embodiment of the present invention includes forming a polysilicon structure by removing a portion of the first polysilicon layer in a process for removing a portion of the second polysilicon layer from the central region. Including.
[0019]
Another embodiment of the present invention provides for the remainder of the second polysilicon layer to have a sloped thickness that has a maximum thickness in the first side end region and the second side end region. Forming a polysilicon structure by removing a portion of the second polysilicon.
[0020]
The variation of the above embodiment further includes the step of forming a second polysilicon layer from the central region of the polysilicon structure to form a contoured recess that defines a central region of the floating gate having a minimum thickness. Forming a first polysilicon structure by removing the portion.
[0021]
Embodiments of the invention also provide a substrate, forming source and drain regions on the substrate, and forming a floating gate memory cell by depositing an insulating layer on the source and drain regions. Including. The method includes forming a contoured floating gate disposed on an insulating layer between the source and drain regions. The floating gate is formed by the method described above.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
The present invention relates to a flash memory cell design that provides a reduced lateral dimension by incorporating a floating gate into a three-dimensional bonding surface. The contoured bonding surface is made by manufacturing the material to form the floating gate such that the thickness varies across the lateral direction. The floating gate is shaped by the manufacturing process.
[0023]
Embodiments of the present invention provide a floating gate formed from a bottom polysilicon structure having a profile defined by at least two polysilicon layers. The profile has a maximum thickness at the side edges of the floating gate and a minimum thickness at the central bending of the floating gate. Another polysilicon layer is deposited on the bottom polysilicon structure that outlines the bottom polysilicon structure. Each of the polysilicon layers used to form the floating gate can be deposited in a separate manufacturing process. The bottom polysilicon structure can be formed by sequentially depositing first and second polysilicon layers and removing a portion of the second polysilicon layer to form sidewalls at the side edges of the floating gate. A portion of the first polysilicon layer that contacts the substrate under the floating gate can be removed to form a bend or minimum thickness region.
[0024]
In one embodiment of the invention, the thickness of the floating gate increases continuously from the minimum thickness region near the center of the floating gate to the side edge of the floating gate. The floating gate can have regions having the same thickness at each side edge. Alternatively, the thickness of the floating gate can be continuously increased to a peak at the side edges. Here, continuously increasing means that the thickness of the bonding surface always increases as the lateral position on the bonding surface is closer to the side edge or side edge region. However, note that the rate of increase need not always be linear. The structure obtained in the embodiment of the present invention forms a three-dimensional coupling surface that increases the coupling ratio with the control gate.
[0025]
As will be described in detail later, the use of the floating gate of the present invention can provide a smaller performance memory cell comparable to other flash EPROM memory cells known in the industry with larger sizes. Provides important benefits. In particular, the memory cell of the present invention is advantageous in that it is inexpensive to manufacture and prevents charge leakage from the floating gate.
[0026]
FIG. 1 illustrates a memory cell according to the present invention, which is aligned to form a memory array or flash EPROM device. Memory cells in the column share the semiconductor substrate 100. The specific design or configuration of the semiconductor substrate 100 can vary depending on the architecture of the memory device. For example, for the source-drain-source configuration shown in FIG. 4, the semiconductor substrate 100 may be p-type as shown in FIG. An n + type source 114 and an n + type drain region 115 may be distributed on the substrate 100. Preferably, a plurality of alignment structures, here shown as oxide structures 126, are individually encapsulated on the oxidized region 127 of the substrate 100. A plurality of floating gates 120 are formed between the oxide structures 126 such that each floating gate 120 is positioned on a corresponding channel region of the substrate 100. Preferably, the floating gate 120 contacts the oxide structure 126 at the first and second side ends 111 and 113. An insulating layer such as tunnel oxide layer 103 can separate substrate 100, floating gate 120, and possibly oxide structure 126. Preferably, source and drain regions 114 and 115 are substantially located below oxide structure 126, respectively.
[0027]
The floating gate 120 extends in the horizontal word line direction as indicated by the directional arrow 135. Additional floating gates extending in the paper aligned in the bit line direction are not shown. Each floating gate 120 is formed from a polysilicon body having a vertical thickness that is greater than the vertical thickness of the oxide structure 126 in one or more regions. As will be described in detail later, the floating gate 120 is formed from a basic structure 125 that extends between a first side end 122 and a second side end 124. An upper portion 115 having a recessed bonding surface is formed on the base structure 125, and the total thickness of the floating gate 120 is maximized near the side edges 122, 124 and is minimized in the central region. Preferably, the thickness of the floating gate is continuously reduced from a region near the first and second side edges 122, 124 to a minimum thickness of the central baseline 118 located in the central region. Although the thickness of the floating gate 120 is preferably symmetric with respect to the central base line 118, a variation of this embodiment provides the minimum thickness of the floating gate 120 at the base line offset from the center. In one embodiment, as shown in FIG. 2A, three or more polysilicon layers are used in the upper portion outlined with the basic structure.
[0028]
As shown, the memory cell 100 may further include an inter-polysilicon dielectric layer 108 deposited over the oxide structure 126 and the floating gate 120. A third layer 150 of polysilicon is deposited on the inter-polysilicon dielectric layer 108 to form a word line control gate. As a result of the respective shapes of the floating gate 120 and the oxide structure 126, the deposition of the polysilicon layer on the inter-polysilicon dielectric forms an aligned trench on the oxide layer and the floating gate.
[0029]
One advantage of the present invention is to provide a floating gate with increased bonding surface. The increase in the coupling surface directly correlates with the coupling ratio between the floating gate and the control gate, and allows the floating gate to occupy less area on the substrate 100, thereby increasing the overall memory cell. Reduce the size of. Furthermore, the operating voltage of the flash EPROM can be reduced and the circuit can be simplified. Another advantage of reducing the size of the floating gate is that the present invention avoids a floating gate structure that includes an enlarged polywing or a laterally extending floating gate that overlaps the source / drain diffusion region vertically. It can be done. In this way, the cell structure of the present invention can reduce drain coupling ratio and drain leakage while the cell is being programmed. Similarly, the cell structure of the present invention can reduce the source coupling ratio during FN erase operation.
[0030]
The floating gate design used in the present invention is described in detail below. FIG. 2A shows a first embodiment of a flotation gate 220 according to the present invention. In this embodiment, a first polysilicon layer is deposited in a first manufacturing process to form a base 205 that extends from a first side end 222 to a second side end 224. A second polysilicon layer is deposited in separate regions on the first polysilicon layer near the first side edge 222 and the second side edge 224 to form tapered sidewalls near the respective side edges. A third polysilicon layer is deposited on the structure formed by the first and second polysilicon layers to form a contoured surface 225 extending between the first and second side ends 222 and 224.
[0031]
As shown in FIG. 2A, the floating gate 220 can be divided into three regions as it moves from left to right, with respect to the first side end region 201, the second side end region 203, and the side end regions 201 and 203. And a central region 202 located in the lateral direction at the center. In the embodiment of FIG. 2A, the thickness of the central region 202 includes a first layer of polysilicon and a third layer of polysilicon. The thickness of the side edge regions 211 and 213 includes the first, second and third layers of polysilicon.
[0032]
In one embodiment, the thickness of the base structure 205 varies to provide in part a contoured recess 262 having a minimum thickness region 264. The varying thickness of the base 205 forms a bend in the depression of the floating gate located at the center of the floating gate 220. Tapered sidewalls 215, 215 'formed by the second polysilicon layer are the largest on the first polysilicon layer and the smallest at the apex or the surface of the floating gate on the first and second side edges 222, 224. Is defined by the horizontal length. A third polysilicon layer is deposited on the first and second polysilicon layers and extends between the side edges 222, 224 and into the contoured recess 262 of the base structure 205. The third polysilicon layer outlines the polysilicon structure formed by the first and second layers of polysilicon. In this way, the first, second, and third polysilicon layers are combined so that the thickness of the floating gate 220 continuously increases from the central region to the first and second side end regions 201 and 203. Is done. The resulting bonding surface 225 is defined by the thickness profile of the floating gate 220 where the thickness profile slope between the bend region and each side edge region is between 0 and 90 degrees.
[0033]
In FIG. 2A, the side edge regions 201 and 203 may be formed of a third polysilicon layer so as to have a relatively uniform thickness in order to form a plateau 280 parallel to the underlying substrate. The third polysilicon layer also forms an inner surface 282 having a contour defined by the sidewalls of the second polysilicon layer and the depressions of the first polysilicon layer. The floating gate includes a boundary surface 284 to each oxide structure perpendicular to the substrate 100. Preferably, the junction of plateau 280 and inner surface 282 forms an angle that is less than 90 degrees. In one embodiment, each plateau 280 and boundary surface 284 may form a 90 degree angle.
[0034]
FIG. 2B shows a second embodiment of a floating gate according to the present invention, which is provided with pointed or peaked side edges. As shown, the first, second and third polysilicon layers such that the thickness of the floating gate 220 increases continuously from the minimum thickness 264 ′ to the first and second side edges 217 and 219. Are combined. The resulting bonding surface 225 'is the thickness of the floating gate 220 where the thickness profile slope between each of the minimum thickness region 264 and the side edges 222, 224 is between 0 and 90 degrees. Defined by the profile. The thickness profile outlines the coupling surface to increase the coupling length of the floating gate between the first and second side edges.
[0035]
FIG. 2C shows another embodiment in which the floating gate has a contoured coupling surface. In this embodiment, a first polysilicon layer is deposited in a first manufacturing process to form a base structure 205 that extends from a first side end 222 to a second side end 224. A second polysilicon layer is deposited on the first polysilicon layer so as to extend continuously between the first and second side edges 222 and 224. A second polysilicon layer is deposited to form a maximum thickness region near each side edge and a minimum thickness region 264 "over the central region of the floating gate. As a result of the second polysilicon layer. The resulting topography will have a thickness of the second polysilicon layer extending continuously over the base 205 to form tapered sidewalls 215, 215 'near the respective side edges 222 and 224. Third poly A silicon layer is deposited on the second polysilicon layer to form a contoured bonding surface 225 "extending between the first and second side edges 222 and 224. In the embodiment of FIG. 2C, the first layer of polysilicon has a substantially uniform thickness between the first and second side edges 222 and 224.
[0036]
3A to 3I show a first embodiment for manufacturing a memory cell according to the present invention, more specifically, an array of floating gates. As shown in FIG. 3A, a relatively thin tunnel oxide layer 303 is grown on the substrate 300, preferably about 100 angstroms thick. In the embodiment as shown in FIG. 4, the substrate comprises a p-type substrate. Next, a conductive layer for forming a floating gate such as the first polysilicon layer 304 is deposited on the tunnel oxide layer 303. Silicon nitride (Si _Three N _Four An insulating or masking layer 306 made of a material such as) is sequentially deposited on the first polysilicon layer 304. The masking layer 306 can be formed on the tunnel oxide layer 303 by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).
[0037]
As shown in FIG. 3B, the first polysilicon layer 304 and the masking layer 306 are etched away to form a pattern of spaced polysilicon-nitride pillars 330 on the substrate 300. Preferably, the pillar 330 is defined by a photomasking process. In this step, dopant can be used to create diffusion regions 314 and 315 between pillars 330. This can be done using conventional ion implantation methods, although chemistry or other similar processes can be used. A dopant used to create a diffusion region such as arsenic (As) is implanted into the substrate 300.
[0038]
FIG. 3C shows an oxide structure 326 deposited between individual polysilicon-nitride columns 330. Next, the polysilicon-nitride pillars 330 and the oxide layer 326 are planarized, preferably by chemical mechanical polishing (CMP). Planarization causes the oxide structure 326 to be flush with the masking layer 306 of the pillar 330 relative to the horizontal plane. Another method for planarizing the oxide structure 326 and the masking layer 306 includes etching the oxide structure to be flush with the masking layer 306. The oxide structure 326 serves to insulate the polysilicon layer 304 from electron leakage, while also providing an alignment structure that determines the height of subsequent polysilicon deposition (shown in FIG. 3D). In this way, the height of the oxide structure 326 can be used to determine the overall height of the floating gate. The oxide structure 326 can be deposited on the substrate 300 by a number of methods including LPCFD, PECVD, and high density plasma CVD (HDPCVD).
[0039]
As shown in FIG. 3D, the masking layer 306 is removed from the pillars 330 by a wet etch process to expose the first polysilicon layer 304 between the oxide structures 326. The resulting structure has a step topography and forms an alignment structure for subsequent deposition of additional polysilicon layers.
[0040]
Next, FIG. 3E shows a second layer of polysilicon 324 deposited over the first polysilicon layer 304 and oxide 326. The second polysilicon layer 324 extends continuously over the oxide structure 326 and the first polysilicon layer 304. Using the oxide structure 326 for alignment, the first and second polysilicon layers 304 and 324 are thickest at the side edges of the floating gate. A second polysilicon layer 324 can be used to profile a floating gate for a third polysilicon layer that is subsequently deposited. Although FIG. 3E shows that the second polysilicon layer 324 is deposited to form an acute angle of 90 degrees, the second polysilicon layer 324 can be deposited to form a more rounded corner. The rounded corners are formed by depositing the second polysilicon layer 324 in a more slowly mixed manner so that its thickness matches the topography of the first polysilicon layer 304 and the oxide structure 326.
[0041]
As shown in FIG. 3F, the second polysilicon layer 324 is removed from the top of the oxide layer 326, preferably by a chemical mechanical polishing (CMP) process. Alternatively, if a thin film is used to separate the first polysilicon layer from the second polysilicon layer 324, the second polysilicon layer 324 can be etched away. The second polysilicon layer 324 has raised end 334 with increased thickness near the oxide structure 326. Preferably, the space defined by the oxide structure 326 is a rectangular depression.
[0042]
FIG. 3G shows the remaining portion of the second layer 324 of polysilicon that has been removed to form a graded cavity between the oxide structures 326, as well as a portion of the first layer of polysilicon 304. FIG. Preferably, the first layer 304 and the second layer 324 of polysilicon are removed simultaneously by a spacer etch. An intermediate floating gate structure is formed between the oxide structures 326 and is formed by a first layer 304 of polysilicon having tapered sidewalls 332 spaced closely opposite each oxide structure 326. Have a base.
[0043]
FIG. 3H shows a third polysilicon layer 327 deposited on the oxide layer 326. A third polysilicon layer 327 is deposited on the second and first polysilicon layers 324 and 304. In a preferred manufacturing method, a third polysilicon layer 327 is also deposited on the oxide structure 326. Between the pair of oxide structures 326, the third polysilicon layer 327 is tilted along the shape formed by the first and second polysilicon layers 304 and 324. In this way, sharp corners and angles can be avoided by depositing the third polysilicon layer 327.
[0044]
As shown in FIG. 3I, another CMP step is performed on the top surface of the oxide structure 326 from which the third polysilicon layer 327 is removed. Alternatively, the third polysilicon layer 327 can be removed by dry etching if a thin film is used to separate the second polysilicon layer 324 from the third polysilicon layer 327.
[0045]
FIG. 3J shows the oxide structure 326 partially removed to allow the polysilicon structure to extend vertically beyond the oxide structure 326. Part of the oxide structure can be removed by a dipping process. In the resulting floating gate, the thickness of the side edge near the oxide structure 326 is greater than the others of the floating gate. The thickness of the floating gate decreases continuously to the central region of the floating gate.
[0046]
As shown in FIG. 3K, an interpolysilicon dielectric layer 308 is deposited over the third polysilicon 327 and the nearby oxide structure 326. A preferred interpolysilicon dielectric material is ONO. SiO ₂ Other materials such as are also suitable. In one embodiment, the ONO layer includes high temperature oxides deposited by CVD, CVD nitride, and other high temperature oxides deposited by CVD. In an exemplary embodiment, the first oxide layer is 62 angstroms thick, the nitride layer is 62 angstroms thick, and the bottom oxide layer is 45 angstroms thick. After the deposition of the second dielectric layer, the second polysilicon layer 427 and WSI that combine to form the control gate _x 474 deposition continues.
[0047]
FIG. 3L shows a fourth layer 360 of polysilicon deposited as word line gate control. The floating gate formed by the method of the present invention is combined with the control gate to form a memory using techniques known in the art.
[0048]
FIG. 4 shows the drain-source-drain configuration of a flash EPROM circuit according to the present invention. The circuit includes a first local bit line 410 and a second local bit line 411. The first and second local bit lines 410 and 411 are constituted by buried diffusion conductors as described below. A local virtual ground line 412 constituted by buried diffusion is also included. The plurality of floating gates, drains and sources are connected to local bit lines 410 and 411 and a local virtual ground line 412. The sources of the plurality of transistors are coupled to the local virtual ground line 412. The drain of the first column of transistors, generally designated 413, is coupled to the first local bit line 410, and the drain of the second column of transistors, generally designated 414, is coupled to the second local bit line 411. The gate of the floating gate transistor is the word line WL ₀ To WL _N Where each word line (eg WL ₁ ) Is connected to the gates of the transistors in the second column 414 (eg, transistor 416). Thus, transistors 415 and 416 can be viewed as one two-transistor cell with a shared source diffusion.
[0049]
As shown in FIG. 4, a first global bit line 417 and a second global bit line 418 are associated with each drain-source-drain block. First global bit line 417 is coupled to the source of upper block select transistor 419 via metal-diffusion contact 420. Similarly, the second bit line 418 is coupled to the source of the upper block select transistor 421 via a metal-diffusion contact 422. The drains of the upper block select transistors 419 and 421 are coupled to the first and second local bit lines 410 and 411, respectively. The gates of the upper block selection transistors 419 and 421 are controlled by the upper block selection signal TBSEL on the line 423.
[0050]
The local virtual ground line 412 is coupled to the virtual ground terminal across the conductor 424 via the bottom block select transistor 425. The drain of bottom block select transistor 425 is coupled to local virtual ground line 412. The source of bottom block select transistor 425 is coupled to lead 424. The gate of the bottom block select transistor 425 is controlled by a bottom block select signal BBSEL across line 426. In the preferred system, the lead 424 is an embedded diffusion conductor that extends to a metal-diffusion contact in a position moved horizontally through the array to provide a contact to a vertical metal virtual ground bus.
[0051]
The global bit lines extend vertically to the column selection transistors 427 and 428, respectively, through the array, and the selected global bit line is coupled to a sense amplifier and a program data circuit (not shown). In this way, the source of the column selection transistor 427 is coupled to the global bit line 417, and the gate of the column selection transistor 427 is connected to the column decode signal Y. ₁ And the drain of column select transistor 427 is coupled to conductor 429.
[0052]
Other memory array device architectures can also be used with the present invention. For example, US Pat. No. 5,696,019 to Chang discloses a memory device architecture suitable for the present invention that includes a plurality of columns of memory sharing one or more bit lines. This architecture is based on a source / drain cell configuration where each column of cells has a single embedded diffuse local source line. An insulating structure such as trench oxide is located between each column of cells.
[0053]
Memory cell operation can be accomplished in one of several ways. In this embodiment, the memory cell is programmed by applying a second positive voltage valve to the drain diffusion embedded with the first positive voltage value at the control gate, while bringing the embedded n-type source diffusion to zero volts. . Under these conditions, electrons can tunnel from the charged band to the conductive band, leaving free holes in the charged band. The voltage at the control gate attracts electrons toward the floating gate. The electrons are accelerated by a strong vertical electric field between the drain diffusion and the control gate and are sufficient to be injected into the floating gate 120 (FIG. 1) via the tunneling dielectric layer 106 (shown in FIG. 1). Become a “hot” electron.
[0054]
Erasing is accomplished by FN tunneling from the floating gate to the buried n-type source diffusion region. During erase, a negative voltage is applied to the control gate, a positive voltage is applied to the source diffusion, and the drain is floated. As a result, FN tunneling erasure of electrons from the floating gate to the source side occurs.
[0055]
In another variant, FN tunneling programming (electron tunneling from the floating gate to the drain side via FN tunneling) and channel erasure (channel to floating gate via FN tunneling). E) can be used. Furthermore, the memory cell also has FN tunneling programming (electrons from the channel to the floating gate via FN tunneling) and FN channel erasure (electrons by FN tunneling from the floating gate to the channel). Can be used.
[0056]
Reading can be accomplished by applying a positive voltage to the drain diffusion and a positive voltage to the control voltage, with the source at zero volts. When the floating gate is charged, the threshold voltage for making the n-channel transistor conductive during reading decreases below the voltage applied to the control gate. Thus, during a read operation, charged transistors are not conducting and uncharged transistors are conducting. The non-conductive state of the cell is interpreted as a binary value 1 or 0 depending on the polarity of the detection circuit.
[0057]
The voltage required for programming, erasing, and / or reading operations depends in part on the coupling ratio between the control gate and the floating gate of the memory cell. The voltage across the floating gate is characterized by:
[0058]
V _FG = V _CG [C _CR / (C _CR + C _K ]]
Where C _CR Is the capacitive coupling ratio between the floating gate and the control gate. Factor C _K Represents the capacitive coupling of the floating gate across the tunnel oxide layer 206 for programming, erasing or reading. In the above equation, the higher the coupling ratio between the floating gate and the control gate, the more equal the voltage across the floating gate compared to the voltage across the control gate. Thus, increasing the coupling ratio between the floating gate and the control gate reduces the voltage required to program, erase, or read.
[0059]
Some prior art memory devices provide a floating gate with a larger coupling surface to increase the coupling ratio between the control gate and the floating gate. In the past, this was achieved by increasing the lateral size of the floating gate on the substrate. Thus, prior art floating gates occupy a large percentage of the area allocated to the memory array device. In contrast, the present invention provides comparable floating gates with reduced lateral dimensions. In particular, the present invention provides a floating gate having a reduced lateral dimension but having the same or increased coupling ratio between the control gate and the floating gate.
[0060]
The foregoing description of the preferred embodiment of the present invention has been made for purposes of illustration and description. There is no intention to limit the invention to the precise form disclosed. There are many modifications and variations that will be apparent to those skilled in the art. The scope of the present invention is defined by the appended claims and their equivalents.
[Brief description of the drawings]
FIG. 1 shows a memory cell according to the present invention.
FIG. 2A is a diagram showing a floating gate according to an embodiment of the present invention.
FIG. 2B illustrates a floating gate including a side edge having a sloped thickness according to another embodiment.
FIG. 2C illustrates a floating gate including a thickness extending over a floating gate including at least three polysilicon layers according to another embodiment of the present invention.
FIGS. 3A to 3I illustrate an embodiment of a method of manufacturing a memory cell according to the present invention, and FIG. 3A includes a tunnel oxide layer, a polysilicon layer, and a masking layer grown on a substrate. The figure which shows a semiconductor structure.
FIG. 3B shows a polysilicon layer and a masking layer etched to form a column pattern.
FIG. 3C illustrates an oxide structure deposited between columns such that each column is in contact with the oxide structure.
FIG. 3D shows the masking layer removed to create a step tomography between the oxide structure and the polysilicon layer.
FIG. 3E shows a second polysilicon layer deposited on the step tomography including columns and oxide structures.
FIG. 3F illustrates a second polysilicon layer etched to selectively remove all of the second polysilicon layer over the oxide structure.
FIG. 3G shows further etching of the second polysilicon layer.
FIG. 3H shows deposition of a third polysilicon layer.
FIG. 3I is a view showing etching of a third polysilicon layer.
FIG. 3J shows the oxide structure removed to shorten the top surface of the oxide structure and to form a contoured top or bonding surface in the top portion of the combined polysilicon layer.
FIG. 3K illustrates an oxide structure and a dielectric layer deposited over a polysilicon layer.
FIG. 3L illustrates the completion of a memory cell with the deposition of another polysilicon layer on the dielectric layer.
FIG. 4 is a circuit diagram of a nonvolatile memory device in which the present invention can be used.

Claims (16)

A method of forming a floating gate in a floating gate memory, comprising:
The floating gate is
A first side end region and a second side end region;
A central region located in the central direction of the floating gate with respect to the first side end region and the second side end region, and the method comprises:
Forming a first polysilicon material;
Forming a second polysilicon material on the first polysilicon material;
Removing a portion of the second polysilicon material to expose a portion of the first polysilicon material in the central region, and leaving a side portion of the second polysilicon material;
Forming a third polysilicon material over the exposed first polysilicon material and the remaining second polysilicon material; and
A method wherein the thickness of the floating gate is continuously reduced from at least one of the first and second side end regions to the central region.   The method of claim 1, wherein the thickness of the floating gate is symmetrical about the central region of the floating gate. The floating gate
A first manufacturing step of depositing a first polysilicon material;
A second manufacturing step of depositing a second polysilicon material in the side edge region;
3. The method of claim 2, wherein the method is formed from a third manufacturing step of depositing a third polysilicon material.   4. The method of claim 3, wherein the first and second side edge regions are formed from first, second and third polysilicon materials and the central region is formed from first and third polysilicon materials.   The method of claim 1, wherein the first and second side edge regions form a peak. A method of forming a floating gate in a floating gate memory cell comprising:
The floating gate is
A first side end and a second side end;
A central region located in the center direction of the floating gate with respect to the first side end and the second side end;
A first manufacturing step of depositing a first polysilicon material so as to extend from the first side end to the second side end;
Near the first side end of the first polysilicon material, a first side wall tapered toward the central region and a second side wall tapered near the second side end toward the central region. a second manufacturing step of the side wall is formed, depositing a second polysilicon material on the first poly-silicon material,
A third manufacturing step of depositing a third polysilicon material on at least the first or second polysilicon material so as to extend from the first side end to the second side end;
A method characterized by comprising:   The method of claim 6, wherein a third polysilicon material is deposited on the second polysilicon layer so as to outline the second polysilicon layer.   The method of claim 6, wherein the thickness of the floating gate is symmetric about a central region of the floating gate. A method of forming a floating gate memory cell comprising:
The floating gate memory cell is
A substrate,
Source and drain regions located on the substrate;
An insulating layer placed over the source and drain regions;
A floating gate placed on the insulating layer between the source and drain regions,
The floating gate has a first side end region and a second side end region;
A central region located in the central direction of the floating gate with respect to the first side end region and the second side end region, and
The method
Forming a first polysilicon material;
Forming a second polysilicon material on the first polysilicon material;
Removing a portion of the second polysilicon material to expose a portion of the first polysilicon material in the central region, and leaving a side portion of the second polysilicon material;
Forming a third polysilicon material over the exposed first polysilicon material and the remaining second polysilicon material; and
A method wherein the thickness of the floating gate is continuously reduced from at least one of the first and second side end regions to the central region.   The method of claim 9, wherein the thickness of the floating gate is symmetric about a central region of the floating gate. The floating gate
A first manufacturing step of depositing a first polysilicon material;
A second manufacturing step of depositing a second polysilicon material in the side edge region;
The method of claim 10, wherein the method comprises forming a third manufacturing step of depositing a third polysilicon material.   12. The first and second side end regions are formed from first, second and third polysilicon materials, and the central region is formed from first and third polysilicon materials. The method described.   The method of claim 9, wherein the first and second side edge regions form a peak. A method of forming a floating gate memory cell comprising:
A substrate,
Source and drain regions located on the substrate;
An insulating layer located on the source and drain regions;
A floating gate located on an insulating layer between the source and drain,
The floating gate is
A first side end and a second side end;
A central region located in the center direction of the floating gate with respect to the first side end and the second side end;
The floating gate
A first manufacturing step of depositing a first polysilicon material so as to extend from the first side end region to the second side end region;
Near the first end of the first poly-silicon material, a first side wall that is tapers toward the central area, and, in the vicinity of the second side edge, assigned a taper toward the central region Forming a second sidewall and depositing a second polysilicon material on the first polysilicon material;
A third manufacturing step of depositing a third polysilicon material on at least the first or second polysilicon material so as to extend from the first side end to the second side end.   15. The method of claim 14, wherein a third polysilicon layer is deposited on the second polysilicon layer so as to outline the second polysilicon layer.   The method of claim 14, wherein the thickness of the floating gate is symmetric about a central region of the floating gate.

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