KR20070031678A - Semiconductor memory device and method for fabricating the same - Google Patents

Abstract

A semiconductor memory device and a method of manufacturing the same are provided. The semiconductor memory device is formed on a contact pad formed in a first interlayer insulating film, a first interlayer insulating film, a second interlayer insulating film having a bit line formed thereon, a third interlayer insulating film formed on a second interlayer insulating film forming bit lines, A fourth interlayer insulating film formed of a material having a lower wet etching rate than the third interlayer insulating film and having a relatively flat upper surface, a contact plug formed in the second to fourth interlayer insulating films and electrically connected to the contact pad, and the fourth interlayer insulating film And a landing pad to increase the top area of the contact plug.

Landing pad, wet etch rate, micro bridge

Description

Semiconductor memory device and method for manufacturing the same {Semiconductor memory device and method for fabricating the same}

1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention.

2 to 6 are cross-sectional views of respective semiconductor memory device manufacturing process steps in accordance with an embodiment of the present invention.

<Explanation of symbols on main parts of the drawings>

100 semiconductor substrate 110 first interlayer insulating film

112: contact pad 120: second interlayer insulating film

130: bit line 140: third interlayer insulating film

150: fourth interlayer insulating film 162, 164: contact hole

170: conductive film 172: contact plug

174: landing pad

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device capable of preventing micro bridges between landing pads and a method of manufacturing the same.

As the degree of integration of a semiconductor memory device increases, the size of the contact hole for connecting the device and the device or the layer and the layer decreases while the thickness of the interlayer insulating film increases. Therefore, the aspect ratio of the contact hole is increased to reduce the alignment margin of the contact hole during the photolithography process. Accordingly, a landing pad is used to extend the contact area between the lower conductive layer and the upper conductive layer. In particular, the landing pad is used to prevent capacitor collapse of the DRAM device and is connected to a buried contact at the bottom.

However, when forming a buried contact for connecting the impurity region and the storage node, wet etching is performed on the substrate on which the contact hole is formed after the contact hole is formed to increase the contact area between the impurity region and the buried contact below. Therefore, the contact hole upper portion is formed in a round shape. Then, a conductive material is deposited in the contact hole of this type, and then a photolithography process is performed to simultaneously form a buried contact and a landing pad. At this time, the contact hole upper profile is formed to be rounded to generate a micro bridge between landing pads.

Accordingly, an aspect of the present invention is to provide a semiconductor memory device capable of preventing micro bridges between landing pads.

Another object of the present invention is to provide a method of manufacturing such a semiconductor memory device.

The technical problem to be achieved by the present invention is not limited to the above-mentioned problem, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, a semiconductor device according to an exemplary embodiment of the present invention may include a contact pad formed in a first interlayer insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer and a bit line formed thereon. A third interlayer insulating film formed on the formed second interlayer insulating film, a fourth interlayer insulating film formed of a material having a lower wet etching rate than the third interlayer insulating film, and having a relatively flat upper surface, and formed in the second to fourth interlayer insulating films And a landing pad disposed on the contact plug and the fourth interlayer insulating layer electrically connected to the pad, wherein the landing pad increases a top area of the contact plug.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor memory device, the method including: forming a second interlayer insulating layer on a first interlayer insulating layer on which contact pads are formed, and forming a bit line on the second interlayer insulating layer Forming a third interlayer insulating film filling the bit line; forming a fourth interlayer insulating film formed of a material having a wet etching rate lower than that of the third interlayer insulating film on the third interlayer insulating film; Forming a contact hole exposing the contact pad by partially dry etching the interlayer insulating film, wet etching the second to fourth interlayer insulating films, but forming a relatively flat top surface of the fourth interlayer insulating film, and extending the width of the contact hole. And contact plugs electrically connected to the contact pads in the contact holes having a wider width and on the fourth interlayer insulating film. Sex and includes forming a landing pad to expand the upper area of the contact plug.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

A semiconductor memory device and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to FIGS. 1 to 6 as follows.

1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention.

As illustrated in FIG. 1, a first interlayer insulating layer 110 including a contact pad 112 is positioned on the semiconductor substrate 100. The contact pad 112 is formed of a conductive material such as polysilicon doped with a high concentration of impurities or a metal material, and is electrically connected to an impurity region (not shown) formed in the semiconductor substrate 100. A gate electrode (not shown) is formed between the contact pads 112.

The second interlayer insulating layer 120 is formed on the first interlayer insulating layer 110, and the impurity regions (not shown) in the bit line 130 and the semiconductor substrate 100 are formed in the second interlayer insulating layer 120. Bit line contact plugs (not shown) for electrical connection are formed. The bit line 130 is formed on the bit line contact plug (not shown) in the second interlayer insulating layer 120.

A third interlayer insulating layer 140 is positioned on the bit line 130, and a fourth interlayer insulating layer 150 having a wet etching rate different from that of the third interlayer insulating layer 140 is positioned on the third interlayer insulating layer 140. In the second to fourth interlayer insulating layers 120, 140, and 150, contact plugs 172 connected to the contact pads 112 positioned in the first interlayer insulating layer 110 are formed. In this case, the contact plug 172 is an enclosed buried contact having an enlarged area in contact with the lower contact pad 112.

In detail, when the contact plug 172 is formed, the fourth interlayer insulating layer 150 is formed of a material having a lower wet etching rate than the third interlayer insulating layer 140 to prevent the upper portion from being rounded. . Therefore, the upper portion of the fourth interlayer insulating layer 150 including the upper portion of the contact plug 172 is formed to be relatively flat.

A landing pad 174 is formed on the fourth interlayer insulating layer 150 to extend a contact area between the storage node of the capacitor to be electrically connected to the contact plug 172 and the contact plug 172. In this case, since the landing pad 174 is positioned on the contact plug 172 and the fourth interlayer insulating layer 150 formed relatively flat, the fourth interlayer insulating layer 150 is rounded to form the fourth interlayer insulating layer 150. The conductive material may remain on top to prevent the microbridges from occurring between the landing pads 174.

Hereinafter, a method of manufacturing a semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to FIGS. 2 to 6.

2 to 6 are cross-sectional views of respective semiconductor memory device manufacturing process steps in accordance with an embodiment of the present invention.

First, as shown in FIG. 2, a gate electrode (not shown) is formed on the semiconductor substrate 100, and an ion implantation process is performed in the semiconductor substrate 100 on both sides of the gate electrode (not shown) to form an impurity region ( Not shown). As described above, an insulating material is deposited on the semiconductor substrate 100 on which the gate electrode (not shown) and the impurity region (not shown) are formed. Then, the first interlayer insulating layer 110 is formed by planarizing the upper portion by performing a chemical mechanical polishing (CMP) or etch back process.

In addition, a normal photolithography process is performed on the first interlayer insulating layer 110 to form a contact hole exposing an impurity region (not shown) in the semiconductor substrate 100. When forming the contact hole in the first interlayer insulating film 110 made of oxide, the contact holes are self-aligned with respect to the gate electrode (not shown) by using an etching gas having a high etching selectivity with respect to the gate electrode (not shown). (self alignment) to expose an impurity region (not shown) in the semiconductor substrate 100.

Next, a conductive film is formed by depositing a conductive material or a metal material such as polysilicon doped with a high concentration of impurities filling the contact hole on the entire surface of the first interlayer insulating film 110 on which the contact hole is formed. Subsequently, the conductive layer is planarized until the upper portion of the first interlayer insulating layer 110 is exposed to form a self-aligned contact pad 112 in the first interlayer insulating layer 110.

Next, an insulating material is deposited and planarized on the first interlayer insulating layer 110 including the contact pad 112 to form a second interlayer insulating layer 120. Then, a bit line contact hole is formed in the second interlayer insulating layer 120, and a conductive material is deposited and planarized to form a bit line contact plug (not shown) in the second interlayer insulating layer 120. In this case, the bit line contact plug (not shown) is selectively connected to the contact pad 112 located in the first interlayer insulating layer 110.

A bit line 130 is formed on the second interlayer insulating layer 120 to be connected to a bit line contact plug (not shown) in the second interlayer insulating layer 120. In detail, the bit line 130 may have a structure in which the diffusion barrier 132, the metal layer 134, and the insulating layer 136 are stacked. Spacers 138 are formed on the sidewalls. In this case, the diffusion barrier 132 may be formed of a titanium / titanium nitride layer (Ti / TiN), and the metal layer 134 may be formed of a tungsten layer (W). The insulating film 136 and the spacer 138 may be formed of a nitride film. Alternatively, the bit line 130 may be formed of polysilicon doped with a high concentration of impurities instead of the diffusion barrier 132 and the metal layer 134.

As such, after forming the bit line 130 on the second interlayer insulating layer 120, as shown in FIG. 3, an insulating material for filling the bit line 130 is deposited and planarized on the entire surface to form a third interlayer insulating layer ( 140). In this case, the third interlayer insulating layer 140 may be formed of silicon oxide such as borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or undoped silicate glass (USG).

The fourth interlayer insulating layer 150 is formed by depositing and planarizing an insulating material having a lower wet etching rate than the third interlayer insulating layer 140 on the third interlayer insulating layer 140. In this case, the fourth interlayer insulating layer 150 may be formed of a nitride film and smaller than the thickness of the third interlayer insulating layer 140.

Next, as shown in FIG. 4, the photoresist pattern 155 is formed on the fourth interlayer insulating layer 150, and the second to fourth interlayer insulating layers are formed using the photoresist pattern 155 as an etching mask. 120, 140, 150) in turn dry etching. Accordingly, a narrow contact hole 162 exposing the lower contact pad 112 is formed. Since the contact hole 162 formed as described above has a small width for exposing the lower contact pad 112, the contact hole 162 may be wet-etched to expand the width for exposing the contact pad 112.

That is, after removing the photoresist pattern 155 on the fourth interlayer insulating layer 150, a wet etching process is performed on the entire surface of the semiconductor substrate 100 on which the first contact holes 162 are formed. Therefore, as shown in FIG. 5, an extended contact hole 164 exposing the contact pad 112 is formed. As such, when the wet etching process is performed, the fourth interlayer insulating layer 150 has a lower wet etching rate than the lower third interlayer insulating layer 140, so that the contact hole 112 having an extended width exposing the contact pad 112 is formed. The upper width of 164 may not extend. In addition, an upper surface of the fourth interlayer insulating layer 150 connected to the contact hole 164 having the width exposing the contact pad 112 may be formed to be relatively flat.

 As such, after forming the contact hole 164, a conductive material for filling the contact hole 164 is deposited on the fourth interlayer insulating layer 150 to form the conductive film 170. In this case, polysilicon containing a high concentration of impurities may be used as the conductive material.

Thereafter, the conductive film 170 is subjected to a normal photolithography process to complete the contact plug 172 and the landing pad 174 as shown in FIG. 1. In this case, the contact plug 172 is formed in the contact hole (see 164 of FIG. 6), and the landing pad 174 is formed on the contact plug 172 and the fourth interlayer insulating layer 150. Therefore, the area electrically connected to the contact plug 172 by the landing pad 174 is increased.

In addition, since the landing pad 174 is positioned on the fourth interlayer insulating layer 150 formed relatively flat, the conductive material remains on the fourth interlayer insulating layer 150 to prevent the microbridges from occurring between the landing pads 174. can do. That is, the bridge between the contact plugs 172 can be prevented.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the semiconductor memory device and a method of manufacturing the same, a contact hole is formed by forming an exposed region of a contact pad on an interlayer insulating layer having a lower wet etching rate than an interlayer insulating layer disposed below when forming an extended contact hole. The upper surface of the interlayer insulating film can be formed relatively flat.

Therefore, when the contact plug and the landing pad are formed, the conductive material may remain on the interlayer insulating layer to prevent the microbridges from occurring between the landing pads.

Claims (10)

A contact pad formed in the first interlayer insulating film; A second interlayer insulating layer formed on the first interlayer insulating layer and having a bit line formed thereon; A third interlayer insulating film formed on the second interlayer insulating film on which the bit line is formed; A fourth interlayer insulating layer formed of a material having a wet etching rate lower than that of the third interlayer insulating layer and having a relatively flat upper surface; A contact plug formed in the second to fourth interlayer insulating layers and electrically connected to the contact pad; And And a landing pad positioned on the fourth interlayer insulating layer, the landing pad increasing an upper area of the contact plug. The method of claim 1, And the bit line is selectively connected to the contact pad. The method of claim 1, And the fourth interlayer insulating film has a thickness smaller than that of the third interlayer insulating film. The method of claim 1, The third interlayer insulating film is an oxide film. The method of claim 1, And the fourth interlayer insulating film is a nitride film. Forming a second interlayer insulating film on the first interlayer insulating film on which contact pads are formed; Forming a bit line on the second interlayer insulating film, and forming a third interlayer insulating film filling the bit line; Forming a fourth interlayer insulating layer on the third interlayer insulating layer, the fourth interlayer insulating layer formed of a material having a wet etching rate lower than that of the third interlayer insulating layer; Partially dry etching the second to fourth interlayer insulating films to form contact holes exposing the contact pads; Wet etching the second to fourth interlayer insulating layers to form a relatively flat top surface of the fourth interlayer insulating layer, and to expand the width of the contact hole; And Forming a contact plug electrically connected to the contact pad and a landing pad formed on the fourth interlayer insulating layer and extending a top area of the contact plug in the width of the contact hole; Way. 7. The method of claim 6, prior to forming the bit line, And selectively connecting the bit line with the contact pad in the second interlayer insulating film. The method of claim 6, And the fourth interlayer insulating film is formed to a thickness smaller than the thickness of the second interlayer insulating film. The method of claim 6, And the third interlayer insulating film is formed of an oxide film. The method of claim 6, And the fourth interlayer insulating film is formed of a nitride film.

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