KR20070025002A - Dual gate of semiconductor device and method for forming the same - Google Patents

Abstract

A dual gate of a semiconductor device and its forming method are provided to improve the reliability of the semiconductor device by restraining boron ions of a polysilicon layer from diffusing into a metal film using a diffusion barrier made of a Ti-B mixed layer. A gate insulating layer(112) is formed on a substrate(110). A first conductive layer(114) and a second conductive layer(124) are sequentially formed on the gate insulating layer. A diffusion barrier(120) is interposed between the first and the second conductive layers. The diffusion barrier is made of a Ti-B mixed layer. The diffusion barrier is used for restraining predetermined ions of the first conductive layer from diffusing into the second conductive layer.

Description

Dual gate of semiconductor device and its formation method {DUAL GATE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME}

1 is a cross-sectional view showing a dual gate of a semiconductor device according to the prior art.

FIG. 2 is a result of comparing Capacitive-Voltage (CV) characteristics between an N ⁺ polysilicon gate electrode and a P ⁺ gate electrode (or NMOS and PMOS) in the dual polysilicon gate shown in FIG. 1.

3 is a test result of the diffusion profile of boron doped to the gate electrode made of TiSi.

4 is a cross-sectional view illustrating a dual gate of a semiconductor device according to a preferred embodiment of the present invention.

5A through 5D are cross-sectional views illustrating a method of forming a dual gate of a semiconductor device in accordance with a preferred embodiment of the present invention.

FIG. 6 is a graph showing a polysilicon reduction rate (PDR) according to whether a Ti-B mixed film is present in a gate electrode made of polysilicon and W; FIG.

Fig. 7 is a result of comparing PDR when polysilicon at the bottom of W is doped with P ⁺ and when doped with N ⁺ .

<Explanation of symbols for main parts of drawing>

110 substrate 112 gate insulating film

114: first conductive film 116: Ti film

118 boron ion implantation process 120 Ti-B mixed film (or diffusion preventing film)

122: etching step 124: second conductive film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual gate of a semiconductor device and a method of forming the same, and more particularly, to a dual gate of a semiconductor device having a gate electrode having a structure in which a metal such as tungsten is laminated on polysilicon and a method of forming the same. will be.

As the degree of integration of semiconductor devices increases, the channel length of transistors also decreases. As described above, as the channel length decreases, a so-called short channel effect (SCD) in which the threshold voltage (Vth) of the transistor is rapidly lowered in the conventional transistor structure is increasing.

In particular, since a buried channel is formed in a P Metal Oxide Semiconductor Field Effet Transistor (PMOSFET) having an N ⁺ polysilicon gate, a short channel effect occurs more severely. To overcome this, conventionally, dual polysilicones each form an N ⁺ polysilicon gate having a low work function (4.14 eV) in an NMOSFET and a P ⁺ polysilicon gate having a high work function (less than 5.3 eV) in a PMOSFET. The research on the gate is being actively conducted. This is to adjust the work function of the polysilicon to implement the surface channel in the PMOSFET as well as the NMOSFET. In this case, a dopant is injected into the polysilicon to control the work function of the polysilicon. In order to form the N ⁺ polysilicon gate, a phosphorous (Phosphorous) or an arsenic (Arsenic) is injected and the P ⁺ polysilicon gate is injected. To form a boron (Boron) or boron fluoride (BF ₂ ) must be injected.

1 is a cross-sectional view illustrating a dual gate formed according to this prior art. Referring to FIG. 1, a conventional dual gate includes a gate insulating film 12 formed in a portion of the substrate 10, and a first conductive film made of polysilicon of N ⁺ or P ⁺ type on the gate insulating film 12. 14 and a gate electrode on which the second conductive film 16 made of a metal such as tungsten (W) is laminated on the first conductive film 14.

However, when forming the dual gate according to the related art, various problems are caused by the out diffusion phenomenon in which the dopant doped in the polysilicon forming the gate electrode is diffused to the outside. Representatively, dopants doped with polysilicon, such as boron of PMOS, penetrate into the channel region through a subsequent process to change the threshold voltage (Vth) of the PMOS, and boron (B) on the polysilicon through a subsequent process. Device characteristics are deteriorated due to depletion of polysilicon caused by diffusion into the metal. In this case, the phenomenon of boron penetration into the channel region may be solved by nitriding the surface of the gate insulating layer 12, but there is currently no solution to the diffusion of boron into the metal on the polysilicon.

FIG. 2 is a result of comparing capacitance-voltage (C-V) characteristics between an NMOS and a PMOS in the dual gate shown in FIG. 1. Referring to FIG. 2, in the case of the PMOS, the capacitance value is smaller than that of the NMOS due to the consumption of the first conductive film caused by the diffusion of boron in the first conductive film made of polysilicon toward the second conductive film. It can be seen that. As a result, it can be seen that the PMOS deteriorates device characteristics due to the out diffusion phenomenon of boron.

Accordingly, the present invention has been proposed to solve the above problems, and the dual gate of the semiconductor device capable of suppressing the out diffusion phenomenon in which the dopant doped to the polysilicon of the PMOS in the dual gate to the material on the polysilicon, and its The purpose is to provide a formation method.

According to an aspect of the present invention, a gate insulating film formed on a substrate and first and second conductive films are stacked on the gate insulating film, and a diffusion barrier layer is formed between the first and second conductive films. Provided is a dual gate of a semiconductor device including a gate electrode formed therebetween.

According to another aspect of the present invention, there is provided a method of forming a gate insulating film on a substrate, depositing a first conductive film on the gate insulating film, and forming a gate insulating film on the first conductive film. Depositing a metal layer, and performing an impurity ion implantation process to form a diffusion barrier film in which the metal of the metal layer and the impurities are mixed at an interface between the first conductive layer and the metal layer, and remaining on the diffusion barrier layer; Removing the metal layer, depositing a second conductive layer on the diffusion barrier layer, selectively etching the second conductive layer, the diffusion barrier layer, the first conductive layer, and the gate insulating layer on the substrate. It provides a method for forming a dual gate of a semiconductor device comprising the step of forming a gate electrode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. Also, throughout the specification, the same reference numerals denote the same components.

Example

4 is a cross-sectional view illustrating a dual gate of a semiconductor device according to a preferred embodiment of the present invention. Here, for convenience of description, only the dual gate of the PMOS device, which is a problem due to the out-diffusion phenomenon as shown in the above-mentioned prior art, is shown. In other words, the dual gate of the NMOS device has the same structure as in the aforementioned prior art.

Referring to FIG. 4, a dual gate of a semiconductor device according to an exemplary embodiment of the present invention may include a substrate 110 having an isolation layer (not shown), a gate insulating layer 112 formed in a portion of the substrate 110, and a gate; The first conductive layer 114 and the second conductive layer 124 are stacked on the gate insulating layer 112, and the gate formed by interposing the diffusion barrier layer 120 between the first and second conductive layers 114 and 124. An electrode.

The first conductive film 114 is formed of amorphous or crystallization, preferably made of P-type dopant, typically polysilicon doped with boron.

The diffusion barrier 120 is formed of a Ti-B mixed film in which Ti and B are combined. In addition, the second conductive film 124 is formed of tungsten (W) or tungsten silicide (WSi _X , where _X is a natural number).

That is, the dual gate of the PMOS device according to the preferred embodiment of the present invention forms a diffusion barrier layer 120 that prevents diffusion of boron on the first conductive layer 114 made of polysilicon, so that the boron is the first conductive layer. Out-diffusion phenomenon diffused into the second conductive film 124 on the 114 can be prevented. Therefore, the reliability of the semiconductor device having the dual gate can be improved.

3 is a result of experimenting with a diffusion profile of boron doped to a gate electrode made of TiSi. This has been disclosed in the paper (Applied physics letter, vol 52, 1803 page, published in 1988). 3 shows the secondary ion mass spectrometry (SIMS) profile of boron distributed in the lower silicon after etching the TiSi film after the thermal process. Referring to FIG. It can be seen that it is suppressed. This is because when Ti is doped with TiSi film, Ti-B compound bonds occur in the TiSi film because the Ti-B mixed film formed here suppresses the diffusion of boron.

Based on these results, in a preferred embodiment of the present invention, by interposing a Ti-B mixed film between polysilicon and W, the out diffusion phenomenon in which boron in the polysilicon diffuses to W is suppressed.

5A through 5D are cross-sectional views illustrating a method of forming a dual gate of a semiconductor device in accordance with an embodiment of the present invention illustrated in FIG. 4. In the figure, as shown in the above-mentioned prior art, only the dual gate of the PMOS device, which is a problem by the out diffusion phenomenon, is shown. However, for convenience of description, the dual gate forming method of the CMOS device will be described at the same time.

First, as shown in FIG. 5A, a shallow trench isolation (STI) process is performed on the substrate 110 to form an isolation layer (not shown) including an HDP (High Density Plasma) oxide film. Thus, a PMOS region (hereinafter referred to as a first region; not shown) in which the PMOS transistor is to be formed and a NMOS region (hereinafter referred to as a second region) in which the NMOS transistor is to be formed are defined in the substrate 110.

Subsequently, a gate insulating layer 112 is formed on the substrate 110. In this case, the gate insulating layer 112 may be formed by performing a separate oxidation process or may be formed as a pad oxide layer (not shown) used in the STI process. The oxidation process is performed by a wet oxidation method in which a silicon substrate is heated at a temperature of approximately 900 to 1000 ° C. in an oxidizing gas such as water vapor, or a dry oxidation method which is heated at a temperature of about 1200 ° C. using pure oxygen as an oxidizing gas. Conduct.

Subsequently, a first conductive film 114 is deposited on the gate insulating film 112. In this case, the first conductive film 114 may be formed of amorphous or crystal, preferably polysilicon.

Subsequently, a photoresist (not shown) is coated on the first conductive film 114, and then a photoresist pattern (not shown) is opened by performing an exposure and development process using a photomask (not shown). To form.

Subsequently, an ion implantation process using a photoresist pattern as an ion implantation mask is performed to inject a P-type dopant such as boron (B) or boron fluoride (BF ₂ ) into the first conductive film 114 in the first region.

Subsequently, the photoresist pattern is removed by performing a strip process, and then a photoresist (not shown) is applied on the first conductive layer 114, and then an exposure and development process using a photomask (not shown) is performed. To form a photoresist pattern (not shown) that opens the second region.

Subsequently, an ion implantation process using a photoresist pattern as an ion implantation mask is performed to implant an N-type dopant such as phosphorus (P) or arsenic (As) into the first conductive layer 114 in the second region.

Subsequently, after removing the photoresist pattern through a strip process, a metal layer such as a Ti film 116 or a TiSi film is deposited on the first conductive film 114.

Subsequently, as shown in FIG. 5B, after the photoresist (not shown) is applied over the entire structure on which the Ti film 116 is formed, an exposure and development process using a photomask (not shown) is performed to perform the first region. A photoresist pattern (not shown) is formed to open.

Subsequently, the boron (B) ion implantation process 118 using the photoresist pattern as the ion implantation mask is performed to form a Ti-B mixed film (at the interface between the first conductive film 114 and the Ti film 116 in the first region). 120 to form a diffusion barrier film.

Subsequently, as shown in FIG. 5C, a wet etching process 122 is performed to remove the Ti film 116 (see FIG. 5B) remaining on the Ti-B mixed film 120. At this time, the wet etching process 122 uses a hydrofluoric acid solution (HF: HydroFluoric acid).

Subsequently, as shown in FIG. 5D, a strip process is performed to remove the photoresist pattern (not shown). Then, the second conductive film 124 is deposited on the entire structure including the Ti-B mixed film 120 in the first region. At this time, the second conductive film 124 is formed of W or WSi _X (where _X is a natural number).

Subsequently, a mask process and an etching process are performed to form the second conductive film 124 in the first and second regions, the Ti-B mixed film 120 in the first region, and the first conductive film in the first and second regions ( 114 and the gate insulating layer 112 in the first and second regions are etched. As a result, a gate electrode having a structure in which the gate insulating layer 112, the first conductive layer 114, the Ti-B mixed layer 120, and the second conductive layer 124 are stacked is formed on the substrate 110 in the first region. At the same time, a gate electrode having a structure in which the gate insulating layer 112, the first conductive layer 114, and the second conductive layer 124 are stacked is formed on the substrate 110 in the second region.

FIG. 6 is a graph showing a polysilicon reduction rate (PDR) according to whether a Ti-B mixed film is present in a gate electrode made of polysilicon and W, and FIG. 7 is a polysilicon doped with P ⁺ at the bottom of W ^; This is a result of comparing the PDR between the case and the case doped with N ⁺ . Referring to FIGS. 6 and 7, in the case of polysilicon doped with N ⁺ , the capacitance value is maximized because the reduction does not occur inside the polysilicon in the inversion state, whereas the polysilicon doped with P ⁺ is maximized. In the case of inversion, it can be seen that a decrease occurs inside the polysilicon so that the PDR value is always smaller than 1. That is, the less boron reduction occurs in P ⁺ polysilicon, the closer the PDR value is to 1. Therefore, in the preferred embodiment of the present invention, the Ti-B mixed film is formed in the gate electrode so that the PDR value is close to one.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a dopant doped with a polysilicon film, that is, boron is formed on a polysilicon layer by forming a diffusion barrier film made of a Ti-B mixed film on a gate electrode made of polysilicon of PMOS in a dual gate. The out diffusion phenomenon diffused into the metal layer can be suppressed. Therefore, the reliability of a semiconductor element can be improved.

Claims (13)

A gate insulating film formed on the substrate; And A gate electrode formed by stacking first and second conductive layers on the gate insulating layer and having a diffusion barrier interposed between the first and second conductive layers Dual gate of a semiconductor device comprising a. The method of claim 1, The diffusion barrier layer is a dual gate of the semiconductor device to prevent the impurity ions of the first conductive film to diffuse into the second conductive film. The method of claim 2, The diffusion barrier is a dual gate of a semiconductor device formed of a Ti-B mixed film. The method according to any one of claims 1 to 3, The dual gate of the semiconductor device formed of the first conductive film polysilicon. The method of claim 4, wherein The second conductive layer is formed of W or WSi _X (where _X is a natural number). Forming a gate insulating film on the substrate; Depositing a first conductive film on the gate insulating film; Depositing a metal layer on the first conductive film; Performing an impurity ion implantation process to form a diffusion barrier layer in which the metal of the metal layer and the impurities are mixed at an interface between the first conductive layer and the metal layer; Removing the metal layer remaining on the diffusion barrier layer; Depositing a second conductive film on the diffusion barrier film; And Selectively etching the second conductive layer, the diffusion barrier layer, the first conductive layer, and the gate insulating layer to form a gate electrode on the substrate Dual gate forming method of a semiconductor device comprising a. The method of claim 6, And the metal layer is formed of a Ti film or a Ti-silicide film. The method of claim 7, wherein The impurity ion implantation process is a method of forming a dual gate of a semiconductor device using boron (B). The method of claim 8, And the diffusion barrier layer prevents the impurity ions of the first conductive layer from diffusing into the second conductive layer. The method of claim 9, The diffusion barrier is a dual gate forming method of a semiconductor device formed of a Ti-B mixed film. The method according to any one of claims 6 to 10, And the second conductive layer is formed of W or WSi _X (where _X is a natural number). The method according to any one of claims 6 to 10, Removing the metal layer is a dual gate forming method of a semiconductor device using a wet etching process. The method of claim 12, The wet etching process is a dual gate forming method of a semiconductor device using HF.

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