KR20070022155A - Signal readout system and test equipment - Google Patents

Abstract

A signal reading apparatus for reading an output signal of a solid-state imaging element, comprising: a plurality of measuring means for measuring pixel data included in an output signal of the solid-state imaging element, and each of the plurality of measuring means is pixel data of the solid-state imaging element And a timing generator for generating a clock signal indicating a timing for measuring the signal and supplying the clock signal to the plurality of measuring means, respectively, to sequentially measure the pixel data of the solid-state image sensor by an interleave operation.

Test, solid-state image sensor, signal reading device, pixel data, timing, interleaving

Description

SIGNAL READOUT SYSTEM AND TEST EQUIPMENT

The present invention relates to a signal reading device and a test device. In particular, this invention relates to the signal reading apparatus which reads the output signal of a solid-state image sensor, and the test apparatus which tests a solid-state image sensor. Regarding a designated country where the incorporation by reference of a document is recognized, the contents described in the following application are incorporated into the present application by reference, and are part of the description of the present application.

Japanese Patent Application No. 2004-180151 Filed Date June 17, 2004

The CCD (Charge Couple Device) transfers the charge photoelectrically converted by the photodiode based on a clock signal input from a driver (hereinafter referred to as "DR") and outputs it as an electrical signal. The signal reading device measures the reset section and the data section of the electrical signal output from the CCD, respectively, and reads out the difference between the reset section and the data section as the pixel data of the CCD. The signal level of the pixel data is amplified by a variable gain amplifier (hereinafter referred to as "VGA"), and the pixel data is converted into a digital signal by an analog-to-digital converter (hereinafter referred to as "ADC").

Since the existence of a prior art document is not recognized at this time, the description regarding a prior art document is abbreviate | omitted.

[Problem to Solve Invention]

In recent years, CCDs that operate at very high speeds have been developed in response to demands such as photographing high quality moving pictures. For this reason, there is a problem that even a signal reading device requires high speed, and that a very high speed VGA and ADC are required.

An object of this invention is to provide the test apparatus which can solve the said subject here. This object is achieved by a combination of the features described in the independent claims in the claims. The dependent claims also define more advantageous embodiments of the invention.

[Means for solving the problem]

According to the first aspect of the present invention, in a signal reading apparatus for reading an output signal of a solid-state imaging element, a plurality of measuring means for measuring pixel data included in the output signal of the solid-state imaging element, and a plurality of measuring means, respectively Generates a clock signal representing the timing of measuring the pixel data of the solid-state imaging element and supplies it to the plurality of measurement means, respectively, thereby causing the plurality of measurement means to sequentially sequence the pixel data of the solid-state imaging element by an interleave operation. It includes a timing generator to measure.

And a signal processing circuit which sequentially selects and acquires the pixel data of the solid-state imaging element measured by the plurality of measuring means by the selector, wherein the timing generator is configured such that each of the plurality of measuring means measures the pixel data of the solid-state imaging element. A clock signal representing the timing corresponding to the timing to be generated may be generated and supplied to the selector.

The timing generator causes the solid-state imaging device to output the same output signal a plurality of times, and generates a clock signal to be supplied to each of the plurality of measuring means, whereby the solid-state imaging device outputs the first output signal. In the case of outputting the second output signal, another measurement means measures the measurement of the pixel data at the same timing in the output signal of the solid-state imaging element, and the signal processing circuit outputs the first output signal by the solid-state imaging element. In one case, the pixel data measured by the plurality of measuring means and the pixel data measured by the plurality of measuring means may be obtained by averaging when the solid-state imaging device outputs the second output signal.

According to the 2nd aspect of this invention, in the test apparatus which tests a solid-state image sensor, each of several measurement means which respectively measures the pixel data contained in the output signal of a solid-state image sensor, and each of a some measurement means is a solid-state image pick-up. A timing generator for generating a clock signal indicating a timing for measuring pixel data of the device and supplying the clock signal to the plurality of measuring means, respectively, thereby causing the plurality of measuring means to sequentially measure pixel data of the solid-state imaging device by interleaving operation; And a goodness determining unit for determining the good or bad of the solid-state imaging element based on the pixel data measured by the measuring means.

According to the third aspect of the present invention, in the signal reading apparatus for reading the output signal of the solid-state imaging element, the measurement means for measuring the pixel data included in the output signal of the solid-state imaging element and the solid-state imaging element make the same output. Outputting the signal a plurality of times, and generating and supplying a clock signal indicating the timing at which the measurement means measures the pixel data of the solid-state imaging element to the measurement means, where the solid-state imaging element outputs the first output signal, and solid-state imaging In the case where the element outputs the second output signal, it includes a timing generator which causes the measuring means to measure other pixel data of the output signal of the solid-state imaging element.

According to the fourth aspect of the present invention, in the test apparatus for testing a solid-state imaging device, the measuring means for measuring pixel data included in the output signal of the solid-state imaging device and the solid-state imaging device output the same output signal a plurality of times. By generating a clock signal indicating the timing of measuring the pixel data of the solid-state imaging element and supplying it to the measurement means, whereby the solid-state imaging element outputs the first output signal, and the solid-state imaging element outputs the second time. In the case of outputting a signal, a timing generator for causing the measuring means to measure other pixel data of the output signal of the solid-state imaging device, and a good-quality determination unit for determining the quality of the solid-state imaging device based on the pixel data acquired by the measuring means do.

According to the fifth aspect of the present invention, in the signal reading apparatus for reading an output signal of a solid-state imaging element, a plurality of measuring means for measuring pixel data included in the output signal of the solid-state imaging element, and a plurality of measuring means, respectively And a signal processing circuit for averaging and acquiring the pixel data measured by the method.

According to the sixth aspect of the present invention, in a test apparatus for testing a solid-state imaging device, a plurality of measuring means for measuring pixel data included in an output signal of the solid-state imaging device, respectively, and a pixel measured by the plurality of measuring means And a signal processing circuit for averaging and acquiring the data, and a quality determining unit for determining the quality of the solid-state imaging element based on the pixel data obtained by averaging the data.

In addition, the summary of the present invention does not enumerate all the essential features of the present invention, and the subcombination of these feature groups may also be the present invention.

[Effects of the Invention]

According to the signal reading apparatus of the present invention, a signal can be read out from a solid-state imaging device at a very high speed.

1 is a diagram illustrating an example of a configuration of a test apparatus 100.

2 shows the operation of the first measuring means 102 and the second measuring means 202.

3 shows the operation of the first measuring means 102 and the second measuring means 202.

4 is a diagram showing pixel data acquired by the signal processing circuit 124.

5 is a diagram showing pixel data acquired by the signal processing circuit 124.

6 shows the operation of the first measuring means 102 and the second measuring means 202.

7 is a diagram showing pixel data acquired by the signal processing circuit 124.

8 is a diagram illustrating an example of a configuration of a test apparatus 800.

9 shows the operation of the measuring means 802.

10 shows the operation of the measuring means 802.

11 is a diagram showing pixel data acquired by the signal processing circuit 824.

12 is a diagram illustrating an example of a configuration of a test apparatus 1000.

13 shows the operation of the measuring means 1102.

14 shows the operation of the measuring means 1102.

15 is a diagram showing pixel data acquired by the signal processing circuit 1124.

[Description of the code]

10 DUT

100 test device

102 First measuring means

104 CDS

106 VGA

108 ADC

110 S & H

112 S & H

114 S & H

116 subtractor

120 DR

122 TG

124 signal processing circuit

126 selector

128 acceptance judgment

202 second measuring means

204 CDS

206 VGA

208 ADC

210 S & H

212 S & H

214 S & H

216 subtractor

800 test device

802 measuring means

804 CDS

806 VGA

808 ADC

810 S & H

812 S & H

814 S & H

816 subtractor

820 DR

822 TG

824 signal processing circuit

828 Acceptance Determination Unit

1000 test device

1102 measuring instrument

1104 1st CDS

1105 selector

1106 VGA

1108 ADC

1110 S & H

1112 S & H

1114 S & H

1116 subtractor

1120 DR

1122 TG

1124 signal processing circuit

1128 Acceptance Determination Unit

1204 2nd CDS

1210 S & H

1212 S & H

1214 S & H

1216 Subtractor

EMBODIMENT OF THE INVENTION Hereinafter, although this invention is demonstrated through embodiment of invention, the following embodiment does not limit invention which belongs to a Claim, and all the combination of the feature demonstrated in embodiment is a solution of invention. It is not limited to essential.

1 shows an example of the configuration of a test apparatus 100 according to the first embodiment of the present invention. The test apparatus 100 includes a first measuring means 102, a second measuring means 202, a DR 120, a timing generator (hereinafter referred to as "TG") 122, a signal processing circuit 124, and a positive and negative determining unit 128. In addition, the test apparatus 100 is an example of the signal reading apparatus which reads the output signal of the solid-state image sensor (henceforth "DUT") of this invention. The DUT is, for example, a CCD and outputs a charge photoelectrically converted by a photodiode as an electric signal.

The first measuring means 102 includes a correlated double sampling circuit (hereinafter, referred to as "CDS") 104, VGA 106, and ADC 108. The CDS 104 includes a sample holder (hereinafter referred to as "S & H") 110, S & H 112, S & H 114, and a subtractor 116. The second measuring means 202 also includes a CDS 204, a VGA 206, and an ADC 208. CDS 204 includes S & H 210, S & H 212, S & H 214, and subtractor 216. The signal processing circuit 124 also includes a selector 126.

In addition, the 1st measuring means 102 and the 2nd measuring means 202 are an example of the measuring means of this invention, and the measuring means of this invention may also include the circuit structure different from 1st measuring means 102 and 2nd measuring means 202. FIG. . In addition, the first measuring means 102 and the second measuring means 202 may include an amplifier with a fixed gain instead of VGA 106 or 206.

The TG 122 generates a clock signal indicating a timing at which the DUT 10 outputs an output signal via the DR 120, and supplies the same to the DUT 10. The DUT 10 outputs an output signal including continuous pixel data on the basis of the clock signal input from the DR 120 and supplies it to the first measuring means 102 and the second measuring means 202.

In addition, the TG 122 generates a clock signal indicating a timing at which each of the first measuring means 102 and the second measuring means 202 measures pixel data included in the output signal of the DUT 10, thereby measuring the first measuring means 102 and the second measuring means. Respectively supplied to the means 202. The first measuring means 102 and the second measuring means 202 respectively measure pixel data included in the output signal of the DUT 10 based on the clock signal supplied from the TG 122.

Specifically, the S & H 110 samples the voltage value of the reset section of the output signal of the DUT 10 based on the clock signal SHP1 input from the TG 122. The S & H 112 obtains the voltage value sampled by the S & H 110 based on the clock signal SHD1 input from the TG 122 and supplies it to the subtractor 116. The S & H 114 samples the voltage value of the data portion of the output signal of the DUT 10 based on the clock signal SHD1 input from the TG 122 and supplies it to the subtractor 116. That is, the clock signal SHP1 and the clock signal SHD1 have a phase difference for a time interval between the reset unit and the data unit of the output signal of the DUT 10. The S & H 112 and S & H 114 operate based on the same clock signal SHD1, thereby supplying a voltage value to the subtractor 116 in synchronization.

The subtractor 116 calculates the difference between the voltage value of the reset section supplied from S & H 112 and the voltage value input from S & H 114 and outputs it as pixel data. The VGA 106 amplifies the pixel data output by the subtractor 116. The ADC 108 converts the pixel data amplified by the VGA 106 into a digital signal based on the clock signal AD1 input from the TG 122 and supplies it to the signal processing circuit 124.

The S & H 210 samples the voltage value of the reset section of the output signal of the DUT 10 based on the clock signal SHP2 input from the TG 122. The S & H 212 acquires the voltage value sampled by the S & H 210 based on the clock signal SHD2 input from the TG 122 and supplies it to the subtractor 216. The S & H 214 samples the voltage value of the data portion of the output signal of the DUT 10 based on the clock signal SHD2 input from the TG 122 and supplies it to the subtractor 216. That is, the clock signal SHP2 and the clock signal SHD2 have a phase difference for a time interval between the reset unit and the data unit of the output signal of the DUT 10. The S & H 212 and the S & H 214 operate based on the same clock signal SHD2, thereby supplying a voltage value to the subtractor 216 in synchronization.

The subtractor 216 calculates a difference between the voltage value of the reset section supplied from S & H 212 and the voltage value input from S & H 214 and outputs it as pixel data. The VGA 206 amplifies the pixel data output by the subtractor 116. The ADC 208 converts the pixel data amplified by the VGA 206 into a digital signal based on the clock signal AD2 input from the TG 122 and supplies it to the signal processing circuit 124.

In addition, the TG 122 generates a clock signal SEL indicating a timing corresponding to the timing at which each of the first measuring means 102 and the second measuring means 202 measures pixel data included in the output signal of the DUT 10, thereby selecting the selector 126. To feed. The signal processing circuit 124 then supplies the pixel data included in the output signal of the DUT 10 measured by the first measuring unit 102 and the second measuring unit 202 to the selector 126 based on the clock signal SEL input from the TG 122. Select and acquire sequentially.

The acceptance determination unit 128 determines the acceptance of the DUT 10 based on the pixel data measured by the first measurement means 102 and the second measurement means 202 and subjected to desired signal processing by the signal processing circuit 124. By the above operation, the test apparatus 100 tests the DUT 10 based on the pixel data included in the output signal of the DUT 10.

In addition, in this example, the test apparatus 100 includes two measuring means of the first measuring means 102 and the second measuring means 202, but in another example, the test apparatus 100 includes three or more measuring means, Three or more measuring means may measure pixel data included in the output signal of the DUT 10 by an interleave operation.

2 to 5 show a first example of the operation of the test apparatus 100 according to the first embodiment. FIG. 2 shows the operation of the first measuring means 102 and the second measuring means 202 when the DUT 10 outputs the first output signal, and FIG. 3 shows the operation when the DUT 10 outputs the second output signal. The operation of the first measuring means 102 and the second measuring means 202 is shown. 4 and 5 show pixel data acquired by the signal processing circuit 124.

The TG 122 generates a clock signal indicating a timing at which each of the first measuring means 102 and the second measuring means 202 measures pixel data included in the output signal of the DUT 10, thereby generating the first measuring means 102 and the second measuring means 202. By supplying to the first measurement means 102 and the second measurement means 202 to sequentially measure the pixel data included in the output signal of the DUT 10 by interleaving operation. In addition, the TG 122 supplies the clock signal indicating the timing at which the DUT 10 outputs the output signal through the DR 120 a plurality of times, thereby causing the DUT 10 to output the same output signal a plurality of times. The TG 122 generates a clock signal indicating a timing at which each of the first measuring means 102 and the second measuring means 202 measures pixel data included in the output signal of the DUT 10, thereby causing the DUT 10 to output the first output signal. In the case of outputting and in the case where the DUT 10 outputs the second output signal, the other measuring means causes measurement of the pixel data of the same timing in the output signal of the DUT 10.

First, referring to FIG. 2, the operation of the test apparatus 100 when the DUT 10 outputs the first output signal IN will be described. The TG 122 sets the phase difference between the clock signals SHP1, SHD1, AD1 and the clock signals SHP2, SHD2, AD2 to the length of the pixel data included in the output signal IN of the DUT 10, and measures the first measurement means. The clock signals SHP1, SHD1, AD1 and the clock signals SHP2, SHD2, AD2 are supplied to each of the 102 and second measuring means 202. Thereby, the 1st measuring means 102 and the 2nd measuring means 202 measure every pixel data contained in the output signal IN sequentially. That is, the first measuring means 102 measures the pixel data N, the second measuring means 202 measures the pixel data N + 1, the first measuring means 102 measures the pixel data N + 2, and The second measuring means 202 measures the pixel data N + 3.

Next, with reference to FIG. 3, the operation of the test apparatus 100 when the DUT 10 outputs the second output signal IN will be described. The TG 122 outputs the second output signal at the same timing as when the DUT 10 outputs the first output signal IN at the same timing as the clock signals SHP2, SHD2, and AD2 are supplied to the second measurement means 202. When outputting (IN), clock signals SHP1, SHD1, AD1 are supplied to the first measuring means 102. The TG 122 has a second timing at the same timing as the timing at which the clock signals SHP1, SHD1, AD1 were supplied to the first measuring unit 102 when the DUT 10 outputs the first output signal IN. When outputting the output signal IN, the clock signals SHP2, SHD2 and AD2 are supplied to the second measuring means 202.

Thereby, the 1st measuring means 102 and the 2nd measuring means 202 measure the pixel data different from the case where the DUT 10 outputs the 1st output signal IN sequentially. That is, the second measuring means 202 measures the pixel data N, the first measuring means 102 measures the pixel data N + 1, and the second measuring means 202 measures the pixel data N + 2. The first measuring means 102 measures the pixel data N + 3.

Next, the operation of the signal processing circuit 124 will be described with reference to FIG. 4. The TG 122 supplies the selector 126 with a clock signal SEL corresponding to the timing at which the first measuring means 102 and the second measuring means 202 respectively measure pixel data. The signal processing circuit 124 selects and acquires the pixel data measured by the first measuring means 102 and the second measuring means 202 by the selector 126 based on the clock signal SEL.

That is, when the DUT 10 outputs the first output signal, the signal processing circuit 124 acquires the pixel data N from the first measuring means 102 and receives the pixel data N + 1 from the second measuring means 202. It acquires, and acquires pixel data N + 2 from the 1st measuring means 102, and acquires pixel data N + 3 from the 2nd measuring means 202. FIG. Further, when the DUT 10 outputs the second output signal, the signal processing circuit 124 acquires the pixel data N from the second measuring means 202, and acquires the pixel data N + 1 from the first measuring means 102. It acquires, and acquires pixel data N + 2 from the 2nd measuring means 202, and acquires pixel data N + 3 from the 1st measuring means 102. As shown in FIG.

Then, the signal processing circuit 124, when the DUT 10 outputs the first output signal, the pixel data measured by the first measurement means 102 and the second measurement means 202 and the DUT 10 outputs the second output signal. The pixel data measured by the first measuring means 102 and the second measuring means 202 are averaged and obtained, and stored in a memory.

Next, a modification of the operation of the signal processing circuit 124 will be described with reference to FIG. 5. In the description of FIG. 4, the signal processing circuit 124 sequentially selects and outputs pixel data measured by the first measurement means 102 or the second measurement means 202 by the selector 126, but the signal processing circuit 124 in the modification. Does not have to have a selector 126. That is, when the DUT 10 outputs the first output signal, the pixel data measured by the first measuring means 102, the pixel data output by the second measuring means 202, and the DUT 10 outputs the second output signal. In this case, the pixel data measured by the first measuring means 102 and the pixel data measured by the second measuring means 202 are stored in the memory. The pixel data measured by the first measuring means 102 and the pixel data measured by the second measuring means 202 a second time are averaged, and the pixel data and the first measuring means 102 measured by the second measuring means 202 first. The pixel data measured the second time is averaged.

According to the test apparatus 100 according to the present example, a test of the DUT 10 operating at high speed can be performed by providing a plurality of measuring means and measuring pixel data included in the output signal of the DUT 10 by interleaving operation. Further, even when there is a measurement error due to a mismatch between the first measuring means 102 and the second measuring means 202, when the image is reproduced based on the pixel data, the mismatch between the first measuring means 102 and the second measuring means 202 occurs. Streaks can be prevented from occurring.

Specifically, the level of pixel data included in the output signal of the DUT 10 is x, the measured value by the first measuring means 102 is y ₁ = ax + b, and the measured value by the second measuring means 202 is y ₂ = cx. If it is set to + d, the pixel data averaged and acquired by the signal processing circuit 124 becomes Y = (a + b) x / 2 + (b + d) x / 2. That is, since (a + b) / 2 and (b + d) / 2 are constants determined by the characteristics of the first measuring unit 102 and the second measuring unit 202, the signal processing circuit 124 The acquired pixel data is shown like the pixel data measured by one measuring means. Therefore, generation | occurrence | production of the measurement error by the mismatch of the 1st measuring means 102 and the 2nd measuring means 202 can be prevented.

In addition, according to the test apparatus 100 according to the present example, the random data generated by the DUT 10 or the test apparatus 100 by averaging the pixel data measured by the first measuring means 102 and the pixel data measured by the second measuring means 202. Random noise can be reduced.

6 to 7 show a second example of the operation of the test apparatus 100 according to the first embodiment. 6 shows the operation of the first measuring means 102 and the second measuring means 202. 7 shows pixel data acquired by the signal processing circuit 124.

The TG 122 generates a clock signal indicating a timing at which each of the first measuring means 102 and the second measuring means 202 measures pixel data included in the output signal of the DUT 10, thereby generating the first measuring means 102 and the second measuring means 202. By respectively supplying to the first measurement means 102 and the second measurement means 202 to simultaneously measure the pixel data included in the output signal of the DUT 10.

First, the operation of the test apparatus 100 will be described with reference to FIG. 6. The TG 122 supplies the clock signals SHP1, SHD1, AD1 to the first measuring means 102, and the clock signals SHP2, SHD2, AD2 at the same timing as the clock signals SHP1, SHD1, AD1 to the second measuring means 202. ). Thereby, the 1st measuring means 102 and the 2nd measuring means 202 measure the pixel data (N, N + 1, N + 2, N + 3, ...) contained in the output signal IN simultaneously.

Next, the operation of the signal processing circuit 124 will be described with reference to FIG. 7. The signal processing circuit 124 acquires pixel data measured simultaneously by the first measuring means 102 and the second measuring means 202, respectively. The signal processing circuit 124 averages and acquires the pixel data measured by the first measuring means 102 and the pixel data measured by the second measuring means 202 and stores them in the memory.

According to the test apparatus 100 according to the present example, the DUT 10 or the test apparatus without increasing the number of measurements by averaging the pixel data measured by the first measuring means 102 and the pixel data measured by the second measuring means 202. Random noise generated by 100 can be reduced.

8 shows an example of a configuration of a test apparatus 800 according to the second embodiment of the present invention. The test apparatus 800 includes the measuring means 802, DR 820, TG 822, signal processing circuit 824, and the quality determining unit 828. In addition, the test apparatus 800 is an example of the signal reading apparatus which reads the output signal of the solid-state image sensor of this invention. The measuring means 802 includes a CDS 804, a VGA 806, and an ADC 808. CDS 804 includes S & H 810, S & H 812, S & H 814, and subtractor 816.

In addition, the measuring means 802 is an example of the measuring means of this invention, and the measuring means of this invention may have a circuit structure different from the measuring means 802. In addition, the measuring means 802 may include a fixed gain amplifier in place of the VGA 806.

The TG 822 generates a clock signal indicating the timing at which the DUT 10 outputs an output signal via the DR 820 and supplies the same to the DUT 10. The DUT 10 outputs an output signal including continuous pixel data based on the clock signal input from the DR 820 and supplies it to the measuring means 802.

The TG 822 also generates and supplies a clock signal indicating the timing at which the measuring means 802 measures pixel data included in the output signal of the DUT 10 to the measuring means 802. And the measuring means 802 measures the pixel data contained in the output signal of the DUT 10 based on the clock signal supplied from TG822.

Specifically, the S & H 810 samples the voltage value of the reset section of the output signal of the DUT 10 based on the clock signal SHP input from the TG 822. The S & H 812 obtains the voltage value sampled by the S & H 810 based on the clock signal SHD input from the TG 822 and supplies it to the subtractor 816. The S & H 814 samples the voltage value of the data portion of the output signal of the DUT 10 based on the clock signal SHD input from the TG 822 and supplies it to the subtractor 816. In other words, the clock signal SHP and the clock signal SHD have a phase difference between the reset section of the output signal of the DUT 10 and the data section. The S & H 812 and the S & H 814 operate on the same clock signal SHD to supply voltage values to the subtractor 816 in synchronization.

The subtractor 816 calculates the difference between the voltage value of the reset section supplied from S & H 812 and the voltage value input from S & H 814 and outputs it as pixel data. The VGA 806 amplifies the pixel data output by the subtractor 816. The ADC 808 converts the pixel data amplified by the VGA 806 into a digital signal based on the clock signal AD input from the TG 822 and supplies it to the signal processing circuit 824.

In addition, the TG 822 generates a clock signal indicating a timing corresponding to the timing at which the measuring means 802 measures pixel data included in the output signal of the DUT 10, and supplies it to the signal processing circuit 824. The signal processing circuit 824 then acquires pixel data included in the output signal of the DUT 10 measured by the measuring unit 802 based on the clock signal supplied from the TG 822.

The quality determining unit 828 measures the quality of the DUT 10 based on the pixel data measured by the measuring unit 802 and subjected to the desired signal processing by the signal processing circuit 824. By the above operation, the test apparatus 800 tests the DUT 10 based on the pixel data included in the output signal of the DUT 10.

9 to 11 show an example of the operation of the test apparatus 800 according to the second embodiment. 9 shows the operation of the measuring means 802 when the DUT 10 outputs the first output signal, and FIG. 10 shows the operation of the measuring means 802 when the DUT 10 outputs the second output signal. 11 shows pixel data acquired by the signal processing circuit 824.

The TG 822 causes the DUT 10 to output the same output signal a plurality of times, and generates and supplies a clock signal indicating the timing at which the measuring means 802 measures pixel data included in the output signal of the DUT 10 to the measuring means 802. Thus, when the DUT 10 outputs the first output signal and when the DUT 10 outputs the second output signal, the measuring means 802 causes the pixel data to measure different pixel data to be measured.

First, the operation of the test apparatus 800 when the DUT 10 outputs the first output signal IN will be described with reference to FIG. 9. The TG 822 sets the timing of the sampling indicated by the clock signals SHP, SHD, and AD to be twice the pixel data included in the output signal IN of the DUT 10, and the clock signal (SHP, SHD, AD). Thereby, the measuring means 802 measures the pixel data contained in the output signal IN across. In other words, the measuring means 802 measures pixel data (N, N + 2, N + 4 ...).

Next, with reference to FIG. 10, operation | movement of the test apparatus 800 in the case where DUT 10 outputs the 2nd output signal IN is demonstrated. When the DUT 10 outputs the first output signal IN, the TG 822 shifts the clock signals SHP, SHD, and AD supplied to the measuring means 802 by the interval of pixel data included in the output signal of the DUT 10. When the DUT 10 outputs the second output signal IN, it is supplied to the measuring means 802. As a result, the measuring means 802 sequentially measures the pixel data different from the case where the DUT 10 outputs the first output signal IN. That is, the measuring means 802 measures pixel data (N + 1, N + 3, N + 5 ...).

Next, with reference to FIG. 11, the operation solution of the signal processing circuit 824 is demonstrated. When the DUT 10 outputs the first output signal, the signal processing circuit 824 obtains pixel data (N, N + 2, N + 4 ...) from the measuring means 802 and stores it in the memory. Further, when the DUT 10 outputs the second output signal, the signal processing circuit 824 acquires pixel data (N + 1, N + 3, N + 5 ...) from the measuring means 802 and stores it in the memory. do.

According to the test apparatus 800 related to this example, by measuring every other pixel data included in the output signal of the DUT 10 by shifting the clock signal indicating the timing of measuring the pixel data included in the output signal of the DUT 10 With the simple structure, the entire pixel data included in the output signal of the DUT 10 operating at high speed can be measured, and the DUT 10 can be tested.

In this example, the TG 822 measures the sampling timing indicated by the clock signals SHP, SHD, and AD at an interval of twice the pixel data contained in the output signal IN of the DUT 10. Although the form for causing the means 802 to measure the output signal of the DUT 10 twice has been described, the measurement means 802 causes the output of the DUT 10 to be at an interval of N times the pixel data included in the output signal IN of the DUT 10. The signal may be measured N times.

12 shows an example of a configuration of a test apparatus 1000 according to the third embodiment of the present invention. The test apparatus 1000 includes a measuring means 1102, a DR 1120, a TG 1122, a signal processing circuit 1124, and a quality determining unit 1128. In addition, the test apparatus 1000 is an example of the signal reading apparatus which reads the output signal of the solid-state image sensor of this invention.

The measuring means 1102 comprises a first CDS 1104, a second CDS 1204, a selector 1105, a VGA 1106, and an ADC 1108. The first CDS 1104 includes an S & H 1110, an S & H 1112, an S & H 1114, and a subtractor 1116. The second CDS 1204 also includes an S & H 1210, an S & H 1212, an S & H 1214, and a subtractor 1216.

The first CDS 1104 and the second CDS 1204 are examples of the measuring means of the present invention, and the measuring means of the present invention may have a circuit configuration different from that of the first CDS 1104 and the second CDS 1204. In addition, the measuring means 1102 may include a fixed gain amplifier in place of VGA 1106.

The TG 1122 generates a clock signal indicating a timing at which the DUT 10 outputs an output signal via the DR 1120, and supplies the generated clock signal to the DUT 10. The DUT 10 outputs an output signal including continuous pixel data based on the clock signal input from the DR 1120 and supplies it to the measuring means 1102.

In addition, the TG 1122 generates a clock signal indicating a timing at which each of the first CDS 1104 and the second CDS 1204 measures pixel data included in the output signal of the DUT 10, and generates a clock signal to the first CDS 1104 and the second CDS 1204, respectively. Supply. The first CDS 1104 and the second CDS 1204 respectively measure pixel data included in an output signal of the DUT 10 based on a clock signal supplied from the TG 1122.

Specifically, the S & H 1110 samples the voltage value of the reset section of the output signal of the DUT 10 based on the clock signal SHP1 input from the TG 1122. The S & H 1112 acquires the voltage value sampled by the S & H 1110 based on the clock signal SHD1 input from the TG 1122 and supplies it to the subtractor 1116. The S & H 1114 samples the voltage value of the data portion of the output signal of the DUT 10 based on the clock signal SHD1 input from the TG 1122 and supplies it to the subtractor 1116. That is, the clock signal SHP1 and the clock signal SHD1 have a phase difference for a time interval between the reset unit and the data unit of the output signal of the DUT 10. In addition, S & H 1112 and S & H 1114 operate based on the same clock signal SHD1, thereby supplying a voltage value to subtractor 1116 in synchronization. The subtractor 1116 calculates a difference between the voltage value of the reset section supplied from S & H 1112 and the voltage value input from S & H 1114, outputs the pixel data, and supplies the pixel data to selector 1105.

The S & H 1210 samples the voltage value of the reset section of the output signal of the DUT 10 based on the clock signal SHP2 input from the TG 1122. The S & H 1212 obtains the voltage value sampled by the S & H 1210 based on the clock signal SHD2 input from the TG 1122 and supplies it to the subtractor 1216. The S & H 1214 samples the voltage value of the data portion of the output signal of the DUT 10 based on the clock signal SHD2 input from the TG 1122 and supplies it to the subtractor 1216. That is, the clock signal SHP2 and the clock signal SHD2 have a phase difference for a time interval between the reset unit and the data unit of the output signal of the DUT 10. The S & H 1212 and S & H 1214 operate based on the same clock signal SHD2, thereby synchronously supplying a voltage value to the subtractor 1216. The subtractor 1216 calculates a difference between the voltage value of the reset section supplied from the S & H 1212 and the voltage value input from the S & H 1214, outputs it as pixel data, and supplies it to the selector 1105.

The selector 1105 sequentially selects pixel data included in the output signal of the DUT 10 measured by the first CDS 1104 and the second CDS 1204 based on the clock signal SEL input from the TG 1122, and supplies the same to the VGA 1106. . The VGA 1106 amplifies the pixel data output by the selector 1105. The ADC 1108 converts the pixel data amplified by the VGA 1106 into a digital signal based on the clock signal AD input from the TG 1122 and supplies it to the signal processing circuit 1124.

The quality determining unit 1128 measures the quality of the DUT 10 based on the pixel data measured by the measuring unit 1102 and subjected to desired signal processing by the signal processing circuit 1124. By the above operation, the test apparatus 1000 tests the DUT 10 based on the pixel data included in the output signal of the DUT 10.

In addition, in this example, the measuring means 1102 includes two CDSs of the first CDS 1104 and the second CDS 1204, but in another example, the test apparatus 1000 includes three or more CDSs, and three or more CDSs. By the way, the pixel data included in the output signal of the DUT 10 may be measured by the interleaving operation.

13 to 15 show an example of the operation of the test apparatus 1000 according to the third embodiment. FIG. 13 shows the operation of the measuring means 1102 when the DUT 10 outputs the first output signal, and FIG. 14 shows the operation of the measuring means 1102 when the DUT 10 outputs the second output signal. 15 shows pixel data acquired by the signal processing circuit 1124.

The TG 1122 generates a clock signal indicating a timing at which each of the first CDS 1104 and the second CDS 1204 measures pixel data included in the output signal of the DUT 10 and supplies the same to the first CDS 1104 and the second CDS 1204, respectively. The first CDS 1104 and the second CDS 1204 may be configured to sequentially measure pixel data included in an output signal of the DUT 10 by interleaving. In addition, the TG 1122 supplies the clock signal indicating the timing at which the DUT 10 outputs the output signal through the DR 1120 a plurality of times, thereby causing the DUT 10 to output the same output signal a plurality of times. The TG 1122 generates a clock signal indicating a timing at which each of the first CDS 1104 and the second CDS 1204 measures pixel data included in the output signal of the DUT 10, so that the DUT 10 outputs the first output signal. In the case where the DUT 10 outputs the second output signal, the other CDS causes the measurement of the pixel data at the same timing in the output signal of the DUT 10 to be measured.

First, the operation of the test apparatus 1000 when the DUT 10 outputs the first output signal IN will be described with reference to FIG. 13. The TG 1122 sets the phase difference between the clock signals SHP1 and SHD1 and the clock signals SHP2 and SHD2 to the length of pixel data included in the output signal IN of the DUT 10, and the first CDS 1104 and the second CDS. Clock signals SHP1 and SHD1 and clock signals SHP2 and SHD2 are supplied to each of the 1204s. As a result, the first CDS 1104 and the second CDS 1204 are sequentially measured for each pixel data included in the output signal IN. That is, the first CDS 1104 measures the pixel data N, the second CDS 1204 measures the pixel data N + 1, the first CDS 1104 measures the pixel data N + 2, and the second The CDS 1204 measures pixel data (N + 3).

The TG 1122 also supplies a selector 1105 with a clock signal SEL corresponding to the timing at which the first CDS 1104 and the second CDS 1204 respectively measure pixel data. The selector 1105 sequentially selects and acquires pixel data measured by the first CDS 1104 and the second CDS 1204 based on the clock signal SEL.

The TG 1122 also supplies the ADC 1108 with a clock signal AD indicating the timing at which the ADC 1108 converts the pixel data acquired by the selector 1105 into digital data. Based on the clock signal AD, the ADC 1108 converts the pixel data selected by the selector 1105 and amplified by the VGA 1106 into digital data and supplies the digital data to the signal processing circuit 1124.

Next, with reference to FIG. 14, the operation of the test apparatus 1000 when the DUT 10 outputs the second output signal IN is described. The TG 1122 outputs the second output signal IN when the DUT 10 outputs the first output signal IN at the same timing as the clock signals SHP2 and SHD2 are supplied to the second CDS 1204. To output the clock signals, the clock signals SHP1 and SHD1 are supplied to the first CDS 1104. In addition, when the DUT 10 outputs the first output signal IN, the TG 1122 outputs the second output signal of the DUT 10 at the same timing as the clock signals SHP1 and SHD1 are supplied to the first CDS 1104. In the case of outputting (IN), clock signals SHP2 and SHD2 are supplied to the second CDS 1204.

As a result, the first CDS 1104 and the second CDS 1204 sequentially measure different pixel data than the case where the DUT 10 outputs the first output signal IN. That is, the second CDS 1204 measures pixel data N, the first CDS 1104 measures pixel data N + 1, the second CDS 1204 measures pixel data N + 2, and the first CDS 1204 measures pixel data N + 2. The CDS 1104 measures pixel data (N + 3).

In addition, when the DUT 10 outputs the first output signal IN, the TG 1122 outputs the second output signal IN at the same timing as the clock signal SEL is supplied to the selector 1105. The clock signal SEL to the selector 1105. The TG 1122 outputs the second output signal IN at the same timing as when the DUT 10 outputs the first output signal IN at the same timing as the clock signal AD is supplied to the ADC 1108. The clock signal AD to the ADC 1108.

And the selector 1105 is based on the clock signal SEL when the DUT 10 outputs the second output signal IN, similarly to the case where the DUT 10 outputs the first output signal IN. The pixel data measured by the CDS 1104 and the second CDS 1204 are sequentially selected and acquired. The ADC 1108 selects 1105 based on the clock signal AD when the DUT 10 outputs the second output signal IN, similarly to the case where the DUT 10 outputs the first output signal IN. Selects and converts the pixel data amplified by VGA 1106 into digital data and supplies it to the signal processing circuit 1124.

Next, the operation of the signal processing circuit 1124 will be described with reference to FIG. 15. The signal processing circuit 1124 obtains, from the ADC 1108, pixel data measured by the first CDS 1104 and the second CDS 1204 and selected by the selector 1105, respectively. That is, the signal processing circuit 1124 acquires the pixel data N measured by the first CDS 1104 when the DUT 10 outputs the first output signal, and the pixel data N + 1 measured by the second CDS 1204. ), The pixel data (N + 2) measured by the first CDS 1104 is acquired, and the pixel data (N + 3) measured by the second CDS 1204 is obtained. Further, when the DUT 10 outputs the second output signal, the signal processing circuit 1124 acquires the pixel data N measured by the second CDS 1204, and the pixel data N + 1 measured by the first CDS 1104. ), The pixel data (N + 2) measured by the second CDS 1204 is acquired, and the pixel data (N + 3) measured by the first CDS 1104 is obtained.

The signal processing circuit 1124 is configured to generate pixel data measured by the first CDS 1104 and the second CDS 1204 when the DUT 10 outputs the first output signal, and the second data signal when the DUT 10 outputs the second output signal. The pixel data measured by one CDS 1104 and the second CDS 1204 are averaged, acquired, and stored in a memory.

According to the test apparatus 1000 according to the present example, a test of the DUT 10 operating at high speed can be performed by providing a plurality of CDSs and measuring pixel data included in the output signal of the DUT 10 by interleaving operation. In addition, even when there is a measurement error due to a mismatch between the first CDS 1104 and the second CDS 1204, when the image is reproduced based on the pixel data, streaks due to the mismatch between the first CDS 1104 and the second CDS 1204 occur. Can be prevented.

Specifically, the level of pixel data included in the output signal of the DUT 10 is x, the measured value by the first CDS 1104 is y ₁ = ax + b, and the measured value by the second CDS 1204 is y ₂ = cx + d. In this case, the pixel data averaged and acquired by the signal processing circuit 1124 becomes Y = (a + b) x / 2 + (b + d) x / 2. That is, since (a + b) / 2 and (b + d) / 2 are constants determined by the characteristics of the first CDS 1104 and the second CDS 1204, they are acquired by the signal processing circuit 1124. The pixel data is shown like the pixel data measured by one measuring means. Therefore, generation of a measurement error due to a mismatch between the first CDS 1104 and the second CDS 1204 can be prevented.

In addition, according to the test apparatus 1000 according to the present example, random noise generated by the DUT 10 or the test apparatus 1000 is obtained by averaging pixel data measured by the first CDS 1104 and pixel data measured by the second CDS 1204. Can be reduced.

Although this invention was demonstrated using the above embodiment, the technical scope of this invention is described in the said embodiment, It is not limited to the range. Various changes or improvement can be added to the said embodiment. It is evident from the description of the claims that the forms adding such changes or improvements may be included in the technical scope of the present invention.

As is apparent from the above description, the signal reading apparatus of the present invention can read out a signal from a solid-state imaging device at a very high speed.

Claims (8)

In the signal reading device for reading the output signal of the solid-state image sensor, A plurality of measuring means for measuring pixel data included in the output signal of the solid-state imaging device, respectively; Each of the plurality of measuring means generates a clock signal indicative of the timing of measuring pixel data of the solid-state imaging element and supplies the clock signal to the plurality of measuring means, respectively, thereby causing the plurality of measuring means to be solidified by an interleave operation. And a timing generator for sequentially measuring pixel data of the image pickup device. The method of claim 1, A signal processing circuit for sequentially selecting and acquiring pixel data of the solid-state imaging element measured by the plurality of measuring means by a selector, And the timing generator generates a clock signal indicative of a timing corresponding to the timing at which each of the plurality of measuring means measures pixel data of the solid-state imaging element, and supplies the signal to the selector. The method of claim 2, The timing generator causes the solid-state imaging element to output the same output signal a plurality of times, and generates a clock signal to be supplied to each of the plurality of measurement means, whereby the solid-state imaging element outputs the first output signal, and solid-state imaging. In the case where the element outputs the second output signal, the other measuring means measures the measurement of the pixel data at the same timing in the output signal of the solid-state imaging element, The signal processing circuit includes the pixel data measured by the plurality of measuring means when the solid state imaging element outputs the first output signal, and the plurality of measuring means when the solid state imaging element outputs the second output signal. A signal reading device for averaging and acquiring pixel data measured by the method. In the test apparatus for testing a solid-state imaging device, A plurality of measuring means for measuring pixel data included in the output signal of the solid-state imaging device, respectively; Each of the plurality of measuring means generates a clock signal indicative of a timing for measuring pixel data of the solid-state imaging element, and supplies the clock signal to the plurality of measuring means, respectively, thereby causing the plurality of measuring means to perform the interleaving operation. A timing generator that sequentially measures pixel data, And a pass / fail determination unit that determines pass / fail of a solid-state image pickup device based on the pixel data measured by the plurality of measuring means. In the signal reading device for reading the output signal of the solid-state image sensor, Measuring means for measuring pixel data included in an output signal of the solid-state imaging device; The solid-state imaging device outputs the first output by causing the solid-state imaging device to output the same output signal a plurality of times, and generating and supplying a clock signal indicating the timing at which the measurement means measures the pixel data of the solid-state imaging device to the measuring means. And a timing generator for causing the measuring means to measure other pixel data of the output signal of the solid state image pickup device when the signal is output and when the solid state image pickup device outputs the second output signal. In the test apparatus for testing a solid-state imaging device, Measuring means for measuring pixel data included in an output signal of the solid-state imaging device; The solid-state imaging device outputs the first output by causing the solid-state imaging device to output the same output signal a plurality of times, and generating and supplying a clock signal indicating the timing at which the measurement means measures the pixel data of the solid-state imaging device to the measuring means. A timing generator for causing the measuring means to measure other pixel data of the output signal of the solid-state image pickup device in the case of outputting a signal and in the case where the solid-state image pickup device outputs a second output signal; And a pass / fail determination unit that determines pass / fail of a solid-state imaging element based on the pixel data acquired by the measurement means. In the signal reading device for reading the output signal of the solid-state image sensor, A plurality of measuring means for measuring pixel data included in the output signal of the solid-state imaging device, respectively; And a signal processing circuit for averaging and acquiring pixel data measured by the plurality of measuring means. In the test apparatus for testing a solid-state imaging device, A plurality of measuring means for measuring pixel data included in the output signal of the solid-state imaging device, respectively; A signal processing circuit for averaging and acquiring pixel data measured by the plurality of measuring means; And a pass / fail determination section for judging pass / fail of a solid state image pickup device based on pixel data obtained by averaging the signal processing circuit.

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