JP2010141924A - Signal readout device and test device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal readout device capable of reading a signal from a solid-state imaging element at very high speed. <P>SOLUTION: A signal readout device which reads out the output signal of the solid-state imaging element is equipped with a plurality of measuring means of measuring pixel data included in the output signal of the solid-state imaging element respectively and a timing generator which generates a clock signal indicating when the plurality of measuring means measure the pixel data of the solid-state imaging element respectively and supplies it to the plurality of measuring means to make the plurality of measuring means measure the pixel data of the solid-state imaging element one after another through interleaving operation. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a signal reading device and a test device. In particular, the present invention relates to a signal reading device that reads an output signal of a solid-state image sensor, and a test device that tests the solid-state image sensor.

  A CCD (Charge Coupled Device) transfers electric charges photoelectrically converted by a photodiode based on a clock signal input from a driver (hereinafter referred to as “DR”) and outputs it as an electric signal. The signal reading device measures the reset part and the data part of the electric signal output from the CCD, respectively, and reads the difference between the reset part and the data part as the pixel data of the CCD. Then, the signal level of the pixel data is amplified by a variable gain amplifier (hereinafter referred to as “VGA”), and the pixel data is converted into a digital signal by an analog-digital converter (hereinafter referred to as “ADC”).

  Since the existence of the prior art document is not recognized at the present time, the description regarding the prior art document is omitted.

  In recent years, CCDs that operate at a very high speed have been developed due to demands such as high-quality moving image shooting. For this reason, the signal reading device is also required to be increased in speed, and it is a problem that very high-speed VGA and ADC are required.

  Accordingly, an object of the present invention is to provide a signal reading device and a test device that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  According to the first aspect of the present invention, there is provided a signal reading device for reading out an output signal of a solid-state image sensor, and a plurality of measurement means for measuring pixel data included in the output signal of the solid-state image sensor, and a plurality of measurement means Generate a clock signal indicating the timing at which the pixel data of the solid-state image sensor is measured and supply the clock signal to the plurality of measurement units, thereby causing the plurality of measurement units to sequentially measure the pixel data of the solid-state image sensor by an interleave operation. And a timing generator.

  A signal processing circuit that sequentially selects and acquires pixel data of the solid-state imaging device measured by the plurality of measuring units by a selector; and a timing generator is a timing at which each of the plurality of measuring units measures the pixel data of the solid-state imaging device A clock signal indicating the timing corresponding to may be generated and supplied to the selector.

  The timing generator causes the solid-state imaging device to output the same output signal multiple times and generates a clock signal to be supplied to each of the plurality of measuring means, so that the solid-state imaging device outputs the output signal for the first time, When the imaging device outputs the output signal for the second time, the measurement of pixel data at the same timing in the output signal of the solid-state imaging device is measured by different measuring means, and the signal processing circuit Obtained by averaging pixel data measured by a plurality of measuring means when outputting an output signal and pixel data measured by a plurality of measuring means when the solid-state imaging device outputs an output signal for the second time. May be.

  According to the second aspect of the present invention, there is provided a test apparatus for testing a solid-state imaging device, and each of a plurality of measuring units that respectively measure pixel data included in an output signal of the solid-state imaging device, and the plurality of measuring units. A timing generator for generating a clock signal indicating timing for measuring pixel data of the solid-state image pickup device and supplying the clock signal to the plurality of measurement units, thereby causing the plurality of measurement units to sequentially measure the pixel data of the solid-state image pickup device by an interleave operation; And a pass / fail determination unit that determines pass / fail of the solid-state imaging device based on pixel data measured by a plurality of measuring means.

  According to a third aspect of the present invention, there is provided a signal readout device for reading out an output signal of a solid-state image sensor, the measuring means for measuring pixel data included in the output signal of the solid-state image sensor, and the same output to the solid-state image sensor When a solid-state image sensor outputs an output signal for the first time by outputting a signal multiple times and generating a clock signal indicating the timing at which the measurement means measures pixel data of the solid-state image sensor and supplying it to the measurement means And a timing generator that causes the measurement means to measure pixel data having different output signals from the solid-state image sensor when the solid-state image sensor outputs an output signal for the second time.

  According to a fourth aspect of the present invention, there is provided a test apparatus for testing a solid-state image sensor, and a plurality of measurement means for measuring pixel data included in an output signal of the solid-state image sensor and a plurality of identical output signals on the solid-state image sensor The solid-state image sensor outputs an output signal for the first time by generating a clock signal indicating the timing at which the measurement means measures the pixel data of the solid-state image sensor and supplying the clock signal to the measurement means. When the image sensor outputs an output signal for the second time, the timing generator that causes the measurement means to measure pixel data with different output signals from the solid-state image sensor, and the quality of the solid-state image sensor based on the pixel data acquired by the measurement means A pass / fail judgment unit for judging.

  According to a fifth aspect of the present invention, there is provided a signal readout device for reading out an output signal of a solid-state image sensor, and a plurality of measurement means for measuring pixel data included in the output signal of the solid-state image sensor, and a plurality of measurement means A signal processing circuit that averages and acquires the pixel data measured by the above.

  According to a sixth aspect of the present invention, there is provided a test apparatus for testing a solid-state image sensor, which is measured by a plurality of measurement units that respectively measure pixel data included in an output signal of the solid-state image sensor, and a plurality of measurement units. A signal processing circuit that averages and acquires the pixel data, and a quality determination unit that determines the quality of the solid-state imaging device based on the pixel data averaged and acquired by the signal processing circuit.

  Note that the above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  According to the signal reading device of the present invention, signals can be read from the solid-state imaging device at a very high speed.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the claimed invention, and all combinations of features described in the embodiments are inventions. It is not always essential to the solution.

  FIG. 1 shows an example of the configuration of a test apparatus 100 according to the first embodiment of the present invention. The test apparatus 100 includes a first measuring unit 102, a second measuring unit 202, a DR 120, a timing generator (hereinafter referred to as “TG”) 122, a signal processing circuit 124, and a pass / fail judgment unit 128. The test apparatus 100 is an example of a signal reading apparatus that reads an output signal of a solid-state imaging device (hereinafter referred to as “DUT”) of the present invention. The DUT is a CCD, for example, and outputs electric charges photoelectrically converted by a photodiode as an electric signal.

  The first measuring means 102 includes a correlated double sampling circuit (hereinafter referred to as “CDS”) 104, a VGA 106, and an ADC 108. The CDS 104 includes a sample hold (hereinafter referred to as “S & H”) 110, S & H 112, S & H 114, and a subtractor 116. The second measuring unit 202 includes a CDS 204, a VGA 206, and an ADC 208. CDS 204 includes S & H 210, S & H 212, S & H 214, and subtractor 216. In addition, the signal processing circuit 124 includes a selector 126.

  The first measuring means 102 and the second measuring means 202 are examples of the measuring means of the present invention, and the measuring means of the present invention has other circuit configurations of the first measuring means 102 and the second measuring means 202. May be. Further, the first measuring unit 102 and the second measuring unit 202 may include an amplifier having a fixed gain instead of the VGA 106 or 206.

  The TG 122 generates a clock signal indicating the timing at which the DUT 10 outputs an output signal via the DR 120 and supplies the clock signal to the DUT 10. The DUT 10 outputs an output signal including continuous pixel data based on the clock signal input from the DR 120 and supplies the output signal to the first measurement unit 102 and the second measurement unit 202.

  In addition, the TG 122 generates a clock signal indicating the timing at which each of the first measuring unit 102 and the second measuring unit 202 measures the pixel data included in the output signal of the DUT 10 to generate the first measuring unit 102 and the second measuring unit 202. To supply each. Then, the first measuring unit 102 and the second measuring unit 202 respectively measure pixel data included in the output signal of the DUT 10 based on the clock signal supplied from the TG 122.

  Specifically, the S & H 110 samples the voltage value of the reset unit of the output signal of the DUT 10 based on the clock signal (SHP1) input from the TG 122. The S & H 112 acquires the voltage value sampled by the S & H 110 based on the clock signal (SHD1) input from the TG 122 and supplies the voltage value to the subtractor 116. The S & H 114 samples the voltage value of the data portion of the output signal of the DUT 10 based on the clock signal (SHD1) input from the TG 122 and supplies the sampled voltage value to the subtractor 116. That is, the clock signal (SHP1) and the clock signal (SHD1) have a phase difference corresponding to the time interval between the reset part and the data part of the output signal of the DUT 10. Further, the S & H 112 and the S & H 114 operate based on the same clock signal (SHD1), thereby supplying a voltage value to the subtractor 116 in synchronization.

  The subtractor 116 calculates a difference between the voltage value of the reset unit supplied from the S & H 112 and the voltage value input from the S & H 114 and outputs the difference as pixel data. The VGA 106 amplifies the pixel data output from the subtractor 116. The ADC 108 converts the pixel data amplified by the VGA 106 into a digital signal based on the clock signal (AD 1) input from the TG 122 and supplies the digital signal to the signal processing circuit 124.

  The S & H 210 samples the voltage value of the reset unit of the output signal of the DUT 10 based on the clock signal (SHP2) input from the TG 122. The S & H 212 acquires the voltage value sampled by the S & H 210 based on the clock signal (SHD2) input from the TG 122 and supplies the voltage value to the subtractor 216. The S & H 214 samples the voltage value of the data portion of the output signal of the DUT 10 based on the clock signal (SHD2) input from the TG 122 and supplies the sampled value to the subtracter 216. That is, the clock signal (SHP2) and the clock signal (SHD2) have a phase difference corresponding to the time interval between the reset part and the data part of the output signal of the DUT 10. Further, the S & H 212 and the S & H 214 operate based on the same clock signal (SHD2), thereby supplying a voltage value to the subtracter 216 in synchronization.

  The subtractor 216 calculates a difference between the voltage value of the reset unit supplied from the S & H 212 and the voltage value input from the S & H 214 and outputs the difference as pixel data. The VGA 206 amplifies the pixel data output from the subtractor 116. The ADC 208 converts the pixel data amplified by the VGA 206 into a digital signal based on the clock signal (AD 2) input from the TG 122 and supplies the digital signal to the signal processing circuit 124.

  In addition, the TG 122 generates a clock signal (SEL) indicating a timing corresponding to a timing at which each of the first measuring unit 102 and the second measuring unit 202 measures the pixel data included in the output signal of the DUT 10 and supplies the clock signal (SEL) to the selector 126. To do. Then, the signal processing circuit 124 sequentially selects pixel data included in the output signal of the DUT 10 measured by the first measuring unit 102 and the second measuring unit 202 based on the clock signal (SEL) input from the TG 122 by the selector 126. And get.

  The pass / fail determination unit 128 determines pass / fail of the DUT 10 based on the pixel data measured by the first measuring unit 102 and the second measuring unit 202 and subjected to desired signal processing by the signal processing circuit 124. With the above operation, the test apparatus 100 tests the DUT 10 based on the pixel data included in the output signal.

  In this example, the test apparatus 100 includes two measurement units, ie, a first measurement unit 102 and a second measurement unit 202. In another example, the test apparatus 100 includes three or more measurement units, The pixel data included in the output signal of the DUT 10 may be measured by an interleaving operation using three or more measuring units.

  2 to 5 show a first example of the operation of the test apparatus 100 according to the first embodiment. 2 shows the operation of the first measuring means 102 and the second measuring means 202 when the DUT 10 outputs an output signal for the first time, and FIG. 3 shows the first when the DUT 10 outputs the output signal for the second time. The operations of the measuring means 102 and the second measuring means 202 are shown. 4 and 5 show pixel data acquired by the signal processing circuit 124. FIG.

  The TG 122 generates a clock signal indicating the timing at which each of the first measuring unit 102 and the second measuring unit 202 measures the pixel data included in the output signal of the DUT 10, and sends the clock signal to the first measuring unit 102 and the second measuring unit 202. By supplying each, the first measuring means 102 and the second measuring means 202 are sequentially made to measure the pixel data included in the output signal of the DUT 10 by the interleaving operation. Further, the TG 122 supplies the clock signal indicating the timing at which the DUT 10 outputs the output signal via the DR 120 a plurality of times, thereby causing the DUT 10 to output the same output signal a plurality of times. The TG 122 generates a clock signal indicating the timing at which each of the first measurement unit 102 and the second measurement unit 202 measures the pixel data included in the output signal of the DUT 10, so that the DUT 10 outputs the output signal for the first time. In the case of outputting and in the case where the DUT 10 outputs an output signal for the second time, the measurement of pixel data at the same timing in the output signal of the DUT 10 is caused to be measured by different measuring means.

  First, the operation of the test apparatus 100 when the DUT 10 outputs the output signal (IN) for the first time will be described with reference to FIG. The TG 122 sets the phase difference between the clock signal (SHP1, SHD1, AD1) and the clock signal (SHP2, SHD2, AD2) to the length of the pixel data included in the output signal (IN) of the DUT 10, and A clock signal (SHP1, SHD1, AD1) and a clock signal (SHP2, SHD2, AD2) are supplied to the measuring means 102 and the second measuring means 202, respectively. Accordingly, the first measuring unit 102 and the second measuring unit 202 measure in order for each pixel data included in the output signal (IN). That is, the first measuring unit 102 measures the pixel data (N), the second measuring unit 202 measures the pixel data (N + 1), the first measuring unit 102 measures the pixel data (N + 2), and the second measurement. Means 202 measures pixel data (N + 3).

  Next, the operation of the test apparatus 100 when the DUT 10 outputs the output signal (IN) for the second time will be described with reference to FIG. When the DUT 10 outputs the output signal (IN) for the first time, the TG 122 has the same timing as the clock signal (SHP2, SHD2, AD2) supplied to the second measuring means 202, and the DUT 10 outputs the output signal for the second time. When outputting (IN), the clock signals (SHP1, SHD1, AD1) are supplied to the first measuring means 102. In addition, the TG 122 has the same timing as the clock signal (SHP1, SHD1, AD1) supplied to the first measuring means 102 when the DUT 10 outputs the output signal (IN) for the first time. When outputting the output signal (IN), the clock signals (SHP2, SHD2, AD2) are supplied to the second measuring means 202.

  Thereby, the first measuring unit 102 and the second measuring unit 202 sequentially measure pixel data different from the case where the DUT 10 outputs the output signal (IN) for the first time. That is, the second measuring unit 202 measures the pixel data (N), the first measuring unit 102 measures the pixel data (N + 1), the second measuring unit 202 measures the pixel data (N + 2), and the first measurement. Means 102 measures pixel data (N + 3).

  Next, the operation of the signal processing circuit 124 will be described with reference to FIG. The TG 122 supplies the selector 126 with a clock signal (SEL) corresponding to the timing at which the first measurement unit 102 and the second measurement unit 202 measure the pixel data. Then, the signal processing circuit 124 selects and acquires the pixel data measured by the first measurement unit 102 and the second measurement unit 202 by the selector 126 based on the clock signal (SEL).

  That is, the signal processing circuit 124 acquires the pixel data (N) from the first measurement unit 102 and the pixel data (N + 1) from the second measurement unit 202 when the DUT 10 outputs the output signal for the first time. The pixel data (N + 2) is acquired from the first measuring unit 102, and the pixel data (N + 3) is acquired from the second measuring unit 202. Further, the signal processing circuit 124 acquires the pixel data (N) from the second measuring unit 202 and the pixel data (N + 1) from the first measuring unit 102 when the DUT 10 outputs the output signal for the second time. The pixel data (N + 2) is acquired from the second measuring unit 202, and the pixel data (N + 3) is acquired from the first measuring unit 102.

  When the DUT 10 outputs the output signal for the first time, the signal processing circuit 124 outputs the pixel data measured by the first measuring means 102 and the second measuring means 202 and when the DUT 10 outputs the output signal for the second time. The pixel data measured by the first measuring means 102 and the second measuring means 202 are averaged and acquired and stored in the memory.

  Next, a modified example of the operation of the signal processing circuit 124 will be described with reference to FIG. In the description of FIG. 4, the signal processing circuit 124 sequentially selects and acquires the pixel data measured by the first measuring unit 102 or the second measuring unit 202 by the selector 126, but the signal processing circuit 124 in the modification example is The selector 126 may not be provided. That is, when the DUT 10 outputs the output signal for the first time, the pixel data measured by the first measuring unit 102, the pixel data measured by the second measuring unit 202, and the DUT 10 outputs the output signal for the second time. In this case, the pixel data measured by the first measuring unit 102 and the pixel data measured by the second measuring unit 202 are stored in the memory. Then, the pixel data measured by the first measuring unit 102 for the first time and the pixel data measured by the second measuring unit 202 for the second time are averaged, and the pixel data measured by the second measuring unit 202 for the first time are compared with the first pixel data. The measuring means 102 averages the pixel data measured for the second time.

  According to the test apparatus 100 according to the present example, the DUT 10 that operates at a high speed can be tested by providing a plurality of measurement units and measuring the pixel data included in the output signal of the DUT 10 by an interleave operation. Even if there is a measurement error due to a mismatch between the first measurement unit 102 and the second measurement unit 202, when the image is reproduced based on the pixel data, the first measurement unit 102 and the second measurement unit 202 It is possible to prevent the occurrence of a stripe pattern due to the mismatch.

Specifically, when the level of the pixel data included in the output signal of the DUT 10 is x, the measured value by the first measuring unit 102 is y ₁ = ax + b, and the measured value by the second measuring unit 202 is y ₂ = cx + d, the signal The pixel data averaged and acquired by the processing circuit 124 is Y = (a + b) x / 2 + (b + d) x / 2. That is, since (a + b) / 2 and (b + d) / 2 are constants determined by the characteristics of the first measuring unit 102 and the second measuring unit 202, the pixel data acquired by the signal processing circuit 124 is one measurement. Looks like the pixel data measured by the means. Therefore, it is possible to prevent the occurrence of measurement error due to mismatch between the first measurement unit 102 and the second measurement unit 202.

  In addition, according to the test apparatus 100 according to the present example, the pixel data measured by the first measurement unit 102 and the pixel data measured by the second measurement unit 202 are averaged to generate a random generated by the DUT 10 or the test apparatus 100. Noise can be reduced.

  6 to 7 show a second example of the operation of the test apparatus 100 according to the first embodiment. FIG. 6 shows operations of the first measuring means 102 and the second measuring means 202. FIG. 7 shows pixel data acquired by the signal processing circuit 124.

  The TG 122 generates a clock signal indicating the timing at which each of the first measuring unit 102 and the second measuring unit 202 measures the pixel data included in the output signal of the DUT 10, and sends the clock signal to the first measuring unit 102 and the second measuring unit 202. By supplying each, the first measuring means 102 and the second measuring means 202 are made to measure the pixel data included in the output signal of the DUT 10 simultaneously.

  First, the operation of the test apparatus 100 will be described with reference to FIG. The TG 122 supplies a clock signal (SHP1, SHD1, AD1) to the first measuring means 102 and a clock signal (SHP2, SHD2, AD2) having the same timing as the clock signals (SHP1, SHD1, AD1) to the second measuring means 202. ). Accordingly, the first measuring unit 102 and the second measuring unit 202 simultaneously measure pixel data (N, N + 1, N + 2, N + 3...) Included in the output signal (IN).

  Next, the operation of the signal processing circuit 124 will be described with reference to FIG. The signal processing circuit 124 acquires pixel data measured simultaneously by the first measuring unit 102 and the second measuring unit 202, respectively. The signal processing circuit 124 averages and acquires the pixel data measured by the first measuring unit 102 and the pixel data measured by the second measuring unit 202, and stores the averaged pixel data in the memory.

  According to the test apparatus 100 according to this example, the pixel data measured by the first measurement unit 102 and the pixel data measured by the second measurement unit 202 are averaged, so that the DUT 10 or the test apparatus is not increased without increasing the number of measurements. Random noise generated by 100 can be reduced.

  FIG. 8 shows an example of the configuration of a test apparatus 800 according to the second embodiment of the present invention. The test apparatus 100 includes measurement means 802, DR820, TG822, a signal processing circuit 824, and a pass / fail judgment unit 828. The test apparatus 800 is an example of a signal reading apparatus that reads out an output signal of the solid-state imaging device of the present invention. The measuring unit 802 includes a CDS 804, a VGA 806, and an ADC 808. CDS 804 includes S & H 810, S & H 812, S & H 814, and subtractor 816.

  The measuring unit 802 is an example of the measuring unit of the present invention, and the measuring unit of the present invention may have other circuit configurations of the measuring unit 802. Further, the measuring unit 802 may include a fixed gain amplifier instead of the VGA 806.

  The TG 822 generates a clock signal indicating the timing at which the DUT 10 outputs an output signal via the DR 820 and supplies the clock signal to the DUT 10. The DUT 10 outputs an output signal including continuous pixel data based on the clock signal input from the DR 820 and supplies the output signal to the measuring unit 802.

  Further, the TG 822 generates a clock signal indicating the timing at which the measuring unit 802 measures the pixel data included in the output signal of the DUT 10 and supplies the clock signal to the measuring unit 802. Then, the measuring unit 802 measures pixel data included in the output signal of the DUT 10 based on the clock signal supplied from the TG 822.

  Specifically, the S & H 810 samples the voltage value of the reset unit of the output signal of the DUT 10 based on the clock signal (SHP) input from the TG 822. The S & H 812 acquires the voltage value sampled by the S & H 810 based on the clock signal (SHD) input from the TG 822 and supplies it to the subtracter 816. The S & H 814 samples the voltage value of the data portion of the output signal of the DUT 10 based on the clock signal (SHD) input from the TG 822 and supplies the sampled voltage value to the subtracter 816. That is, the clock signal (SHP) and the clock signal (SHD) have a phase difference corresponding to the time interval between the reset portion and the data portion of the output signal of the DUT 10. Further, the S & H 812 and the S & H 814 operate based on the same clock signal (SHD), thereby supplying a voltage value to the subtracter 816 in synchronization.

  The subtractor 816 calculates a difference between the voltage value of the reset unit supplied from the S & H 812 and the voltage value input from the S & H 814, and outputs the difference as pixel data. The VGA 806 amplifies the pixel data output from the subtracter 816. The ADC 808 converts the pixel data amplified by the VGA 806 into a digital signal based on the clock signal (AD) input from the TG 822 and supplies the digital signal to the signal processing circuit 824.

  Further, the TG 822 generates a clock signal indicating a timing corresponding to the timing at which the measuring unit 802 measures the pixel data included in the output signal of the DUT 10 and supplies the clock signal to the signal processing circuit 824. Then, the signal processing circuit 824 acquires pixel data included in the output signal of the DUT 10 measured by the measuring unit 802 based on the clock signal supplied from the TG 822.

  The pass / fail determination unit 828 determines pass / fail of the DUT 10 based on the pixel data measured by the measuring unit 802 and subjected to desired signal processing by the signal processing circuit 824. With the above operation, the test apparatus 800 tests the DUT 10 based on the pixel data included in the output signal.

  9 to 11 show an example of the operation of the test apparatus 800 according to the second embodiment. FIG. 9 shows the operation of the measuring means 802 when the DUT 10 outputs the output signal for the first time, and FIG. 10 shows the operation of the measuring means 802 when the DUT 10 outputs the output signal for the second time. FIG. 11 shows pixel data acquired by the signal processing circuit 824.

  The TG 822 causes the DUT 10 to output the same output signal a plurality of times, and generates a clock signal indicating the timing at which the measurement unit 802 measures the pixel data included in the output signal of the DUT 10 and supplies the clock signal to the measurement unit 802. When the DUT 10 outputs an output signal for the first time and when the DUT 10 outputs an output signal for the second time, the measurement unit 802 measures different pixel data of the output signal of the DUT 10.

  First, the operation of the test apparatus 800 when the DUT 10 outputs the output signal (IN) for the first time will be described with reference to FIG. The TG 822 sets the sampling timing indicated by the clock signals (SHP, SHD, AD) to an interval twice the pixel data included in the output signal (IN) of the DUT 10 and sends the clock signal (SHP, SHD, AD). Thereby, the measuring unit 802 measures the pixel data included in the output signal (IN) by one. That is, the measuring unit 802 measures pixel data (N, N + 2, N + 4...).

  Next, the operation of the test apparatus 800 when the DUT 10 outputs the output signal (IN) for the second time will be described with reference to FIG. The TG 822 shifts the clock signal (SHP, SHD, AD) supplied to the measuring means 802 when the DUT 10 outputs the output signal (IN) for the first time by the interval of the pixel data included in the output signal of the DUT 10. When the DUT 10 outputs the output signal (IN) for the second time, it is supplied to the measuring means 802. As a result, the measurement unit 802 sequentially measures pixel data different from the case where the DUT 10 outputs the output signal (IN) for the first time. That is, the measuring means 802 measures pixel data (N + 1, N + 3, N + 5...).

  Next, the operation of the signal processing circuit 824 will be described with reference to FIG. When the DUT 10 outputs an output signal for the first time, the signal processing circuit 824 acquires pixel data (N, N + 2, N + 4...) From the measuring unit 802 and stores it in the memory. Further, when the DUT 10 outputs an output signal for the second time, the signal processing circuit 824 acquires pixel data (N + 1, N + 3, N + 5...) From the measuring unit 802 and stores it in the memory.

  According to the test apparatus 800 according to this example, the pixel data included in the output signal of the DUT 10 is measured twice every other time while the clock signal indicating the timing for measuring the pixel data included in the output signal of the DUT 10 is shifted. By doing this, it is possible to measure all of the pixel data contained in the output signal of the DUT 10 operating at high speed with a simple structure, and to test the DUT 10.

  In this example, the TG 822 sets the sampling timing indicated by the clock signal (SHP, SHD, AD) to the measuring unit 802 with an interval twice the pixel data included in the output signal (IN) of the DUT 10. Although the embodiment in which the output signal of the DUT 10 is measured twice has been described, if the measurement unit 802 measures the output signal of the DUT 10 N times at intervals of N times the pixel data included in the output signal (IN) of the DUT 10 Good.

  FIG. 12 shows an example of the configuration of a test apparatus 1000 according to the third embodiment of the present invention. The test apparatus 1000 includes measurement means 1102, DR 1120, TG 1122, signal processing circuit 1124, and pass / fail judgment unit 1128. The test apparatus 1000 is an example of a signal reading apparatus that reads an output signal of the solid-state imaging device of the present invention.

  The measuring unit 1102 includes a first CDS 1104, a second CDS 1204, a selector 1105, a VGA 1106, and an ADC 1108. The first CDS 1104 includes S & H 1110, S & H 1112, S & H 1114, and a subtracter 1116. The second CDS 1204 includes an S & H 1210, an S & H 1212, an S & H 1214, and a subtractor 1216.

  The first CDS 1104 and the second CDS 1204 are examples of the measuring unit of the present invention, and the measuring unit of the present invention may have other circuit configurations of the first CDS 1104 and the second CDS 1204. Further, the measuring means 1102 may have a fixed gain amplifier instead of the VGA 1106.

  The TG 1122 generates a clock signal indicating the timing at which the DUT 10 outputs an output signal via the DR 1120 and supplies the clock signal to the DUT 10. The DUT 10 outputs an output signal including continuous pixel data based on the clock signal input from the DR 1120 and supplies the output signal to the measuring unit 1102.

  Further, the TG 1122 generates a clock signal indicating the timing at which each of the first CDS 1104 and the second CDS 1204 measures the pixel data included in the output signal of the DUT 10 and supplies the clock signal to the first CDS 1104 and the second CDS 1204, respectively. Then, the first CDS 1104 and the second CDS 1204 respectively measure pixel data included in the output signal of the DUT 10 based on the clock signal supplied from the TG 1122.

  Specifically, the S & H 1110 samples the voltage value of the reset unit of the output signal of the DUT 10 based on the clock signal (SHP1) input from the TG 1122. The S & H 1112 acquires the voltage value sampled by the S & H 1110 based on the clock signal (SHD1) input from the TG 1122, and supplies the voltage value to the subtractor 1116. The S & H 1114 samples the voltage value of the data portion of the output signal of the DUT 10 based on the clock signal (SHD1) input from the TG 1122 and supplies the sampled voltage value to the subtracter 1116. That is, the clock signal (SHP1) and the clock signal (SHD1) have a phase difference corresponding to the time interval between the reset part and the data part of the output signal of the DUT 10. Further, the S & H 1112 and the S & H 1114 operate based on the same clock signal (SHD1) to supply a voltage value to the subtracter 1116 in synchronization. The subtractor 1116 calculates the difference between the voltage value of the reset unit supplied from the S & H 1112 and the voltage value input from the S & H 1114, outputs it as pixel data, and supplies the pixel data to the selector 1105.

  The S & H 1210 samples the voltage value of the reset unit of the output signal of the DUT 10 based on the clock signal (SHP2) input from the TG 1122. The S & H 1212 acquires the voltage value sampled by the S & H 1210 based on the clock signal (SHD2) input from the TG 1122 and supplies it to the subtractor 1216. The S & H 1214 samples the voltage value of the data portion of the output signal of the DUT 10 based on the clock signal (SHD2) input from the TG 1122 and supplies the sampled voltage value to the subtractor 1216. That is, the clock signal (SHP2) and the clock signal (SHD2) have a phase difference corresponding to the time interval between the reset part and the data part of the output signal of the DUT 10. Further, the S & H 1212 and the S & H 1214 operate based on the same clock signal (SHD2) to supply a voltage value to the subtractor 1216 in synchronization. The subtractor 1216 calculates a difference between the voltage value of the reset unit supplied from the S & H 1212 and the voltage value input from the S & H 1214, outputs the difference as pixel data, and supplies the pixel data to the selector 1105.

  The selector 1105 sequentially selects pixel data included in the output signal of the DUT 10 measured by the first CDS 1104 and the second CDS 1204 based on the clock signal (SEL) input from the TG 1122 and supplies the selected pixel data to the VGA 1106. The VGA 1106 amplifies the pixel data output from the selector 1105. The ADC 1108 converts the pixel data amplified by the VGA 1106 into a digital signal based on the clock signal (AD) input from the TG 1122 and supplies the digital signal to the signal processing circuit 1124.

  The pass / fail judgment unit 1128 judges pass / fail of the DUT 10 based on the pixel data measured by the measuring unit 1102 and subjected to desired signal processing by the signal processing circuit 1124. With the above operation, the test apparatus 1000 tests the DUT 10 based on the pixel data included in the output signal.

  In this example, the measuring unit 1102 includes two CDSs of the first CDS 1104 and the second CDS 1204. In another example, the test apparatus 1000 includes three or more CDSs, and the three or more CDSs of the DUT 10 Pixel data included in the output signal may be measured by an interleave operation.

  13 to 15 show an example of the operation of the test apparatus 1000 according to the third embodiment. FIG. 13 shows the operation of the measuring means 1102 when the DUT 10 outputs the output signal for the first time, and FIG. 14 shows the operation of the measuring means 1102 when the DUT 10 outputs the output signal for the second time. FIG. 15 shows pixel data acquired by the signal processing circuit 1124.

  The TG 1122 generates a clock signal indicating the timing at which each of the first CDS 1104 and the second CDS 1204 measures the pixel data included in the output signal of the DUT 10 and supplies the clock signal to the first CDS 1104 and the second CDS 1204, respectively. The pixel data included in the output signal of the DUT 10 is sequentially measured by the interleave operation. Also, the TG 1122 causes the DUT 10 to output the same output signal a plurality of times by supplying a clock signal indicating the timing at which the DUT 10 outputs an output signal a plurality of times via the DR 1120. The TG 1122 generates a clock signal indicating the timing at which each of the first CDS 1104 and the second CDS 1204 measures pixel data included in the output signal of the DUT 10, so that the DUT 10 outputs the output signal for the first time, and the DUT 10 When the output signal is output for the second time, the pixel data at the same timing in the output signal of the DUT 10 is measured by different CDSs.

  First, the operation of the test apparatus 1000 when the DUT 10 outputs the output signal (IN) for the first time will be described with reference to FIG. The TG 1122 sets the phase difference between the clock signal (SHP1, SHD1) and the clock signal (SHP2, SHD2) to the length of the pixel data included in the output signal (IN) of the DUT 10, and sets the first CDS 1104 and the second CDS 1204. A clock signal (SHP1, SHD1) and a clock signal (SHP2, SHD2) are supplied to each. Accordingly, the first CDS 1104 and the second CDS 1204 measure in order for each pixel data included in the output signal (IN). That is, the first CDS 1104 measures pixel data (N), the second CDS 1204 measures pixel data (N + 1), the first CDS 1104 measures pixel data (N + 2), and the second CDS 1204 measures pixel data (N + 3).

  Further, the TG 1122 supplies the selector 1105 with a clock signal (SEL) corresponding to the timing at which the first CDS 1104 and the second CDS 1204 respectively measure the pixel data. The selector 1105 sequentially selects and acquires pixel data measured by the first CDS 1104 and the second CDS 1204 based on the clock signal (SEL).

  Further, the TG 1122 supplies the ADC 1108 with a clock signal (AD) indicating the timing at which the ADC 1108 converts the pixel data acquired by the selector 1105 into digital data. The ADC 1108 converts the pixel data selected by the selector 1105 and amplified by the VGA 1106 based on the clock signal (AD) into digital data and supplies the digital data to the signal processing circuit 1124.

  Next, the operation of the test apparatus 1000 when the DUT 10 outputs the output signal (IN) for the second time will be described with reference to FIG. When the DUT 10 outputs the output signal (IN) for the first time, the TG 1122 outputs the output signal (IN) for the second time at the same timing as the clock signals (SHP2, SHD2) are supplied to the second CDS 1204. In this case, the clock signals (SHP1, SHD1) are supplied to the first CDS 1104. Further, the TG 1122 outputs the output signal (IN) at the same timing as the clock signal (SHP1, SHD1) is supplied to the first CDS 1104 when the DUT 10 outputs the output signal (IN) at the first time. To output the clock signal (SHP2, SHD2) to the second CDS 1204.

  Accordingly, the first CDS 1104 and the second CDS 1204 sequentially measure pixel data different from the case where the DUT 10 outputs the output signal (IN) for the first time. That is, the second CDS 1204 measures pixel data (N), the first CDS 1104 measures pixel data (N + 1), the second CDS 1204 measures pixel data (N + 2), and the first CDS 1104 measures pixel data (N + 3).

  In addition, when the DUT 10 outputs the output signal (IN) for the first time, the TG 1122 outputs the output signal (IN) for the second time at the same timing as when the clock signal (SEL) is supplied to the selector 1105. In this case, a clock signal (SEL) is supplied to the selector 1105. In addition, when the DUT 10 outputs the output signal (IN) for the first time, the TG 1122 outputs the output signal (IN) for the second time at the same timing as when the clock signal (AD) is supplied to the ADC 1108. In this case, a clock signal (AD) is supplied to the ADC 1108.

  Then, similarly to the case where the DUT 10 outputs the output signal (IN) for the first time, the selector 1105, based on the clock signal (SEL), when the DUT 10 outputs the output signal (IN) for the second time. Pixel data measured by the 1CDS 1104 and the second CDS 1204 are sequentially selected and acquired. The ADC 1108 then selects the selector 1105 based on the clock signal (AD) when the DUT 10 outputs the output signal (IN) for the second time, as in the case where the DUT 10 outputs the output signal (IN) for the first time. The pixel data selected and amplified by the VGA 1106 is converted into digital data and supplied to the signal processing circuit 1124.

  Next, the operation of the signal processing circuit 1124 will be described with reference to FIG. The signal processing circuit 1124 acquires the pixel data measured by the first CDS 1104 and the second CDS 1204 and selected by the selector 1105 from the ADC 1108. That is, the signal processing circuit 1124 acquires the pixel data (N) measured by the first CDS 1104 and the pixel data (N + 1) measured by the second CDS 1204 when the DUT 10 outputs the output signal for the first time, The pixel data (N + 2) measured by the 1CDS 1104 is acquired, and the pixel data (N + 3) measured by the second CDS 1204 is acquired. The signal processing circuit 1124 acquires the pixel data (N) measured by the second CDS 1204 and the pixel data (N + 1) measured by the first CDS 1104 when the DUT 10 outputs the output signal for the second time. The pixel data (N + 2) measured by the 2CDS 1204 is acquired, and the pixel data (N + 3) measured by the first CDS 1104 is acquired.

  The signal processing circuit 1124 then outputs pixel data measured by the first CDS 1104 and the second CDS 1204 when the DUT 10 outputs the output signal for the first time, and the first CDS 1104 and the second CDS 1204 when the DUT 10 outputs the output signal for the second time. Are obtained by averaging the pixel data measured by the above and stored in the memory.

  According to the test apparatus 1000 according to the present example, the DUT 10 that operates at high speed can be tested by providing a plurality of CDSs and measuring pixel data included in the output signal of the DUT 10 by an interleave operation. Further, even when there is a measurement error due to a mismatch between the first CDS 1104 and the second CDS 1204, a stripe pattern due to the mismatch between the first CDS 1104 and the second CDS 1204 is prevented when an image is reproduced based on pixel data. be able to.

Specifically, if the level of the pixel data included in the output signal of the DUT 10 is x, the measured value by the first CDS 1104 is y ₁ = ax + b, and the measured value by the second CDS 1204 is y ₂ = cx + d, the signal processing circuit 1124 performs averaging. The pixel data thus obtained is Y = (a + b) x / 2 + (b + d) x / 2. That is, since (a + b) / 2 and (b + d) / 2 are constants determined by the characteristics of the first CDS 1104 and the second CDS 1204, the pixel data acquired by the signal processing circuit 1124 is a pixel measured by one measuring unit. Looks like data. Therefore, it is possible to prevent a measurement error from occurring due to a mismatch between the first CDS 1104 and the second CDS 1204.

  Further, according to the test apparatus 1000 according to this example, the random noise generated by the DUT 10 or the test apparatus 1000 can be reduced by averaging the pixel data measured by the first CDS 1104 and the pixel data measured by the second CDS 1204. it can.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various modifications or improvements can be added to the above embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

1 is a diagram illustrating an example of a configuration of a test apparatus 100. FIG. It is a figure which shows operation | movement of the 1st measurement means 102 and the 2nd measurement means 202. It is a figure which shows operation | movement of the 1st measurement means 102 and the 2nd measurement means 202. It is a figure which shows the pixel data which the signal processing circuit 124 acquires. It is a figure which shows the pixel data which the signal processing circuit 124 acquires. It is a figure which shows operation | movement of the 1st measurement means 102 and the 2nd measurement means 202. FIG. It is a figure which shows the pixel data which the signal processing circuit 124 acquires. 2 is a diagram illustrating an example of a configuration of a test apparatus 800. FIG. FIG. 10 is a diagram showing the operation of the measuring means 802. FIG. 10 is a diagram showing the operation of the measuring means 802. 7 is a diagram illustrating pixel data acquired by a signal processing circuit 824. FIG. It is a figure which shows an example of a structure of the test apparatus. FIG. 10 is a diagram showing the operation of the measuring means 1102. FIG. 10 is a diagram showing the operation of the measuring means 1102. It is a figure which shows the pixel data which the signal processing circuit 1124 acquires.

10 DUT
100 test apparatus 102 first measuring means 104 CDS
106 VGA
108 ADC
110 S & H
112 S & H
114 S & H
116 Subtractor 120 DR
122 TG
124 signal processing circuit 126 selector 128 pass / fail judgment unit 202 second measuring means 204 CDS
206 VGA
208 ADC
210 S & H
212 S & H
214 S & H
216 Subtractor 800 Test device 802 Measuring means 804 CDS
806 VGA
808 ADC
810 S & H
812 S & H
814 S & H
816 Subtractor 820 DR
822 TG
824 signal processing circuit 828 pass / fail judgment unit 1000 test apparatus 1102 measuring means 1104 first CDS
1105 Selector 1106 VGA
1108 ADC
1110 S & H
1112 S & H
1114 S & H
1116 Subtractor 1120 DR
1122 TG
1124 signal processing circuit 1128 pass / fail judgment unit 1204 second CDS
1210 S & H
1212 S & H
1214 S & H
1216 subtractor

Claims (8)

A signal reading device for reading an output signal of a solid-state imaging device,
A plurality of measuring means each for measuring pixel data included in the output signal of the solid-state imaging device;
Each of the plurality of measurement units generates a clock signal indicating timing for measuring pixel data of the solid-state image sensor and supplies the clock signal to each of the plurality of measurement units, so that the solid-state image sensor is interleaved with the plurality of measurement units. A signal readout device comprising a timing generator for sequentially measuring the pixel data of the first and second pixels. A signal processing circuit for sequentially selecting and acquiring pixel data of the solid-state imaging device measured by the plurality of measuring means by a selector;
2. The signal readout device according to claim 1, wherein the timing generator generates a clock signal indicating a timing corresponding to a timing at which each of the plurality of measuring units measures pixel data of the solid-state imaging device and supplies the clock signal to the selector. The timing generator causes the solid-state imaging device to output the same output signal a plurality of times, and generates a clock signal to be supplied to each of the plurality of measuring means, whereby the solid-state imaging device outputs an output signal for the first time; In the case where the solid-state image sensor outputs an output signal for the second time, the measurement means measures the pixel data at the same timing in the output signal of the solid-state image sensor,
The signal processing circuit includes: pixel data measured by the plurality of measurement means when the solid-state image sensor outputs an output signal for the first time; and the plurality of pixel data measured when the solid-state image sensor outputs an output signal for the second time. The signal reading device according to claim 2, wherein the pixel data measured by the measuring means is averaged and acquired. A test apparatus for testing a solid-state imaging device,
A plurality of measuring means each for measuring pixel data included in the output signal of the solid-state imaging device;
Each of the plurality of measurement units generates a clock signal indicating timing for measuring pixel data of the solid-state image sensor and supplies the clock signal to each of the plurality of measurement units, so that the solid-state image sensor is interleaved with the plurality of measurement units. A timing generator that sequentially measures the pixel data of
A test apparatus comprising: a pass / fail determination unit that determines pass / fail of the solid-state imaging device based on the pixel data measured by the plurality of measuring means. A signal reading device for reading an output signal of a solid-state imaging device,
Measuring means for measuring pixel data included in the output signal of the solid-state imaging device;
The solid-state image sensor outputs the same output signal to the solid-state image sensor a plurality of times, and generates a clock signal indicating the timing at which the measurement unit measures the pixel data of the solid-state image sensor and supplies the clock signal to the measurement unit. A signal readout comprising a timing generator that causes the measurement means to measure pixel data having different output signals from the solid-state image sensor when the output signal is output the first time and when the solid-state image sensor outputs an output signal the second time. apparatus. A test apparatus for testing a solid-state imaging device,
Measuring means for measuring pixel data included in the output signal of the solid-state imaging device;
The solid-state image sensor outputs the same output signal to the solid-state image sensor a plurality of times, and generates a clock signal indicating the timing at which the measurement unit measures the pixel data of the solid-state image sensor and supplies the clock signal to the measurement unit. A timing generator that causes the measurement means to measure different pixel data of the output signal of the solid-state imaging device in the case of outputting the output signal for the first time and the output signal of the solid-state imaging device for the second time;
A test apparatus comprising: a pass / fail determination unit that determines pass / fail of the solid-state imaging device based on the pixel data acquired by the measuring unit. A signal reading device for reading an output signal of a solid-state imaging device,
A plurality of measuring means each for measuring pixel data included in the output signal of the solid-state imaging device;
And a signal processing circuit that averages and acquires pixel data measured by the plurality of measuring means. A test apparatus for testing a solid-state imaging device,
A plurality of measuring means each for measuring pixel data included in the output signal of the solid-state imaging device;
A signal processing circuit that averages and acquires pixel data measured by the plurality of measuring means;
A test apparatus including a pass / fail judgment unit that judges pass / fail of the solid-state imaging device based on pixel data obtained by averaging the signal processing circuit.

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