KR20070008257A - Interconnection metal, method for fabricating the same, thin film transistor plate and method for fabricating the same - Google Patents

Abstract

A wire, a method for forming the wire, a thin film transistor substrate, and a method for manufacturing the thin film transistor substrate are provided to improve the adhesive force between the wire and a lower layer, thereby preventing the exfoliation of the wire, by disposing a solid solution layer below a low resistance metal layer in the wire. A wire is composed of an adhesive metal layer(2), a solid solution layer(4), a low resistance metal layer(6), and a transparent conductive layer(8) sequentially formed on a substrate(1). The adhesive metal layer is formed of a material, which has an excellent adhesive property and reduces the contact resistance. The solid solution layer is formed by heating a low resistance metal material and a predetermined metal material, which forms a solid solution together with the low resistance metal material.

Description

Wiring, a method of forming the same, and a thin film transistor substrate and a method of manufacturing the same {Interconnection metal, method for fabricating the same, thin film transistor plate and method for fabricating the same}

1 is a cross-sectional view of a wiring according to an embodiment of the present invention.

2 is a process flowchart of a wiring forming method according to an embodiment of the present invention.

4 and 5 are cross-sectional views illustrating the process steps of the wire forming method according to the exemplary embodiment of the present invention.

5A is a layout diagram of a thin film transistor substrate manufactured by a manufacturing method according to an embodiment of the present invention.

FIG. 5B is a cross-sectional view taken along the line BB ′ of FIG. 5A.

6A through 9A are layout views sequentially illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment.

6B to 9B are cross-sectional views taken along the line BB ′ of FIGS. 6A to 9A, respectively.

<Description of the symbols for the main parts of the drawings>

2: adhesive metal layer 4: solid solution layer

6: low resistance metal layer 8: transparent conductive layer

10: substrate 22: gate line

24: gate pad 26: gate electrode

27: sustain electrode 28: sustain electrode line

30: gate insulating film 40: semiconductor layer

55, 56: ohmic contact layer 62: data line

65 source electrode 66 drain electrode

67: drain electrode extension 68: data pad

70: protective film 82: pixel electrode

The present invention relates to a wiring, a method for forming the same, a thin film transistor substrate, and a method for manufacturing the same. More particularly, the wiring with improved adhesion, excellent conductivity, a method for forming the same, a thin film transistor substrate formed using the same, and a method for manufacturing the same It is about.

Liquid crystal display (LCD) is one of the most widely used flat panel displays. It consists of two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween. A display device adjusts the amount of light transmitted by rearranging liquid crystal molecules of a liquid crystal layer by applying a voltage.

Among the liquid crystal display devices, a field generating electrode is provided on each of two substrates. Among them, a plurality of pixel electrodes are arranged in a matrix form on one substrate, and one common electrode covers the entire surface of the substrate on another substrate. In such a liquid crystal display, an image is displayed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal element for switching a voltage applied to a pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a voltage to be applied to the pixel electrode. A data line to transfer is formed on the substrate.

On the other hand, as the display area of the liquid crystal display device becomes larger and larger, the gate line and the data line connected to the thin film transistor also become longer, thereby increasing the resistance of the wiring. Therefore, in order to solve such problems as signal delay caused by an increase in resistance, it is necessary to form the gate line and the data line with a material having the lowest specific resistance.

The lowest specific resistance among the wiring materials is silver (Ag). Silver (Ag) is known to have a specific resistance of about 1.59 µΩcm. Therefore, in the actual process, problems such as signal delay and the like can be solved by using the gate line and the data line made of silver (Ag). However, silver (Ag) is extremely poor in adhesion to a substrate such as glass or a lower substrate such as a semiconductor substrate made of intrinsic amorphous silicon, doped amorphous silicon, or the like, so that deposition is not easy, lifting or peeling is easily induced.

The technical problem to be achieved by the present invention is to provide a wiring and a method of forming the good adhesion and conductivity.

Another object of the present invention is to provide a thin film transistor substrate and a method for manufacturing the same, including a wiring having good adhesion and conductivity.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A wiring according to an embodiment of the present invention for achieving the technical problem includes a low resistance metal layer and a transparent conductive layer formed sequentially on a substrate, which is included in the low resistance metal layer between the substrate and the low resistance metal layer And a solid solution layer composed of metal.

In accordance with another aspect of the present invention, there is provided a method of forming a wire, sequentially laminating a metal layer, a low resistance metal layer, and a transparent conductive layer forming a low resistance metal and a solid solution on a substrate. Heat-treating to form a solid solution layer comprising the low resistance metal, the low resistance metal, and a metal forming a solid solution between the substrate and the low resistance metal layer, and patterning the resultant heat treatment into a desired shape. Include.

In accordance with another aspect of the present invention, a thin film transistor substrate includes a substrate, a gate wiring formed on the substrate, and including a gate electrode, a gate insulating film and a semiconductor layer formed on the gate wiring. And a pixel electrode formed on the semiconductor layer and including a source / drain electrode, and a pixel electrode formed in an area defined by the gate line and the data line intersecting and electrically connected to the drain electrode. The gate wiring and / or data wiring is composed of the wiring as described above.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate, the method including: forming a gate wiring including a gate electrode on a substrate; Forming a data line including a source / drain electrode on the semiconductor layer; and electrically connecting a drain electrode included in the data line to a region defined by the gate line crossing the data line. Forming a pixel electrode, wherein the gate wiring and / or data wiring is formed by the wiring forming method as described above.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only the embodiments are to make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

First, a wiring and a method of forming the same according to an embodiment of the present invention will be described. 1 is a cross-sectional view of a wiring according to an embodiment of the present invention, FIG. 2 is a process flowchart of a wiring forming method according to an embodiment of the present invention, and FIGS. 3 and 4 are one embodiment of the present invention. The process step by step of the wiring forming method according to the.

Referring to FIG. 1, a wiring according to an embodiment of the present invention may include an adhesive metal layer 2, a low resistance metal, and a solid solution thereof made of a metal material having excellent adhesion on a substrate 1 and lowering contact resistance. The solid solution layer 4 formed by heat-treating the metal to be formed, the low-resistance metal layer 6 having excellent electrical conductivity, and the low-resistance metal layer 6 by heat treatment are prevented from agglomeration, and the control of the etching rate is facilitated. And a transparent conductive layer 8 for improving adhesiveness with an upper film such as an insulating film. In the case of the adhesive metal layer 2, if the contact resistance with the lower layer is not a problem, it can be omitted.

Subsequently, a wiring forming method according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4.

First, referring to FIG. 2, an adhesive metal layer, a metal layer forming a low resistance metal and a solid solution, a low resistance metal layer, and a transparent conductive layer are sequentially stacked on the substrate (FIG. S1).

Referring to FIG. 3, the adhesive metal layer 2 is formed on the substrate 1, for example, a semiconductor substrate made of glass, intrinsic amorphous silicon, doped amorphous silicon, or the like. The adhesive metal layer 2 may be formed of a refractory metal, for example, molybdenum (Mo), which is a metal material having excellent adhesion to the substrate 1 and lowering contact resistance. At this time, the thickness of the adhesive metal layer 2 may be, for example, 300 to 500 kPa.

The adhesive metal layer 2 may be omitted if the contact resistance with the lower layer is not a problem.

Next, on the adhesive metal layer 2, the metal layer 3 which forms a low resistance metal and a solid solution is formed. Low-resistance metals, such as silver (Ag), have excellent electrical conductivity, but are very poor in adhesion to the substrate, so that when wiring is formed only with silver (Ag), the wiring is lifted in a subsequent process such as a cleaning process. Or peeling may occur.

Therefore, when the wiring is formed using a low resistance metal such as silver, it is necessary to improve the adhesiveness with the substrate. The low resistance metal and the solid solution may be formed under the low resistance metal layer 6 while having excellent adhesion with the lower layer. The adhesion of the low resistance metal layer 6 can be improved by interposing the metal layer 3 to be formed.

Examples of the low resistance metal and the metal forming the solid solution as described above include, for example, an aluminum (Al) metal having a solid solubility of about 15 atomic% at a temperature of 300 ° C. At this time, the thickness of the metal layer forming the low-resistance metal and the solid solution is not particularly limited. However, when the thickness is too thick, the amount of diffusion into the low-resistance metal layer increases and the resistance value of the wiring increases. have.

Next, the low resistance metal layer 6 is formed. Silver is mentioned as a low resistance metal which forms the low resistance metal layer 6, for example. At this time, the thickness of the low resistance metal layer 6 may be about 1000 to 3000 kPa, for example, 1500 to 2000 kPa.

Next, the transparent conductive layer 8 is formed on the low resistance metal layer 6. The transparent conductive layer 8 improves the adhesion of the low resistance metal layer 6 to the upper film, prevents the low resistance metal, for example, silver (Ag) from diffusing into the upper film, and aggregates the low resistance metal. Serves to prevent. In addition, by forming the transparent conductive layer 8 on the low resistance metal layer 6, the etching rate of the low resistance metal layer 6, for example, silver (Ag), having an extremely fast etching rate can be lowered. . The transparent conductive layer 8 may be formed using, for example, indium tin oxide (ITO) or indium zinc oxide (IZO). In this case, the thickness of the transparent conductive layer 8 may be, for example, about 50 to 300 kPa.

Subsequently, heat treatment is performed on the lamination resultant (S2 in FIG. 2).

Referring to FIG. 4, an adhesive metal layer 2, a metal layer 3 forming a low resistance metal and a solid solution, a low resistance metal layer 6, and a transparent conductive layer 8 are sequentially stacked on the substrate 1. The lamination resultant is heat-treated, and the solid solution layer 4 is completed by forming a solid solution by mutual diffusion between the low resistance metal layer 6 and the metal included in the metal layer 3 forming the solid solution. At this time, the heat treatment temperature should be carried out at a temperature lower than the temperature in the lamination step. When the heat treatment is performed at a high temperature, the diffusion between the metals occurs well, but, for example, when the substrate is formed of glass or the like, warpage of the glass substrate may occur, and the low-resistance metal layer 6, for example, silver (Ag) Agglomeration of the metal layer formed by) may occur, and such agglomeration may cause disconnection of the wiring. Therefore, the heat treatment temperature may be performed at a temperature lower than the lamination temperature of each conductor layer, for example, 300 ° C. or lower. The solid solution layer 4 is formed under the low-resistance metal layer 6 to improve adhesiveness with the lower film, and does not cause lifting or peeling off by a subsequent process.

Subsequently, the heat treatment resultant is patterned into a target shape (S3 in FIG. 2).

Referring to FIG. 1, a photoresist pattern is formed on a heat treatment resultant in which the solid solution layer 4 is formed by heat treatment as described above, and the wiring pattern is completed by patterning the heat treatment resultant into a desired formation using this as a visual mask.

The wiring and the method of forming the wiring as described above can be applied to the thin film transistor substrate and the manufacturing method thereof.

Hereinafter, a thin film transistor substrate and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the accompanying drawings.

First, a structure of a thin film transistor substrate manufactured by a manufacturing method according to an exemplary embodiment of the present invention will be described with reference to FIGS. 5A and 5B. FIG. 5A is a layout view of a thin film transistor substrate manufactured by a manufacturing method according to an embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along the line BB ′ of FIG. 5A.

A plurality of gate wires for transmitting a gate signal are formed on the substrate 10. The gate wires 22, 24, 26, 27, and 28 are connected to the ends of the gate line 22 and the gate line 22 extending in the horizontal direction, and receive gate signals from the outside to the gate line 22. The storage electrode 27 and the storage electrode line 28 which are connected to the gate pad 24 and the gate line 22, and formed in parallel with the gate electrode 26 and the gate line 22 of the thin film transistor formed in the form of protrusions. It includes. The storage electrode line 28 extends in the horizontal direction across the pixel region and is connected to the storage electrode 27 having a width wider than that of the storage electrode line 28. The storage electrode 27 overlaps with the drain electrode extension 67 connected to the pixel electrode 82, which will be described later, to form a storage capacitor that improves the charge storage capability of the pixel. Such shapes and arrangements of the storage electrode 27 and the storage electrode line 28 may be modified in various forms, and may not be formed when the storage capacitance generated by the overlap between the pixel electrode 82 and the gate line 22 is sufficient. It may not.

The gate wirings 22, 24, 26, and 27 are formed of a refractory metal such as molybdenum (Mo), such as molybdenum (Mo), which is excellent in adhesiveness with the lower layer and can lower the contact resistance. A low-resistance metal that improves adhesion to the lower layer of the resistive metal layer and a metal forming a solid solution, for example, an aluminum (Al) -based metal and a low-resistance metal, for example, a solid solution composed of silver (Ag) Prevents agglomeration of the layers 222, 242, 262, and 272, the low resistance metal layers 223, 243, 263, and 273 formed of a low resistance metal such as silver (Ag) and the low resistance metal, and controls the etching rate And a transparent conductive layer 224, 244, 264, or 274 formed of indium tin oxide or indium zinc oxide to prevent diffusion into the upper layer. In the case of the gate wiring, since the contact resistance with the substrate is not a big problem, the adhesive metal layers 221, 241, 261, and 271 may be omitted.

Although not shown directly in the drawing, the storage electrode lines 28 also have the same structure as the other gate wirings 22, 24, 26, 27. The sustain electrode line 28 is also included in the gate wiring of the structure demonstrated below.

A gate insulating film 30 made of silicon nitride (SiNx) or the like is formed on the substrate 10 and the gate wirings 22, 24, 26, 27, and 28.

A semiconductor layer 40 made of a semiconductor such as hydrogenated amorphous silicon or polycrystalline silicon is formed in an island shape on the gate insulating layer 30 of the gate electrode 26, and silicide or n-type impurities are formed on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as heavily doped n ⁺ hydrogenated amorphous silicon are formed, respectively.

Data lines 62, 65, 66, 67, and 68 are formed on the ohmic contacts 55 and 56 and the gate insulating layer 30. The data lines 62, 65, 66, 67, and 68 are formed in the vertical direction and cross the gate line 22 to define the pixel and the branch of the data line 62 and the data line 62 to define a pixel. Is connected to one end of the source electrode 65 and the data line 62 extending to an upper portion of the circuit board, and is separated from the data pad 68 and the source electrode 65 to which an image signal from the outside is applied, and the gate electrode 26. Or a wide area extending from the drain electrode 66 and the drain electrode 66 formed on the ohmic contact layer 56 opposite to the source electrode 65 with respect to the channel portion of the thin film transistor and overlapping the storage electrode 27. A drain electrode extension 67 of the area.

The data lines 62, 65, 66, 67, and 68 may be formed of adhesive metal layers 621, 651, 661, 671, and 681, solid solution layers 622, 652, 662, 672, and 682, and low resistance metal layers 623 and 653. 663, 673, 683 and transparent conductive layers 623, 654, 664, 674, 684. For the data wires 62, 65, 66, 67, and 68, the adhesive metal layers 621, 651, 661, 671, and 681 are not omitted in order to reduce the contact resistance with the ohmic contacts 55 and 56. Since the structure and function are the same as those in the gate wirings 22, 24, 26, 27, and 28, the overlapping description is omitted.

The source electrode 65 overlaps at least a portion of the semiconductor layer 40, and the drain electrode 66 faces the source electrode 65 around the gate electrode 26 and at least partially overlaps the semiconductor layer 40. do. Here, the ohmic contact layers 55 and 56 exist between the semiconductor layer 40 below and the source electrode 65 and the drain electrode 66 above and serve to lower the contact resistance.

The drain electrode extension 67 is formed to overlap the storage electrode 27, and a storage capacitor is formed with the storage electrode 27 and the gate insulating layer 30 interposed therebetween. When the sustain electrode 27 is not formed, the drain electrode extension 27 is also not formed.

The passivation layer 70 is formed on the data wires 62, 65, 66, 67, and 68 and the semiconductor layer 40 not covered by the data lines 62. The protective film 70 is formed of, for example, a-Si: C: O or a-Si: It may be formed of a low dielectric constant insulating material such as O: F, or silicon nitride (SiNx), which is an inorganic material. In addition, when the protective film 70 is formed of an organic material, the organic material of the protective film 70 is prevented from coming into contact with the exposed portion of the semiconductor layer 40 between the source electrode 65 and the drain electrode 66. For this purpose, an insulating film (not shown) made of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) may be further formed below the organic film.

Contact holes 77 and 78 exposing the drain electrode extension 67 and the data line pad 68 are formed in the passivation layer 70, and the gate line pads 24 are formed in the passivation layer 70 and the gate insulating layer 30. The contact hole 74 exposing) is formed. The pixel electrode 82, which is electrically connected to the drain electrode 66 and positioned in the pixel, is formed on the passivation layer 70 through the contact hole 77. The pixel electrode 82 to which the data voltage is applied generates an electric field together with the common electrode of the upper panel to determine the arrangement of liquid crystal molecules of the liquid crystal layer between the pixel electrode 82 and the common electrode.

In addition, an auxiliary gate pad 84 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 are formed on the passivation layer 70 through the contact holes 74 and 78, respectively. The pixel electrode 82, the auxiliary gates, and the data pads 86 and 88 are made of a transparent conductive material, for example, indium tin oxide or indium zinc oxide.

Hereinafter, a method of manufacturing a thin film transistor substrate using a wiring forming method according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 5A and 5B and FIGS. 6A to 9B.

First, as shown in FIGS. 6A and 6B, on the substrate 10, adhesive metal layers 221, 241, 261, and 271 made of a refractory metal such as molybdenum (Mo), for example, aluminum (Al). A metal layer (not shown) forming a solid solution and a low resistance metal made of a system metal, for example, a low resistance metal layer 223, 243, 263, 273 made of silver (Ag) and, for example, indium tin oxide or indium zinc oxide. The transparent conductive layers 224, 244, 264, and 274 made of the same are sequentially stacked, and then heat-treated at a temperature of 300 ° C. or lower. A solid solution layer 222, 242, 262, 272 made of a solid solution of aluminum (Al) metal and silver (Ag) under the low resistance metal layer by mutual diffusion of aluminum (Al) metal and silver (Ag) by heat treatment. And then pattern the gate wirings 22, 24, 26, 27 including the gate lines 22, the gate electrodes 26, the gate pads 24, the storage electrodes 27, and the storage electrode lines 28. , 28). Since the method for forming the gate wirings 22, 24, 26, 27, and 28 is the same as the wiring forming method according to the exemplary embodiment of the present disclosure, overlapping descriptions thereof will be omitted.

7A and 7B, the gate insulating film 30 made of silicon nitride, the intrinsic amorphous silicon layer, and the doped amorphous silicon layer are each 1,500 kV to 5,000 kV and 500 kV, respectively, using chemical vapor deposition. And the island-like semiconductor layer 40 on the gate insulating film 30 on the gate electrode 24 by photolithography by successively depositing a thickness of about 2,000 to 2,000 kV, 300 to 600 mW. The ohmic contacts 55 and 56 are formed.

Next, as shown in FIGS. 8A and 8B, an adhesive made of a refractory metal such as molybdenum (Mo), for example, is formed on the gate insulating layer 30, the exposed semiconductor layer 40, and the ohmic contact layers 55 and 56. Metal layers 621, 651, 661, 671, 681, for example, a low resistance metal made of aluminum (Al) -based metal and a metal layer (not shown) forming a solid solution, for example a low resistance metal layer made of silver (Ag) (623, 653, 663, 673, 683) and transparent conductive layers 624, 654, 664, 674, 684 made of, for example, indium tin oxide or indium zinc oxide, etc., sequentially stacked, and then Heat treatment to temperature A solid solution layer 622, 652, 662, 672, which is made of a solid solution of aluminum (Al) -based metal and silver (Ag) under the low-resistance metal layer by interdiffusion of aluminum (Al) -based metal and silver (Ag) by heat treatment 682 is formed, and then patterned to form a data line 62 crossing the gate line 22, a source electrode 65 connected to the data line 62, and extending up to the upper portion of the gate electrode 26. A data pad 68 connected to one end of the 62, a drain electrode 66 and a drain electrode 66 which are separated from the source electrode 65 and face the source electrode 65 with respect to the gate electrode 26. ), Data lines 62, 65, 66, 67, and 68 are formed to include a drain electrode extension 67 having a large area that extends from and overlaps the sustain electrode 27. For the data wires 62, 65, 66, 67, and 68, the adhesive metal layers 621, 651, 661, 671, and 681 are not omitted in order to reduce the contact resistance with the ohmic contacts 55 and 56. Is the same as the method of forming the gate wirings 22, 24, 26, 27, and 28, and thus redundant description thereof will be omitted.

Next, the doped amorphous silicon layer not covered by the data lines 62, 65, 66, 67, and 68 is etched to move the data lines 62, 65, 66, 67, and 68 to both sides of the gate electrode 26. While separating, the semiconductor layer 40 between the two ohmic contact layers 55 and 56 is exposed. At this time, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Subsequently, as shown in FIGS. 9A and 9B, organic materials having excellent planarization characteristics and photosensitivity, a-Si: C: O, a-Si formed by Plasma Enhanced Chemical Vapor Deposition (PECVD) A low dielectric constant insulating material, such as: O: F, or silicon nitride (SiNx), which is an inorganic material, is formed in a single layer or in a plurality of layers to form a passivation layer 70.

Subsequently, the passivation layer 70 is patterned together with the gate insulating layer 30 by a photolithography process, thereby contact holes 74, 77, and 78 exposing the gate pad 24, the drain electrode extension 67, and the data pad 68. ). In this case, in the case of the organic film having photosensitivity, the contact hole may be formed only by a photolithography process, and the gate hole 30 and the passivation layer 70 may be formed under etching conditions having substantially the same etching ratio.

Finally, as shown in FIGS. 5A and 5B, a transparent conductive material, for example, indium tin oxide or indium zinc oxide, is deposited and photo-etched to be connected to the drain electrode 66 through the contact hole 77. An auxiliary gate pad 84 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 are formed through the pixel electrode 82 and the contact holes 74 and 78, respectively.

In this embodiment, the gate wiring and the data wiring have been described as an example in which the adhesive metal layer, the solid solution layer, the low resistance metal layer, and the transparent conductive layer have been described. However, when only one of the gate wiring and the data wiring is formed in the wiring structure as described above. The same can be applied to.

In addition, in the present embodiment, a method of manufacturing a thin film transistor substrate in which a semiconductor layer and a data line are formed by a photolithography process using different masks has been described. However, the semiconductor layer and the data line are formed by a photolithography process using a single photoresist pattern. The same applies to the method of manufacturing the thin film transistor substrate.

The method of manufacturing a thin film transistor substrate according to the present invention may be easily applied to an AOC (Array On Color filter) structure in which a thin film transistor array is formed on a color filter in addition to the above-described embodiments.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, the gate wiring or the data wiring of the thin film transistor substrate formed using the wiring forming method according to the exemplary embodiment of the present invention is formed under the low resistance metal layer through a solid solution layer to form silver, which is a low resistance conductive material. Even in the case of forming the wirings, the adhesion between the gate wirings or the data wirings and the lower layer is improved to prevent the lifting or peeling of the wirings, thereby improving the signal characteristics of the liquid crystal display and improving the image quality.

Claims (19)

And a low-resistance metal layer and a transparent conductive layer sequentially formed on a substrate, and comprising a solid solution layer comprising a metal contained in the low-resistance metal layer as a component between the substrate and the low-resistance metal layer. The method of claim 1, And the low resistance metal comprises silver. The method of claim 1, And the solid solution layer comprises silver and aluminum. The method of claim 1, And an adhesive metal layer formed between the substrate and the solid solution layer. The method of claim 4, wherein And the adhesive metal layer includes a refractory metal. The method of claim 5, Wherein the refractory metal comprises molybdenum. The method of claim 1, And the transparent conductive layer includes indium tin oxide or indium zinc oxide. Sequentially stacking a metal layer, a low resistance metal layer, and a transparent conductive layer forming a low resistance metal and a solid solution on the substrate; Heat-treating the lamination result to form a solid solution layer comprising a metal forming the low resistance metal, the low resistance metal, and a solid solution between the substrate and the low resistance metal layer; And And patterning the heat treatment resultant into a target shape. The method of claim 8, And the low resistance metal comprises silver. The method of claim 8, And a metal layer forming the low resistance metal and the solid solution includes aluminum. The method of claim 8, And the solid solution layer comprises silver and aluminum. The method of claim 8, And forming an adhesive metal layer on the substrate before forming the metal layer forming the low resistance metal layer and the solid solution. The method of claim 12, And the adhesive metal layer includes a refractory metal. The method of claim 13, And the refractory metal comprises molybdenum. The method of claim 8, And the transparent conductive layer comprises indium tin oxide or indium zinc oxide. The method of claim 8, And the temperature of the heat treatment step is lower than the temperature of the stacking step. The method of claim 16, The heat treatment is a wiring forming method wherein the temperature of the step is performed at 300 ℃ or less. Board; A gate wiring formed on the substrate and including a gate electrode; A gate insulating film and a semiconductor layer formed on the gate wiring; A data line formed on the semiconductor layer and including a source / drain electrode; And And a pixel electrode formed in an area defined by the gate wiring crossing the data wiring, and electrically connected to the drain electrode, wherein the gate wiring and / or the data wiring are any one of claims 1 to 7. A thin film transistor substrate comprising the wiring according to claim. Forming a gate wiring including a gate electrode on the substrate; Forming a gate insulating film and a semiconductor layer on the gate wiring; Forming a data line including a source / drain electrode on the semiconductor layer; And Forming a pixel electrode electrically connected to a drain electrode included in the data line in a region defined by the intersection of the gate line and the data line; A manufacturing method of a thin film transistor substrate formed by the wiring forming method according to any one of claims 17.

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