KR20070002620A - Liquid crystal display device - Google Patents

Abstract

An LCD is provided to prevent a flicker phenomenon by minimizing a feed throw voltage. A liquid crystal panel(202) includes thin film transistors formed at intersections of a plurality of gate lines(GL0~GLn) and a plurality of data lines(DL1~DLm). A first gate driver(204a) is provided at the other side of the liquid crystal panel, and supplies a first or second scan signal to the liquid crystal panel. A first switch(212a) selectively outputs one of the first and second scan signals for supply to the first gate driver. A second switch(212b) selectively outputs one of the first and second scan signals for supply to the second gate driver. A timing controller(208) switching-controls one of the first and second switches. A flicker detector(216) supplies information on a flicker generation position detected from the liquid crystal panel to the timing controller.

Description

Liquid crystal display device

1 is a view showing a conventional liquid crystal display device.

FIG. 2 is a waveform diagram illustrating a voltage applied to the liquid crystal display of FIG. 1.

3 is a view showing a liquid crystal display device according to an embodiment of the present invention.

4 illustrates a liquid crystal display according to another exemplary embodiment of the present invention.

5 is a view showing a liquid crystal display device according to another embodiment of the present invention.

<Brief description of the main parts of the drawing>

102, 202: Liquid Crystal Panel 104: Gate Driver

204a: first gate driver 204b: second gate driver

106, 206: Data driver 108, 208: Timing controller

110, 210: gate modulation section 212a: first switching section;

212b: second switching unit 214: power supply unit

216: flicker detector

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device that can prevent the flicker phenomenon.

The LCD displays an image by adjusting the light transmittance of the liquid crystal cells according to the image signal. Among the liquid crystal display devices, an active matrix type in which switching elements are provided for each liquid crystal cell is suitable for displaying a moving image. In the active matrix liquid crystal display device, a thin film transistor (TFT) is mainly used as a switching element. Such a liquid crystal display device can be miniaturized compared to a CRT, and is widely used for personal computers (PCs) and notebook computers, as well as office automation equipment such as copy machines, mobile phones and pagers.

1 is a view showing a conventional liquid crystal display device.

As shown in FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 2 in which liquid crystal cells are arranged in a matrix, and gates for driving a plurality of gate lines GL0 to GLn of the liquid crystal panel 2. A driver 4, a data driver 6 for driving the data lines DL1 to DLm of the liquid crystal panel 2, and a timing controller for controlling the gate driver 4 and the data driver 6 ( 8).

The liquid crystal display is well known and a detailed description of the liquid crystal display is omitted.

The data driver 6 supplies a data voltage to the plurality of data lines DL1 to DLm according to a data control signal generated from the timing controller 8. On the other hand, if the data voltage Vd in the same direction is continuously applied to the pixel electrode, the liquid crystal cell Clc is deteriorated.

To prevent this, the data voltage Vd supplied from the data lines DL1 to DLm is repeatedly driven to be positive (+) and negative (-).

The gate high voltage VGH and the gate low voltage VGL are supplied to the gate lines GL0 to GLn of the liquid crystal display device driven in this manner. Here, the gate high voltage VGH is supplied during the horizontal period (1H) corresponding to the gate lines GL0 to GLn, and the gate low voltage VGL is applied during the remaining period.

In this case, the gate high voltage VGH turns on the thin film transistor TFT on the liquid crystal panel 2 and during the period when the thin film transistor TFT is turned on. The data voltage supplied from the data driver 6 is charged to the pixel electrode.

As the gate high voltage VGH supplied to the gate lines GL0 to GLn is changed to the gate low voltage VGL, the thin film transistor TFT is turned into a turn-off state and the pixel electrode is instantaneously. As shown in FIG. 2, the data voltage Vd charged in the voltage drop is generated as much as the feed-through voltage (Vp) by the parasitic capacitance Cgs of the thin film transistor TFT.

An image displayed on the liquid crystal panel 2 may cause flicker and afterimages due to the feed throw voltage Vp, resulting in a problem of deterioration in image quality.

An object of the present invention is to provide a liquid crystal display device which can improve the image quality by preventing the flicker phenomenon.

According to an aspect of the present invention, there is provided a liquid crystal display device including a liquid crystal panel including a thin film transistor formed at an intersection of a plurality of gate lines and a data line, and a first or second scan signal provided on the other side of the liquid crystal panel. A first gate driver for supplying a light to the liquid crystal panel, a first switch for selectively outputting one of the first or second scan signals for supplying the first gate driver, and a second gate driver A second switch for selectively outputting one of the first and second scan signals, a timing controller for switching and controlling one of the first and second switches, and information on a flicker generation position detected from the liquid crystal panel. And a flicker detector for supplying the timing controller.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention.

3 illustrates a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the liquid crystal display device includes a liquid crystal panel 102 for displaying a predetermined image, a gate driver 104 and a data driver 106 for driving the liquid crystal panel 102, and the gate. A timing controller 108 for controlling the driver 104 and the data driver 106 and a gate modulation unit 110 for generating the second gate high voltage VGH_2.

The liquid crystal panel 102 includes a plurality of gate lines GL0 to GLn and data lines DL1 to DLm defining a pixel area, and the gate lines GL0 to GLn and the data lines DL1 to DLm. Thin film transistors (TFTs) are formed at the intersections.

The thin film transistor TFT is turned on when first and second gate high voltages VGH_1 and VGH_2 are supplied from the gate lines GL0 to GLn. The thin film transistor TFT is continuously turned on when a voltage above the threshold voltage Vth is supplied.

The first gate high voltage VGH_1 is generated by a power supply (not shown) and is supplied to the gate driver 104 for one half horizontal section 1 / 2H, which is half of one horizontal section 1H, for example. The second gate high voltage VGH_2 is generated by the gate modulation unit 110 and supplied to the gate driver 104 during the remaining 1/2 horizontal section 1 / 2H of the first horizontal section 1H.

The thin film transistor TFT is connected to the gate lines GL0 to GLn line by line. The first and second gate high voltages VGH_1 and VGH_2 and the gate low voltage VGL are supplied to the thin film transistor TFT through the gate lines GL0 to GLn.

The gate modulation unit 110 receives the first gate high voltage VGH_1 from the power supply unit (not shown). The gate modulation unit 110 divides the first gate high voltage VGH_1 into predetermined resistors to generate a second gate high voltage VGH_2 of about 10V.

The thin film transistor TFT is turned on when a voltage greater than or equal to the threshold voltage Vth is turned on, and thus is turned on with the second gate high voltage VGH_2.

The reason why the first and second gate high voltages VGH_1 and VGH_2 are supplied to the gate driver 104 in the liquid crystal display device driven as described above is to reduce the above-mentioned feed-throw voltage? Vp.

In the conventional liquid crystal display, the gate high voltage VGH supplied to the gate line is changed to the gate low voltage VGL, and thus the thin film transistor TFT is turned into a turn-off state. At this moment, the voltage drop charged in the pixel electrode is generated by the feed-through voltage (Vp) by the parasitic capacitance Cgs of the thin film transistor TFT.

That is, the feed-throw voltage Vp is generated due to the parasitic capacitance (for example, Cgs, etc.) affected by the gate high voltage VGH being changed to the gate low voltage VGL. Due to the feed-through voltage (Vp), flicker and residual images are generated in the image displayed on the liquid crystal panel, resulting in a problem of deterioration in image quality.

Therefore, there are various methods for reducing the feed-through voltage (Vp). In the present invention, while maintaining the turn-on state of the thin film transistor TFT, the difference value between the gate high voltage VGH and the gate low voltage VGL is reduced to reduce the feed-through voltage Vp. Decreases.

The feed throw voltage (Vp) is expressed by Equation 1 below.

는 에 피드 스로우 전압(ㅿVp)이고

는 박막트랜지스터(TFT)의 게이트 전극(G)과 소스전극(C) 사이의 캐패시터이다. 또한,

는 스토리지 캐패시터이고,

는 액정셀의 캐패시터이며,

는 게이트 하이 전압이고,

은 게이트 로우 전압을 나타낸다.here,

Is the feed-through voltage (ㅿ Vp)

Denotes a capacitor between the gate electrode G and the source electrode C of the thin film transistor TFT. Also,

Is the storage capacitor,

Is the capacitor of the liquid crystal cell,

Is the gate high voltage,

Denotes the gate low voltage.

In order to reduce the feed-throw voltage Vp in Equation 1, the gate capacitor Vg, which is the difference between the parasitic capacitor Cgs, the gate high voltage VGH, and the gate low voltage VGL, is reduced and the storage capacitor Vp is reduced. Cst) should be increased.

When the gate high voltage VGH is reduced, the variation amount Vg of the gate voltage can be reduced, and as a result, the feed through voltage Vp can be reduced.

Accordingly, the present invention is to reduce the gate high voltage (VGH) in order to reduce the feed-through voltage (Vp).

The gate modulation unit 110 generates the second gate high voltage VGH_2 that is about half lower than the first gate high voltage VGH_1 and according to the control signal generated by the timing controller 108, the gate driver 104. To supply.

The gate driver 104 sequentially supplies the second gate high voltage VGH_2 to the gate lines GL0 to GLn. As a result, the second gate high voltage VGH_2 is supplied to the gate lines GL0 to GLn to turn on the first gate high voltage VGH_1 to turn on the thin film transistor TFT. Keep it.

When the gate low voltage VGL is supplied to the thin film transistor TFT to which the second gate high voltage VGH_2 is supplied, the feed throw voltage VVp is generated. In this case, the feed throw voltage VVp is generated. ) Is reduced than in the conventional case.

Due to the second gate high voltage VGH_2, the feed-throw voltage? Vp is reduced compared to the conventional liquid crystal display, thereby overcoming flicker and residual images displayed on the liquid crystal panel 102.

Meanwhile, as the liquid crystal display becomes larger, the liquid crystal panel 102 also increases in size and number of pixels. In the case of the enlarged liquid crystal panel 102, as the capacitance characteristics are changed for each pixel position, the flicker and the residual image are easily compensated even when the second gate high voltage VGH_2 is supplied to the gate lines GL0 to GLn. Will not be made.

4 is a diagram illustrating a liquid crystal display according to another exemplary embodiment of the present invention.

As shown in FIG. 4, the liquid crystal display includes a liquid crystal panel 202 for displaying a predetermined image, a flicker detecting unit 216 for detecting flicker generated in the liquid crystal panel 202 during a first frame, First and second gate drivers 204a and 204b and data driver 206 for driving the liquid crystal panel 202, a timing controller 208 for generating a predetermined control signal, and a first gate high voltage VGH_1. Power supply unit 214 for generating predetermined voltages, the gate modulation unit 210 for generating second gate high voltage VGH_2, and the control signal generated from the timing controller 208. First and second switching units 212a and 212b supplying second gate high voltages VGH_1 and VGH_2 to the first and second gate drivers 204a and 204b.

The same description as described in the embodiment of the present invention will be omitted.

The first and second gate drivers 204a and 204b are provided as the liquid crystal display becomes larger.

The flicker detector 216 detects flicker generated on the liquid crystal panel 202 during the first frame. The flicker detector 216 detects flicker when a change occurs in a data voltage value charged in a pixel electrode (not shown) connected to the thin film transistor TFT of the liquid crystal panel 202.

When the flicker detector 216 detects flicker on the right side of the liquid crystal panel 202 during the first frame, the flicker detector 216 supplies a high control signal to the timing controller 208.

In addition, when the flicker detector 216 detects flicker on the left side of the liquid crystal panel 202 during the first frame, the flicker detector 216 supplies a low control signal to the timing controller 208.

The timing controller 208 supplied with the high control signal supplies a predetermined control signal to the second switching unit 212b. The timing controller 208 supplied with the low control signal supplies a predetermined control signal to the first switching 212a.

When flicker occurs on the right side of the liquid crystal panel 202 during the first frame, the timing controller 208 supplies a predetermined control signal to the second switching unit 212b.

In this case, the first and second gate drivers 204a and 204b are connected to the gate lines GL0 to GLn.

The first and second switching units 212a and 212b include a first gate high voltage VGH_1 generated by the power supply unit 212 and a second gate high voltage VGH_2 generated by the gate modulation unit 210. Is supplied.

The first gate driver 204a sequentially supplies the first gate high voltage VGH_1 to the gate lines GL0 to GLn according to a control signal supplied from the timing controller 208.

The second gate driver 204b includes the second gate high voltage VGH_2 generated by the gate modulation 210 and the first gate high voltage generated by the power supply unit 214 through the second switching unit 212b. (VGH_1) is supplied.

In this case, a control signal generated from the timing controller 208 is supplied to the second switching unit 212b, and when the control signal is high, the second switching unit 212b receives the second gate high voltage. (VGH_2) is supplied to the second gate driver 204b.

When the control signal is low, the second switching unit 212b supplies the first gate high voltage VGH_1 to the second gate driver 204b.

For example, the low control signal is supplied to the second switching unit 212b during the 1/2 horizontal section 1 / 2H of the 1 horizontal section 1H and the high control signal is the 1 horizontal section. The second switching unit 212b is supplied to the second switching unit 212b during the remaining half horizontal section 1 / 2H of the section 1H.

The second gate driver 204b may include a gate line in which the first and second gate high voltages VGH_1 and VGH_2 supplied from the second switching unit 212b are arranged in the liquid crystal panel 202 according to the control signal. Supply to (GL0 to GLn).

As flicker occurs on the right side of the liquid crystal panel 202 in the first frame section, the second gate driver 204b positioned on the right side of the liquid crystal panel 202 may be connected to the second switch 212b. The first and second gate high voltages VGH_1 and VGH_2 are supplied through the first and second gate high voltages.

Accordingly, the flicker phenomenon can be reduced for the remaining frames except for the first frame.

The liquid crystal display is driven in the first frame period to detect a portion where flicker occurs, and the first and second gate high voltages VGH_1 and VGH_2 are supplied to the portion where the flicker occurs from the next frame. As the feed-through voltage ΔVp is reduced, the flicker phenomenon may be reduced.

The feed through voltage ΔVp is supplied by supplying the first and second gate high voltages VGH_1 and VGH_2 to the thin film transistor TFT positioned at the right side of the liquid crystal panel 202 where flicker occurs during the first frame. Can be reduced.

As the feed throw voltage ΔVp is reduced, flicker does not occur on the liquid crystal panel 202.

As the liquid crystal display is driven during the first frame period, flicker generated at the right side of the liquid crystal panel 202 is detected. Accordingly, the flicker phenomenon may be overcome by reducing the feed-through voltage ΔVp generated in the right portion of the liquid crystal panel 202 in the next frame.

When flicker occurs on the left side of the liquid crystal panel 202, the timing controller 208 supplies a predetermined control signal to the first switching unit 212a.

In this case, the first and second gate drivers 204a and 204b are connected to the gate lines GL0 to GLn.

The first and second switching units 212a and 212b include a first gate high voltage VGH_1 generated by the power supply unit 212 and a second gate high voltage VGH_2 generated by the gate modulation unit 210. Is supplied.

The second gate driver 204b sequentially supplies the first gate high voltage VGH_1 to the gate lines GL0 to GLn according to a control signal supplied from the timing controller 208.

The first gate driver 204a includes the second gate high voltage VGH_2 generated by the gate modulation 210 and the first gate high voltage generated by the power supply unit 214 through the first switching unit 212a. (VGH_1) is supplied.

The control signal generated from the timing controller 208 is supplied to the first switching unit 212a. When the control signal is high, the first switching unit 212a receives the second gate high voltage VGH_2. ) Is supplied to the first gate driver 204a.

When the control signal is low, the first switching unit 212a supplies the first gate high voltage VGH_1 to the first gate driver 204a.

For example, the low control signal is supplied to the first switching unit 212a during a half horizontal section 1 / 2H of one horizontal section 1H, and the high control signal is provided at the first horizontal section 1H. It is supplied to the first switching unit 212a during the remaining 1/2 horizontal section 1 / 2H of the section 1H.

The first gate driver 204a arranges the first and second gate high voltages VGH_1 and VGH_2 supplied from the first switching unit 212a in the liquid crystal panel 202 according to the control signal. Supply to (GL0 to GLn).

As flicker occurs on the left side of the liquid crystal panel 202 in the first frame section, the first gate driver 204a positioned on the left side of the liquid crystal panel 202 may be connected to the first switch 212a. The first and second gate high voltages VGH_1 and VGH_2 are supplied through the first and second gate high voltages.

Accordingly, the flicker phenomenon can be reduced for the remaining frames except for the first frame.

The liquid crystal display is driven in the first frame period to detect a portion where flicker occurs, and the first and second gate high voltages VGH_1 and VGH_2 are supplied to the portion where the flicker occurs from the next frame. As the feed-through voltage ΔVp is reduced, the flicker phenomenon may be reduced.

The feed-throw voltage ΔVp is supplied by supplying the first and second gate high voltages VGH_1 and VGH_2 to the thin film transistor TFT positioned on the left side of the liquid crystal panel 202 where flicker occurs during the first frame. Can be reduced.

As the feed throw voltage ΔVp decreases, flicker does not occur on the liquid crystal panel 202.

As the liquid crystal display is driven during the first frame period, flicker generated in the left portion of the liquid crystal panel 202 is detected. Accordingly, the flicker phenomenon may be overcome by reducing the feed-through voltage ΔVp generated in the left portion of the liquid crystal panel 202 in the next frame.

The liquid crystal display according to the present invention operates the liquid crystal display during the first frame period to detect a portion where flicker occurs and to reduce the feed-through voltage (ΔVp) of the portion where the flicker occurs in the next frame to overcome the flicker phenomenon. can do. Accordingly, the liquid crystal display according to the present invention can improve image quality.

As described above, the liquid crystal display according to the present invention reduces the feed-through voltage ΔVp by reducing the value of the gate voltage ΔVg supplied to the thin film transistor TFT positioned at the portion where flicker occurs. Therefore, the flicker phenomenon can be overcome. In addition, the liquid crystal display according to the present invention can improve image quality.

Claims (4)

A liquid crystal panel including a thin film transistor formed at an intersection of a plurality of gate lines and a data line; A first gate driver provided at the other side of the liquid crystal panel to supply a first or second scan signal to the liquid crystal panel; A first switch for selectively outputting one of the first or second scan signals for supplying to the first gate driver; A second switch for selectively outputting one of the first or second scan signals for supplying to the second gate driver; A timing controller configured to control switching of one of the first and second switches; And And a flicker detector for supplying information on a flicker generation position detected from the liquid crystal panel to the timing controller. The method of claim 1, And the second gate high voltage VGH_2 has a voltage value lower than the first gate high voltage VGH_1. The method of claim 1, The thin film transistor is turned on when the first gate high voltage is supplied, and is turned on when the second gate high voltage is supplied, and is turned off when the gate low voltage is supplied. . The method of claim 1, And the first and second scan signals are supplied to the first and second switches.

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