KR20090129558A - Liquid crystal display panel - Google Patents

Abstract

PURPOSE: A liquid crystal display panel is provided to improve flicker and afterimage generated in a display image by generating the feed through voltage which is different according to the voltage level of the data voltage inputted to each pixel in all data voltages. CONSTITUTION: A data voltage(Vdata) is applied in a data line. A first scan signal and a second scan signal are applied to a first gate line and a second gate line respectively. A control thin film transistor(TFT-C) is connected to a second gate line and a data line. A control capacitor(Ccon) is composed between the control thin film transistor and the first gate line. A switching thin film transistor(TFT-SW) is connected to the data line, and is switched and controlled by the output of the control thin film transistor. A liquid crystal capacitor and a storage capacitor are connected to the switching thin film transistor.

Description

Liquid crystal display panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel, and in particular, a flicker generated in a display image by causing the feed throw voltage ΔVp, which is different depending on the voltage level of the data voltage input to each pixel, to appear the same at all data voltages. The present invention relates to a liquid crystal display panel with improved afterimages.

Currently widely used liquid crystal display (LCD) is a plurality of liquid crystal pixels arranged in a matrix form on the substrate and to control the amount of light transmission by controlling the rotation angle of the liquid crystal in each of these liquid crystal pixels A desired gray scale is displayed on a screen by transmitting light supplied from a backlight unit to a liquid crystal panel having a thin film transistor (TFT) for supplying image data.

FIG. 1 is a diagram illustrating an equivalent circuit of one pixel of a general liquid crystal display panel, in which a gate line GL and a data line DL extending from a gate driver and a source driver are vertically and horizontally. And a thin film transistor (TFT) connected to the gate line (GL), the data line (DL), and the liquid crystal capacitor (Clc), and a storage capacitor (Cstg) connected in parallel with the liquid crystal capacitor (Clc). do.

Referring to the operation of the pixel with reference to the signal timing diagram of FIG. 2, when the scan signal, that is, the gate high voltage Vgh is supplied to the gate line GL, the thin film transistor TFT is switched to an on-switching state. The data voltage Vd supplied to the data line DL is charged in the storage capacitor Cstg, and is supplied to the liquid crystal capacitor Clc to control the rotation angle of the liquid crystal to adjust the amount of light to be transmitted. Done. In addition, the signal timing diagram further includes signal waveforms for the common voltage Vcom and the gate low voltage Vgl.

However, in the above operation, the data voltage Vd supplied to the liquid crystal capacitor Clc decreases by ΔVp when the gate high voltage Vgh falls to the gate low voltage Vgl. It is called fed through voltage. In other words, the image data supplied to the liquid crystal capacitor Clc is distorted by the feed trough voltage ΔVp at the moment when the scan signal is turned off, which is a flicker or afterimage on a screen that is soon displayed. Cause problems.

The feed crow voltage ΔVp is mainly generated by a parasitic capacitor existing inside the liquid crystal pixel including the thin film transistor TFT, and the current feed trough voltage ΔVp by the parasitic capacitor is generally represented by Equation (1) below. It is explained as follows.

Formula (1)

In Equation (1), ΔVgs represents a voltage difference between a voltage of a scan signal supplied to a thin film transistor TFT and a pixel voltage supplied to a liquid crystal pixel, and Cgs represents a gate electrode and a source of the thin film transistor TFT. A parasitic capacitor is formed between the electrodes.

It can be seen from the equation (1) that the feed trough voltage ΔVp is proportional to Cgs and ΔVgs, where the most important factor is Cgs.

The Cgs may be classified into two components, one of which is a capacitance caused by a thin film transistor (TFT) (hereinafter, Cgs_tft) and the other of which is a capacitance caused by the signal wiring (hereinafter, Cgs_line). In this case, the Cgs_line always induces a constant feed trough voltage ΔVp for data voltages of various voltage levels, whereas the Cgs_tft causes different feed trough voltages ΔVp for each data voltage.

The Cgs_tft becomes higher when the gate high voltage (Vgh) of the scan signal is greater than the data voltage (Vd) or more than the data voltage (Vd) when the scan signal applied to the thin film transistor (TFT) is turned off. The larger the voltage difference between the gate high voltage (Vgh) and the data voltage (Vd) at the moment when the scan signal applied to the thin film transistor (TFT) is turned off, the larger the feed flow is. It means that the voltage ΔVp is generated.

Therefore, the conventional liquid crystal display device which applies the same gate high voltage and gate low voltage to data voltages having various voltage levels according to gray levels is not only difficult to improve flicker and residual images, but also to each of the data voltages for all gray levels. It is not easy to design a gray scale voltage generation circuit in consideration of the feed throw voltage DELTA Vp, and it is not possible to cope with the feed trough voltage DELTA Vp which is different from each other due to the process deviation of each liquid crystal display panel.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display panel and a driving method thereof having the same feed-through voltage (ΔVp) characteristics for each pixel regardless of the data voltage. .

Another object of the present invention is to improve display defects such as flicker and afterimage by displaying the same feed-through voltage (ΔVp) characteristic for each pixel regardless of the data voltage for each pixel.

The present invention to achieve the above object,

According to the first embodiment,

 A data line to which a data voltage is applied; A first gate line and a second gate line to which the first scan signal and the second scan signal are respectively applied; A control thin film transistor connected to the second gate line and the data line; A control capacitor configured between the control thin film transistor and the first gate line; A switching thin film transistor connected to the data line and controlled to be controlled by an output of the control thin film transistor; The present invention provides a liquid crystal display panel including a liquid crystal capacitor and a storage capacitor connected to the switching thin film transistor.

In the first embodiment, the first scan signal and the second scan signal may be voltage signals having different voltage levels and signal waveforms.

In the first embodiment, the first scan signal includes a gate low voltage, a first gate high voltage, and a second gate high voltage, and the second scan signal includes a gate low voltage and a gate high voltage. It is characterized by that.

In the first embodiment, the first gate line and the second gate line are formed in parallel with each other, and the data line is formed in a direction crossing the first gate line and the second gate line.

In the first embodiment, the control thin film transistor and the switching thin film transistor are characterized in that the same channel type.

Also according to the second embodiment,

A data line to which a data voltage is applied; A first gate line and a second gate line to which the first scan signal and the second scan signal are respectively applied; A control thin film transistor configured to be switched by the second scan signal and output the first scan signal; A control capacitor configured between the control thin film transistor and the data line; A switching thin film transistor connected to the data line and controlled to be controlled by an output of the control thin film transistor; The present invention provides a liquid crystal display panel including a liquid crystal capacitor and a storage capacitor connected to the switching thin film transistor.

In the second embodiment, the first scan signal and the second scan signal may be voltage signals having different voltage levels and signal waveforms.

In the second embodiment, the first gate line and the second gate line are formed in parallel with each other, and the data line is formed in a direction crossing the first gate line and the second gate line.

In the second embodiment, the control thin film transistor and the switching thin film transistor are characterized in that the same channel type.

In the liquid crystal display panel according to the first and second embodiments of the present invention having the above characteristics, a phenomenon in which the feed through voltage ΔVp is different for each pixel according to the voltage level deviation between the data voltage and the gate high voltage is known. It is improved to exhibit the same feed-through voltage (ΔVp) characteristics regardless of the data voltage. This provides effects of flicker improvement and afterimage improvement in video display.

Hereinafter, each embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, the liquid crystal display panel according to the present invention supplies a specific voltage (or data voltage) to the gate electrode of the switching thin film transistor in advance so as to have the same feed throw voltage (ΔVp) for each data voltage, and then charges it again. The gate high voltage or the gate low voltage of the scan signal is supplied to the gate electrode of the switching thin film transistor.

First embodiment

3A and 3B are a pixel equivalent circuit diagram and a signal timing diagram according to the first embodiment of the present invention, respectively.

As shown in FIG. 3A, in the liquid crystal display panel according to the first embodiment of the present invention, a first gate line GL1 in which a first scan signal Vg1 and a second scan signal Vg2 are respectively applied on a substrate and are parallel to each other. And a data line DL crossing the second gate line GL2, the first gate line GL1, and the second gate line GL2, to which a data voltage Vdata is applied, and the second gate line GL. A control thin film transistor TFT-C connected to GL2) and the data line DL, a control capacitor Ccon formed between the control thin film transistor TFT-C and the first gate line GL1; A switching thin film transistor TFT-SW connected to the data line DL and controlled by an output of the control thin film transistor TFT-C, and a liquid crystal capacitor Clc connected to the switching thin film transistor TFT-SW. ) And a storage capacitor Cstg.

In this case, the control thin film transistor (TFT-C) and the switching thin film transistor (TFT-SW) are the same channel type, and are configured as n-type for convenience of description.

The pixel structure of the liquid crystal display panel according to the first embodiment of the present invention is a control film TFT (TFT-C) and the control capacitor (Ccon) in a structure of a thin film transistor / 1 capacitor (1T-1C), which is a conventional liquid crystal pixel structure. ) And 2T-2C pixel structure with gate line added.

An operation example of the pixel having the above-described structure will be described with reference to the signal timing diagram of FIG. 3B.

First, as in section ①, a first gate high voltage Vgh1-1 is applied to the first gate line GL1 through a first scan signal Vg1, and a second gate line GL2 is applied to the first gate line GL2. The gate high voltage Vgh2 of the two scan signals Vg2 is applied, and the state is changed to the state in which the data voltage Vdata is applied to the data line DL.

Accordingly, the control thin film transistor TFT-C is switched on-switched by the second scan signal Vg2, and the node N corresponding to the gate electrode of the switching thin film transistor TFT-SW is Vdata. Is charged. In this case, the first gate high voltage Vgh1-1 may be selected to a voltage such that the switching thin film transistor TFT-SW cannot be switched to an on-switching state.

Subsequently, in a section ②, the gate low voltage Vgl2 of the second scan signal Vg2 is applied to the second gate line GL2, and the first gate high voltage Vgh1 is applied to the first gate line GL1. A second gate high voltage Vgh1- which has a voltage level higher than that of -1 and which is boot-straped to a voltage level capable of switching the switching thin film transistor TFT-SW to an on-switching state. 2) is applied.

Accordingly, the control thin film transistor TFT-C is switched to the off-switching state, and the switching thin film transistor TFT-SW is switched to the on-switching state so that the data voltage Vdata is transferred to the storage capacitor Cstg. In addition to being stored, it is supplied to the liquid crystal capacitor Clc to represent gray scale.

In this operation, the node N corresponding to the gate electrode of the switching thin film transistor TFT-SW is already charged with Vdata in the section ①, and then boots-straps to the voltage level (Vgh1-2). In practice, the changed voltage in switching the switching state of the switching thin film transistor TFT-SW is shown as {Vdata + A * [(Vgh1-2)-(Vgh1-1)]}. In this case, A is a value determined by the control capacitor Ccon and the parasitic capacitors and satisfying a relationship of 0 <A <1.

That is, even if the data voltage Vdata is applied to a pixel at any voltage level, the voltage difference between the data voltage Vdata and the gate high voltage for on-switching the switching thin film transistor TFT-SW is A * [( Vgh1-2)-(Vgh1-1)].

For example, assuming that a first data voltage applied to an arbitrary first pixel is 5.5V and a second data voltage applied to any second pixel horizontally adjacent to the first pixel is 5.0V. When the gate high voltage for the on-switching of the switching thin film transistor is 25.5V, the gate high voltage for the on-switching of the switching thin film transistor of the second pixel is 25.0V.

In this case, the gate-low voltage for off-switching of the switching thin film transistor TFT-SW is also provided through bootstrapping, similarly to the operation of the gate high voltage. It is natural to operate to have the same voltage difference for Vdata).

Therefore, when each of the first scan signal Vg1 and the second scan signal Vg2 is provided with the same voltage to each of the first gate line GL1 and the second gate line GL2 configured in the entire liquid crystal display panel, In each pixel, since the voltage difference between the gate high voltage Vgh and the data voltage Vdata is the same for all data voltages, each pixel is conventionally a pixel according to a voltage level deviation between the data voltage and the gate high voltage. The phenomenon in which the feed trough voltage ΔVp is different from each other is improved, so that the same feed trough voltage ΔVp appears regardless of the data voltage. This provides the effect of the flicker improvement and the afterimage improvement in the video display.

Second embodiment

4A and 4B are a pixel equivalent circuit diagram and a signal timing diagram according to the second embodiment of the present invention, respectively.

As shown in FIG. 4A, in the liquid crystal display panel according to the second exemplary embodiment of the present invention, a first gate line GL1 in which a first scan signal Vg1 and a second scan signal Vg2 are applied to the substrate and are parallel to each other. And a data line DL crossing the second gate line GL2, the first gate line GL1 and the second gate line GL2, to which a data voltage Vdata is applied, and the second scan signal A control capacitor configured to be switched by Vg2) and output the first scan signal Vg1, and a control capacitor configured between the control thin film transistor TFT-C and the data line DL. (Ccon), a switching thin film transistor (TFT-SW) connected to the data line (DL) and controlled to be controlled by the output of the control thin film transistor (TFT-C), and the switching thin film transistor (TFT-SW). Defined as one pixel including the liquid crystal capacitor (Clc) and the storage capacitor (Cstg) connected to the It is constructed.

In this case, the control thin film transistor (TFT-C) and the switching thin film transistor (TFT-SW) are the same channel type, and are configured as n-type for convenience of description.

The pixel structure of the liquid crystal display panel according to the second embodiment of the present invention is the control thin film transistor TFT-C and the control capacitor in a 1-thin film transistor / 1-capacitor 1T-1C structure which is a conventional liquid crystal pixel structure. (Ccon) is added to add 2T-2C pixel structure and one more gate line.

An operation example of the pixel having the above-described structure will be described with reference to the signal timing diagram of FIG. 4B.

First, in a section ①, the first gate high voltage Vgh1 of the first scan signal Vg1 is applied to the first gate line GL1, and the second scan signal is applied to the second gate line GL2. The gate high voltage Vgh2 of Vg2 is applied, and the state is changed to a state in which the data voltage Vdata is not applied to the data line DL.

Accordingly, the control thin film transistor TFT-C outputs the gate high voltage Vgh1 of the first scan signal Vg1 applied to the first gate line GL1, and thus the switching thin film transistor TFT-SW. The node N corresponding to the gate electrode of the () is charged to (Vgh1) and switches the switching thin film transistor TFT-SW to an on-switching state. However, in the section ①, there is no data voltage Vdata applied to the data line DL in spite of switching the switching thin film transistor TFT-SW to an on-switching state, thereby the liquid crystal capacitor Clc and the storage capacitor. There is no signal voltage provided to (Cstg).

Subsequently, in a section ②, the gate low voltage Vgl2 of the second scan signal Vg2 is applied to the second gate line GL2, and the first gate line GL1 continuously maintains a first gate high voltage ( Vgh1) is applied, and a data voltage Vdata is applied to the data line DL.

Accordingly, the control thin film transistor TFT-C is switched to an off-switching state, and the switching thin film transistor TFT-SW outputs the data voltage Vdata in a continuous on-switching state to store the storage capacitor Cstg. In addition to being stored in the liquid crystal capacitor Clc, the gray scale is represented.

In this operation, since the node N corresponding to the gate electrode of the switching thin film transistor TFT-SW is already charged with the voltage of Vgh1 in the section ①, the data voltage Vdata is applied in the subsequent section ②. When the data voltage Vdata and the switching thin film transistor TFT-SW are on-switched, the voltage difference between the last provided gate high voltage, that is, {Vgh1 + A * (Vdata-Vgnd)} is Vgh1. It is fixed constantly. In this case, Vgnd is a ground potential, and A is a value determined by the control capacitor Ccon and parasitic capacitors and satisfying a relationship of 0 <A <1.

In addition, in the section ③, the node N is charged to Vgl1 by the control thin film transistor TFT-C to turn off the switching thin film transistor TFT-SW.

Therefore, when each of the first scan signal Vg1 and the second scan signal Vg2 is provided with the same voltage to each of the first gate line GL1 and the second gate line GL2 configured in the entire liquid crystal display panel, In each pixel, since the voltage difference between the gate high voltage Vgh and the data voltage Vdata is the same for all data voltages, each pixel is conventionally a pixel according to a voltage level deviation between the data voltage and the gate high voltage. The phenomenon in which the feed trough voltage ΔVp is different from each other is improved, so that the same feed trough voltage ΔVp appears regardless of the data voltage. This provides the effect of the flicker improvement and the afterimage improvement in the video display.

1 is a diagram illustrating an equivalent circuit for one pixel of a general liquid crystal display panel.

2 is a signal timing diagram for explaining an operation of the pixel of FIG. 1.

3A and 3B are pixel equivalent circuit diagrams and signal timing diagrams according to the first embodiment of the present invention, respectively.

4A and 4B are a pixel equivalent circuit diagram and a signal timing diagram according to the second embodiment of the present invention, respectively.

<Brief description of the main parts of the drawing>

Vg1, Vg2: First and second scan signals Ccon: Control capacitor

DL: Data line GL1, GL2: First and second gate lines

TFT-C: Control Thin Film Transistor

TFT-SW: Switching Thin Film Transistor

Claims (9)

A data line to which a data voltage is applied; A first gate line and a second gate line to which the first scan signal and the second scan signal are respectively applied; A control thin film transistor connected to the second gate line and the data line; A control capacitor configured between the control thin film transistor and the first gate line; A switching thin film transistor connected to the data line and controlled to be controlled by an output of the control thin film transistor; Liquid crystal capacitor and storage capacitor connected to the switching thin film transistor Liquid crystal display panel comprising a The method according to claim 1, The first scan signal and the second scan signal are voltage signals having different voltage levels and signal waveforms. The method according to claim 1, The first scan signal includes a gate low voltage, a first gate high voltage, and a second gate high voltage, and the second scan signal is a voltage signal consisting of a gate low voltage and a gate high voltage. panel The method according to claim 1, The first gate line and the second gate line may be formed in parallel with each other, and the data line may be formed in a direction crossing the first gate line and the second gate line. The method according to claim 1, The control thin film transistor and the switching thin film transistor are of the same channel type, the liquid crystal display panel A data line to which a data voltage is applied; A first gate line and a second gate line to which the first scan signal and the second scan signal are respectively applied; A control thin film transistor which is switched by the second scan signal and outputs the first scan signal; A control capacitor configured between the control thin film transistor and the data line; A switching thin film transistor connected to the data line and controlled to be controlled by an output of the control thin film transistor; Liquid crystal capacitor and storage capacitor connected to the switching thin film transistor Liquid crystal display panel comprising a The method of claim 6, The first scan signal and the second scan signal are voltage signals having different voltage levels and signal waveforms. The method of claim 6, The first gate line and the second gate line may be formed in parallel with each other, and the data line may be formed in a direction crossing the first gate line and the second gate line. The method of claim 6, The control thin film transistor and the switching thin film transistor are of the same channel type, the liquid crystal display panel

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