KR20070002516A - Method for forming landing plug of semiconductor device - Google Patents

Method for forming landing plug of semiconductor device Download PDF

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KR20070002516A
KR20070002516A KR1020050058085A KR20050058085A KR20070002516A KR 20070002516 A KR20070002516 A KR 20070002516A KR 1020050058085 A KR1020050058085 A KR 1020050058085A KR 20050058085 A KR20050058085 A KR 20050058085A KR 20070002516 A KR20070002516 A KR 20070002516A
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landing plug
cmp
epitaxial silicon
film
gates
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KR1020050058085A
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Korean (ko)
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이훈
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주식회사 하이닉스반도체
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Publication of KR20070002516A publication Critical patent/KR20070002516A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method for forming a landing plug of a semiconductor device is provided to minimize the dishing of the landing plug and to secure an SAC(Self-Aligned Contact) margin by performing directly a landing plug CMP(Chemical Mechanical Polishing) process on an amorphous epitaxial silicon layer without a post annealing process on the epitaxial silicon layer. A plurality of gates(26) and junction regions(27) are formed on a semiconductor substrate(21). An interlayer dielectric(28) is formed thereon. Contact holes for exposing simultaneously the gates and junction regions are formed on the resultant structure by etching selectively the interlayer dielectric. An amorphous epitaxial silicon layer for filling the contact holes is formed on the resultant structure by using an SPE(Solid Phase Epitaxy). A CMP process is performed on the epitaxial silicon layer until the gates are exposed to the outside.

Description

반도체 소자의 랜딩 플러그 형성방법{Method for forming landing plug of semiconductor device}Method for forming landing plug of semiconductor device

도 1a 및 도 1b는 종래의 랜딩 플러그 형성방법을 설명하기 위한 공정별 단면도.Figure 1a and 1b is a cross-sectional view for each process for explaining a conventional landing plug forming method.

도 2a 내지 도 2c는 본 발명에 따른 랜딩 플러그 형성방법을 설명하기 위한 공정별 단면도.Figures 2a to 2c is a cross-sectional view for each process for explaining a landing plug forming method according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21: 반도체기판 22: 소자분리막21: semiconductor substrate 22: device isolation film

23: 게이트절연막 24: 게이트도전막23: gate insulating film 24: gate conductive film

25: 하드마스크 질화막 26: 게이트25: hard mask nitride layer 26: gate

27: 접합영역 28: 층간절연막27: junction region 28: interlayer insulating film

29: 비정질 상태의 에피 실리콘막 29a: 랜딩 플러그 29: epitaxial silicon film in amorphous state 29a: landing plug

본 발명은 반도체 소자의 랜딩 플러그 형성방법에 관한 것으로, 보다 상세하게는, 랜딩 플러그 형성을 SPE 공정을 이용하여 형성한 후, 후속 어닐링 공정을 수 행하지 않고 랜딩 플러그 CMP를 수행하여 랜딩 플러그에 발생하는 디싱(dishing)을 최소화 할 수 있는 반도체 소자의 랜딩 플러그 형성방법에 관한 것이다.The present invention relates to a method of forming a landing plug of a semiconductor device, and more particularly, to form a landing plug by using an SPE process, and then perform a landing plug CMP without performing a subsequent annealing process to generate a landing plug. The present invention relates to a method for forming a landing plug of a semiconductor device capable of minimizing dishing.

반도체 소자의 고집적화에 따라 상하부 패턴들간, 특히 기판 접합영역과 비트라인간 및 기판 접합영역과 캐패시터간이 전기적 연결에 어려움을 겪게 되었다. 이에 따라, 최근의 반도체 제조 공정에서는 자기정렬콘택(self aligned contact : 이하 SAC)을 통해 접합영역 상에 랜딩 플러그를 형성함으로써, 이러한 랜딩 플러그에 의해 상하부 패턴들간의 안정적인 전기적 연결이 이루어지도록 하고 있다.Due to the high integration of semiconductor devices, it has been difficult to electrically connect between upper and lower patterns, in particular, between the substrate junction region and the bit line, and between the substrate junction region and the capacitor. Accordingly, in a recent semiconductor manufacturing process, a landing plug is formed on a junction region through a self aligned contact (hereinafter referred to as SAC), such that the landing plug enables stable electrical connection between upper and lower patterns.

이하에서는 종래의 랜딩 플러그 형성방법을 도 1a 및 도 1b를 참조해서 간략하게 설명하도록 한다.Hereinafter, a conventional landing plug forming method will be briefly described with reference to FIGS. 1A and 1B.

도 1a를 참조하면, 소자분리막(2)을 구비한 반도체기판(1) 상에 게이트산화막(3), 게이트도전막(4) 및 하드마스크 질화막(5)의 적층 구조로된 수 개의 게이트(6)를 형성한 후, 상기 게이트의 양측벽에 스페이서(미도시)를 형성한다. 그런다음, 상기 게이트 양측의 기판 표면 내에 접합영역(7)을 형성한다.Referring to FIG. 1A, several gates 6 having a stacked structure of a gate oxide film 3, a gate conductive film 4, and a hard mask nitride film 5 on a semiconductor substrate 1 having an isolation layer 2 are provided. ) Is formed, and spacers (not shown) are formed on both side walls of the gate. Then, a junction region 7 is formed in the substrate surface on both sides of the gate.

다음으로, 상기 게이트(6)를 덮도록 기판 전면 상에 층간절연막(8)을 증착한 후, 그 표면을 CMP(chemical mechanical polishing)하여 평탄화시킨다. 그런다음, 상기 평탄화된 층간절연막(8)을 식각하여 수 개의 게이트(6) 및 기판 접합영역(7)을 동시에 노출시키는 랜딩 플러그 콘택(landing plug contact)을 형성한 후, 상기 랜딩 플러그 콘택을 매립하도록 기판 결과물 상에 폴리실리콘막(9)을 증착한다.Next, after the interlayer insulating film 8 is deposited on the entire surface of the substrate to cover the gate 6, the surface is planarized by chemical mechanical polishing (CMP). Then, the planarized interlayer insulating film 8 is etched to form a landing plug contact which simultaneously exposes several gates 6 and the substrate junction region 7, and then embeds the landing plug contact. The polysilicon film 9 is deposited on the substrate resultant.

도 1b를 참조하면, 상기 게이트의 하드마스크 질화막(5)이 노출될 때까지 상기 폴리실리콘막(9)과 층간절연막(8)을 CMP하고, 이를 통해, 게이트(6)들 사이의 기판 접합영역(7) 상에 랜딩 플러그(9a)를 형성한다. Referring to FIG. 1B, the polysilicon film 9 and the interlayer insulating film 8 are CMP until the hard mask nitride film 5 of the gate is exposed, and thereby, the substrate bonding region between the gates 6. The landing plug 9a is formed on (7).

그러나, 종래의 랜딩 플러그 형성방법에 따르면, 상기 폴리실리콘막(9)의 CMP 공정시 층간절연막용 슬러리를 이용하여 CMP 하게 되면 이 과정에서 상기 층간절연막(8), 하드마스크 질화막(5) 및 폴리실리콘막(9)이 동시에 연마되면서 각 층의 제거속도(removal rate)의 차이에 따라 제거속도가 빠른 폴리실리콘막(9)의 디싱이 발생하게 되어 SAC 마진이 작아지게 된다.However, according to the conventional landing plug forming method, when the CMP process of the polysilicon film 9 is performed using the slurry for the interlayer insulating film, the interlayer insulating film 8, the hard mask nitride film 5, and the poly As the silicon film 9 is polished at the same time, dishing of the polysilicon film 9 having a high removal rate occurs according to a difference in removal rate of each layer, thereby reducing the SAC margin.

현재 반도체 소자의 수율을 증가 시키기 위한 목적으로 종래의 랜딩 플러그 를 대체하여 셀 플러그(cell plug)에 베이스라인(baseline)으로 적용중인 것이 SPE(Solid Phase epitaxy)공정이다. SPE 공정에 따라 비정질 상태의 에피 실리콘막을 형성한 후, 비정질 상태의 에피 실리콘막이 결정화되도록 어닐링 공정을 하게 되며, 이후 에피 실리콘막 CMP를 통해 랜딩 플러그를 형성하게 된다.In order to increase the yield of semiconductor devices, SPE (Solid Phase Epitaxy) is being applied as a baseline to a cell plug instead of a conventional landing plug. After forming the epitaxial silicon film in the amorphous state according to the SPE process, the annealing process is performed to crystallize the amorphous episilicon film, and then the landing plug is formed through the episilicon film CMP.

이 과정에서 SPE는 어닐링 공정에 유무에 따라 랜딩 플러그 CMP의 식각률(removal rate)의 차이가 발생하며, 어닐링 공정을 거치면 식각률이 빨라지게 되어 랜딩 플러그의 디싱 현상을 더욱 악화시킨다. 이러한 디싱으로 인해 SAC 마진이 작아지게 된다.In this process, the difference in the removal rate of the landing plug CMP occurs depending on the presence or absence of the annealing process, and the annealing process causes the etching rate to be faster, thereby worsening the dishing phenomenon of the landing plug. This dishing results in a smaller SAC margin.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로서, 랜딩 플러그에 발생되는 디싱을 최소화 할 수 있는 반도체 소자의 랜딩 플러그 형성방법을 제공함에 그 목적이 있다. Accordingly, an object of the present invention is to provide a method for forming a landing plug of a semiconductor device capable of minimizing dishing occurring in a landing plug.

상기와 같은 목적을 달성하기 위하여, 본 발명은, 다수의 게이트 및 접합영역이 형성된 반도체기판을 제공하는 단계; 상기 기판 전면 상에 층간절연막을 형성하는 단계; 상기 층간절연막을 식각하여 수 개의 게이트 및 접합영역을 동시에 노출시키는 콘택홀을 형성하는 단계; 상기 콘택홀을 매립하도록 SPE 공정에 따라 비정질 상태의 에피 실리콘막을 형성하는 단계; 상기 게이트가 노출될 때까지 에피 실리콘막을 CMP하는 단계; 및 상기 비정질 상태의 에피 실리콘막이 결정화되도록 기판 결과물을 열처리하는 단계;를 포함하는 반도체 소자의 랜딩 플러그 형성방법을 제공한다. In order to achieve the above object, the present invention provides a semiconductor substrate comprising a plurality of gates and a junction region formed; Forming an interlayer insulating film on the entire surface of the substrate; Etching the interlayer insulating layer to form a contact hole exposing several gates and a junction region at the same time; Forming an epitaxial silicon film in an amorphous state according to an SPE process so as to fill the contact hole; CMP the epi silicon film until the gate is exposed; And heat treating a substrate resultant material so that the epitaxial silicon film in the amorphous state is crystallized.

여기서, 상기 비정절 상태의 에피 실리콘막은 1000Å 이상의 두께로 형성한다.Here, the epi silicon film in the amorphous state is formed to a thickness of 1000 GPa or more.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 랜딩 플러그 형성방법을 설명하기 위한 공정별 단면도이다.2A through 2C are cross-sectional views illustrating processes of forming a landing plug of a semiconductor device according to an exemplary embodiment of the present invention.

도 2a를 참조하면, 액티브영역을 한정하는 소자분리막(22)이 형성된 반도체기판(21) 상에 게이트절연막(23)을 층착한 후, 상기 게이트절연막(23) 상에 폴리실리콘막 및 텅스텐실리사이드막의 적층막으로 이루어진 게이트도전막(24)을 층착하고, 상기 게이트도전막(24) 상에 하드마스크 질화막(25)을 증착한다.Referring to FIG. 2A, after the gate insulating layer 23 is deposited on the semiconductor substrate 21 on which the device isolation layer 22 defining the active region is formed, the polysilicon layer and the tungsten silicide layer may be formed on the gate insulating layer 23. A gate conductive film 24 made of a laminated film is laminated, and a hard mask nitride film 25 is deposited on the gate conductive film 24.

다음으로, 상기 하드마스크 질화막(25), 게이트도전막(24) 및 게이트절연막 (23)을 식각하여 수 개의 게이트(26)를 형성한다. 그런다음, 상기 게이트(26) 양측벽에 스페이서(미도시)를 형성한다.Next, the hard mask nitride layer 25, the gate conductive layer 24, and the gate insulating layer 23 are etched to form several gates 26. Then, spacers (not shown) are formed on both side walls of the gate 26.

이어서, 상기 기판 결과물에 대해 소오스/드레인 이온주입을 수행하여 게이트(26) 양측 기판 표면 내에 접합영역(27)을 형성한다. Subsequently, source / drain ion implantation is performed on the substrate product to form a junction region 27 in the substrate surface on both sides of the gate 26.

계속해서, 상기 기판 결과물 상에 산화막 재질의 층간절연막(28)을 증착한다.Subsequently, an interlayer insulating film 28 made of an oxide film is deposited on the substrate product.

도 2b를 참조하면, 상기 층간절연막을 CMP(chemical mechanical polishing)하여 평탄화시킨다. 그런다음, 상기 평탄화된 층간절연막(28)을 식각하여 수 개의 게이트(26) 및 기판 접합영역(27)을 동시에 노출시키는 랜딩 플러그 콘택(landing plug contact)을 형성한다. Referring to FIG. 2B, the interlayer insulating layer is planarized by chemical mechanical polishing (CMP). The planarized interlayer insulating film 28 is then etched to form a landing plug contact that simultaneously exposes several gates 26 and substrate junction regions 27.

다음으로, 상기 노출된 게이트(26)를 포함한 CMP된 층간절연막(28) 상에 랜딩 플러그 콘택이 매립되도록 SPE 공정에 따라 비정질 상태의 에피 실리콘막(29)을 증착한다. Next, an epitaxial epitaxial layer 29 is deposited on the CMP interlayer dielectric layer 28 including the exposed gate 26 to form a landing plug contact.

도 2c를 참조하면, 상기 비정질 상태의 에피 실리콘막(29)과 층간절연막(28)을 게이트(26)의 하드마스크 질화막(25)이 노출될 때까지 CMP한다.Referring to FIG. 2C, the epitaxial silicon film 29 and the interlayer insulating film 28 in the amorphous state are CMP until the hard mask nitride film 25 of the gate 26 is exposed.

다음으로, 상기 CMP된 비정질 상태의 에피 실리콘막(29)이 결정화되도록 기판 결과물을 열처리하여 본 발명에 따른 랜딩 플러그(29a)를 완성한다. Next, the substrate resultant is heat-treated so that the CMP episilicon film 29 in the amorphous state is crystallized to complete the landing plug 29a according to the present invention.

여기서, 본 발명의 방법은 SPE 공정에 따라 비정질 상태의 에피 실리콘막(29)을 증착한 후, 어닐링 공정을 수행하지 않고 CMP를 수행한다. 따라서, 비정질 상태의 에피 실리콘막(29) CMP 공정시 하드마스크 질화막(25)과 비정질 상태의 에 피 실리콘막(29)의 식각률 차이가 작아지게 되어 랜딩 플러그(29a)의 디싱을 최소화 할 수 있다.Herein, the method of the present invention deposits the epitaxial silicon film 29 in an amorphous state according to the SPE process, and then performs CMP without performing an annealing process. Accordingly, the difference in etching rate between the hard mask nitride layer 25 and the amorphous silicon layer 29 in the amorphous state during the CMP process of the amorphous silicon layer 29 may be reduced, thereby minimizing dishing of the landing plug 29a. .

상기 에피 실리콘막(29) CMP 후, 후속 열처리를 진행함으로 CMP전의 어닐링 공정은 진행하지 않아도 무방하며, 이에 따른 공정 단순화에도 기여하게 된다.After the epi silicon film 29 CMP, the annealing process before the CMP does not have to proceed, thereby contributing to the process simplification.

이상에서와 같이, 본 발명은 랜딩 플러그 형성은 SPE 공정에 따라 비정질 상태의 에피 실리콘막을 증착한 후, 후속 어닐링 공정을 수행하지 않고 랜딩 플러그 CMP를 수행함으로서, 랜딩 플러그에 발생하는 디싱(dishing)을 최소화 할 수 있어 SAC 마진을 확보할 수 있다.As described above, in the present invention, the landing plug is formed by depositing an epitaxial epi-silicon film according to the SPE process and then performing landing plug CMP without performing a subsequent annealing process, thereby causing dishing to occur in the landing plug. It can be minimized to secure SAC margin.

랜딩 플러그 CMP 후, 후속 열공정을 진행을 하기 때문에 랜딩 플러그 CMP 전의 어닐링 공정은 수행하지 않아도 무방하다. 이에 따라, 공정 단순화을 얻을 수 있다.After the landing plug CMP, the subsequent thermal process is performed, so the annealing process before the landing plug CMP may not be performed. Thus, process simplification can be obtained.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

Claims (2)

다수의 게이트 및 접합영역이 형성된 반도체기판을 제공하는 단계; Providing a semiconductor substrate having a plurality of gates and junction regions formed therein; 상기 기판 전면 상에 층간절연막을 형성하는 단계; Forming an interlayer insulating film on the entire surface of the substrate; 상기 층간절연막을 식각하여 수 개의 게이트 및 접합영역을 동시에 노출시키는 콘택홀을 형성하는 단계; Etching the interlayer insulating layer to form a contact hole exposing several gates and a junction region at the same time; 상기 콘택홀을 매립하도록 SPE 공정에 따라 비정질 상태의 에피 실리콘막을 형성하는 단계; Forming an epitaxial silicon film in an amorphous state according to an SPE process so as to fill the contact hole; 상기 게이트가 노출될 때까지 에피 실리콘막을 CMP하는 단계; 및 CMP the epi silicon film until the gate is exposed; And 상기 비정질 상태의 에피 실리콘막이 결정화되도록 기판 결과물을 열처리하는 단계;를 포함하는 반도체 소자의 랜딩 플러그 형성방법.And heat-treating the substrate product to crystallize the epitaxial silicon film in the amorphous state. 제 1 항에 있어서, 상기 비정질 상태의 에피 실리콘막은 1000Å 이상의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 랜딩 플러그 형성방법.The method of claim 1, wherein the amorphous epi silicon film is formed to a thickness of 1000 GPa or more.
KR1020050058085A 2005-06-30 2005-06-30 Method for forming landing plug of semiconductor device KR20070002516A (en)

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