KR20070000723A - Wbl tape and semiconduct package with wbl tape - Google Patents

Wbl tape and semiconduct package with wbl tape Download PDF

Info

Publication number
KR20070000723A
KR20070000723A KR1020050056292A KR20050056292A KR20070000723A KR 20070000723 A KR20070000723 A KR 20070000723A KR 1020050056292 A KR1020050056292 A KR 1020050056292A KR 20050056292 A KR20050056292 A KR 20050056292A KR 20070000723 A KR20070000723 A KR 20070000723A
Authority
KR
South Korea
Prior art keywords
wbl
tape
die
wbl tape
substrate
Prior art date
Application number
KR1020050056292A
Other languages
Korean (ko)
Other versions
KR100713909B1 (en
Inventor
김승지
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR20050056292A priority Critical patent/KR100713909B1/en
Publication of KR20070000723A publication Critical patent/KR20070000723A/en
Application granted granted Critical
Publication of KR100713909B1 publication Critical patent/KR100713909B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

A WBL(Wafer Backside Lamination) tape and a semiconductor package using the same are provided to improve reliability by exhausting voids from the WBL tape using grooves. A WBL tape(10) is used for attaching a die onto a substrate. A plurality of grooves(11) are formed on the WBL tape in order to remove voids from the WBL tape. The plurality of grooves are spaced apart from each other. The groove is formed like one selected from a group consisting of a line type structure or a cross type structure. The WBL tape is interposed between the die and the substrate, so that the die is stably attached to the substrate without voids.

Description

더블유비엘 테입 및 이를 이용한 반도체 패키지{WBL tape and semiconduct package with WBL tape}WBI tape and semiconductor package using same {WBL tape and semiconduct package with WBL tape}

도 1a 및 도 1b는 본 발명의 일 실시예에 따른 WBL 테입을 나타낸 사시도,1a and 1b is a perspective view showing a WBL tape according to an embodiment of the present invention,

도 2는 도 1의 WBL 테입을 이용한 반도체 패키지를 나타낸 단면도.FIG. 2 is a cross-sectional view illustrating a semiconductor package using the WBL tape of FIG. 1. FIG.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10,20... WBL 테입 11,12... 홈10,20 ... WBL Tape 11,12 ... Home

본 발명은 WBL 테입 및 이를 이용한 반도체 패키지에 관한 것으로서, 특히 기판 상에 다이를 부착 시 발생하는 보이드의 제거를 위한 WBL 테입 및 이를 이용한 반도체 패키지에 관한 것이다.The present invention relates to a WBL tape and a semiconductor package using the same, and more particularly, to a WBL tape and a semiconductor package using the same for removing voids generated when a die is attached to a substrate.

종래 다이 부착 공정에서 사용되는 리퀴드(liquid) 접착제는 직접 기판 상에 접착제를 도포한 후, 다이(die)를 압착하는 순간 접착제가 다이 외부로 밀려 나가면서 접착제에 의하여 발생한 보이드(void)를 같이 외부로 밀어내어 패키지의 신뢰성에는 문제가 없었으나, 본드 라인(bond line)의 두께가 크고, 웨팅 콘트롤(wetting control)이 필요하여 새로운 접착제가 요구되었다.Liquid adhesive used in the conventional die attach process is applied directly on the substrate, the moment the pressing the die is pushed to the outside of the die as the adhesive (void) generated by the adhesive outside Although there was no problem in the reliability of the package by pushing it out, the new adhesive was required due to the large thickness of the bond line and the need for wetting control.

이러한 요구에 부응하기 위하여 WBL(wafer backside lamination) 테입이 출현하였는데, 이 WBL 테입은 종래의 리퀴드 접착제보다 본드 라인의 두께가 얇고, 웨팅 콘트롤이 필요 없어 적층형 패키지나 칩의 단부에서 리드까지의 거리가 가까운 패키지에 많이 사용되고 있다.To meet these demands, wafer backside lamination (WBL) tapes have emerged. These WBL tapes have a smaller bond line thickness than conventional liquid adhesives, and do not require wetting control, so the distance from the end of the stacked package or chip to the lead is reduced. It's used a lot in nearby packages.

그런데, 이러한 WBL 테입은 웨이퍼 뒷면에 테입 전체가 붙어 있어 다이 부착 공정에서 히터 블럭(heater block)과 본드 툴(bond tool)과의 언밸런스(unbalance), 본드 툴 자체의 평탄도나 마모, 온도 변화, 다이 워페이지 등과 같은 공정 변수에 의하여 쉽게 보이드가 발생하여 패키지의 신뢰성에 악영향을 끼치는 문제점이 있다.However, the WBL tape has the entire tape on the back side of the wafer, and thus, unbalance between the heater block and the bond tool in the die attach process, flatness or wear of the bond tool itself, temperature change, and die Voids are easily generated by process variables such as warpage, which adversely affects the reliability of the package.

본 발명은 상기의 문제점을 해결하기 위하여 창출된 것으로서, 패키지의 신뢰성을 확보할 수 있도록 개선된 WBL 테입 및 이를 이용한 반도체 패키지를 제공하는 것을 그 목적으로 한다.The present invention was created to solve the above problems, and an object thereof is to provide an improved WBL tape and a semiconductor package using the same.

상기의 목적을 달성하기 위한 본 발명의 WBL 테입은, 기판 상에 다이를 부착하기 위한 것으로서, 상기 WBL 테입에는 보이드 제거를 위하여 일정한 간격으로 다수의 홈이 형성된다.The WBL tape of the present invention for achieving the above object is to attach a die on a substrate, a plurality of grooves are formed in the WBL tape at regular intervals for void removal.

여기서, 상기 다수의 홈은 일자 및 십자 형태 중 어느 하나인 것이 바람직하다.Here, the plurality of grooves is preferably any one of the date and cross shape.

그리고, 본 발명의 WBL 테입을 이용한 반도체 패키지는, 기판; 상기 기판 상 에 일면이 열 압착되며, 중심에 홈이 형성된 WBL 테입; 상기 WBL 테입의 타면 상에 부착된 다이; 상기 기판과 상기 다이를 전기적으로 연결하는 와이어; 및 상기 홈을 채우며, 상기 다이와 상기 와이어를 밀봉하는 EMC를 포함한다. In addition, the semiconductor package using the WBL tape of the present invention, the substrate; One surface is thermally compressed on the substrate, the groove WBL tape is formed in the center; A die attached to the other side of the WBL tape; A wire electrically connecting the substrate and the die; And an EMC filling the groove and sealing the die and the wire.

여기서, 상기 홈은 일자 및 십자 형태 중 어느 하나인 것이 바람직하다.Here, the groove is preferably one of the date and cross shape.

이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 및 도 1b는 본 발명의 일 실시예에 따른 WBL 테입을 나타낸 사시도이다.1A and 1B are perspective views illustrating a WBL tape according to an embodiment of the present invention.

도면을 참조하면, WBL 테입(10,20)은 일정한 간격으로 다수의 홈(11,21)이 형성된다. 여기서, 일정한 간격은 WBL 테입(10,20)에 부착되는 다이(미도시)의 피치(pitch)와 동일한 피치를 말하며, 이는 WBL 테입(10,20) 상에 다이가 부착될 경우, 다이의 중앙에 홈이 위치하도록 하기 위함이다.Referring to the drawings, the WBL tapes 10 and 20 are formed with a plurality of grooves 11 and 21 at regular intervals. Here, the constant spacing refers to a pitch equal to the pitch of a die (not shown) attached to the WBL tapes 10 and 20, which is the center of the die when the die is attached onto the WBL tapes 10 and 20. This is for the groove to be located in.

홈(11,21)의 형태는 도 1a와 같이 일자형(11) 또는 도 1b와 같이 십자형(21)을 가질 수 있으며, 그 형태는 변형이 가능하다.The grooves 11 and 21 may have a straight shape 11 as shown in FIG. 1A or a cross shape 21 as shown in FIG. 1B, and the shape may be modified.

이 홈(11,21)은 WBL 테입(10,20) 상에 다이가 부착될 경우, WBL 테입(10,20) 상에서 발생할 수 있는 보이드를 외부로 배출하기 위한 경로로써의 역할을 한다. The grooves 11 and 21 serve as a path for discharging voids that may occur on the WBL tapes 10 and 20 to the outside when a die is attached to the WBL tapes 10 and 20.

도 2는 본 발명의 일 실시예에 따른 반도체 패키지의 단면도로서, 이 반도체 패키지에는 상기 도 1a 또는 도 1b에 도시된 바와 같은 WBL 테입이 채용된다.FIG. 2 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention, in which the WBL tape as shown in FIG. 1A or 1B is employed.

여기서, 반도체 패키지의 구성 요소로서의 리드 프레임 등은 종래의 것과 동일하므로 그 설명 및 도면에의 도시는 생략하기로 한다.Here, since the lead frame or the like as a component of the semiconductor package is the same as the conventional one, the description and the drawings in the drawings will be omitted.

도면을 참조하면, 반도체 패키지(70)는 기판(30)과, 기판(30) 상에 일면이 열 압착된 WBL 테입(10)과, WBL 테입(10)의 타면 상에 부착된 다이(40)와, 기판(30)과 다이(40)를 전기적으로 연결하는 와이어(50) 및 다이(40) 및 와이어(50)를 밀봉하여 외부로부터 다이(40) 및 와이어(50)를 보호하는 EMC(epoxy molding compound;60)를 포함한다.Referring to the drawings, the semiconductor package 70 includes a substrate 30, a WBL tape 10 having one surface thermocompressed on the substrate 30, and a die 40 attached to the other surface of the WBL tape 10. And an EMC (epoxy) sealing the wire 50 and the die 40 and the wire 50 electrically connecting the substrate 30 and the die 40 to protect the die 40 and the wire 50 from the outside. molding compound;

WBL 테입(10)은 상기와 같이 다이(40)가 부착될 경우 및 다이(40)가 부착된 상태에서 기판(30)에 열 압착 시, WBL 테입(10)에서 발생할 수 있는 보이드를 외부로 배출하기 위한 경로로써 다이(30)의 중앙에 위치한다.The WBL tape 10 discharges voids that may occur in the WBL tape 10 to the outside when the die 40 is attached as described above and when the die 40 is attached to the substrate 30 by thermocompression bonding. It is located in the center of the die 30 as a path for.

그리고 EMC(60)에 의하여 밀봉 시, EMC(60)는 WBL 테입(10)에 형성된 홈(11)을 채우게 된다. And when sealed by the EMC (60), the EMC (60) fills the groove (11) formed in the WBL tape (10).

이와 같은 구조의 반도체 패키지(70)에 의하면, WBL 테입(10)에 다이(40)가 부착되거나, 다이(40)가 부착된 상태로 기판(30)에 열 압착될 때에도 WBL 테입(10)에서 발생하는 보이드를 홈(11)을 통해서 배출하고, EMC(60)에 의하여 홈(11)을 채우므로 종래에 WBL 테입에서의 보이드 제거 문제를 해결 할 수 있게 된다.According to the semiconductor package 70 having such a structure, even when the die 40 is attached to the WBL tape 10, or when the die 40 is thermocompressed to the substrate 30 with the die 40 attached thereto, Since the generated voids are discharged through the grooves 11 and the grooves 11 are filled by the EMC 60, the void removal problem in the WBL tape can be solved in the related art.

상술한 바와 같이 본 발명의 WBL 테입 및 이를 이용한 반도체 패키지에 의하면, WBL 테입에 형성된 홈을 통하여 보이드를 배출함으로써 반도체 패키지의 신뢰성을 향상시킬 수 있는 효과를 제공한다.As described above, according to the WBL tape and the semiconductor package using the same, the voids are discharged through the grooves formed in the WBL tape, thereby providing an effect of improving the reliability of the semiconductor package.

본 발명은 상기에 설명되고 도면에 예시된 것에 의해 한정되는 것은 아니며, 다음에 기재되는 청구의 범위 내에서 더 많은 변형 및 변용예가 가능한 것임은 물 론이다.It is to be understood that the invention is not limited to that described above and illustrated in the drawings, and that more variations and modifications are possible within the scope of the claims set out below.

Claims (4)

기판 상에 다이를 부착하기 위한 WBL 테입에 있어서,In a WBL tape for attaching a die on a substrate, 상기 WBL 테입에는 보이드 제거를 위하여 일정한 간격으로 다수의 홈이 형성된 것을 특징으로 하는 WBL 테입.The WBL tape WBL tape, characterized in that a plurality of grooves are formed at regular intervals to remove the void. 제1항에 있어서,The method of claim 1, 상기 다수의 홈은 일자 및 십자 형태 중 어느 하나인 것을 특징으로 하는 WBL 테입.The plurality of grooves WBL tape, characterized in that any one of the date and cross shape. 기판;Board; 상기 기판 상에 일면이 열 압착되며, 중심에 홈이 형성된 WBL 테입;One surface is thermally compressed on the substrate, the WBL tape having a groove formed in the center; 상기 WBL 테입의 타면 상에 부착된 다이;A die attached to the other side of the WBL tape; 상기 기판과 상기 다이를 전기적으로 연결하는 와이어; 및A wire electrically connecting the substrate and the die; And 상기 홈을 채우며, 상기 다이와 상기 와이어를 밀봉하는 EMC를 포함한 것을 특징으로 하는 반도체 패키지. And a EMC filling the groove and sealing the die and the wire. 제3항에 있어서,The method of claim 3, 상기 홈은 일자 및 십자 형태 중 어느 하나인 것을 특징으로 하는 반도체 패키지.The groove is a semiconductor package, characterized in that any one of the date and cross shape.
KR20050056292A 2005-06-28 2005-06-28 WBL tape and semiconduct package with WBL tape KR100713909B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR20050056292A KR100713909B1 (en) 2005-06-28 2005-06-28 WBL tape and semiconduct package with WBL tape

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR20050056292A KR100713909B1 (en) 2005-06-28 2005-06-28 WBL tape and semiconduct package with WBL tape

Publications (2)

Publication Number Publication Date
KR20070000723A true KR20070000723A (en) 2007-01-03
KR100713909B1 KR100713909B1 (en) 2007-05-07

Family

ID=37868478

Family Applications (1)

Application Number Title Priority Date Filing Date
KR20050056292A KR100713909B1 (en) 2005-06-28 2005-06-28 WBL tape and semiconduct package with WBL tape

Country Status (1)

Country Link
KR (1) KR100713909B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170022310A (en) 2015-08-20 2017-03-02 (주) 주원테크 Void removal and plasma cleaning composite devices for LED packaging process

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09269201A (en) * 1996-04-01 1997-10-14 Kazuo Saito Measuring tape with through groove bored
KR20020069288A (en) * 2001-02-24 2002-08-30 삼성전자 주식회사 Semiconductor package using tape circuit board forming groove for preventing the encapsulant from overflowing and method for manufacturing thereof
JP2003215383A (en) * 2002-01-28 2003-07-30 Furukawa Electric Co Ltd:The V groove stage for splicing tape-like secondary coated optical fibers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170022310A (en) 2015-08-20 2017-03-02 (주) 주원테크 Void removal and plasma cleaning composite devices for LED packaging process

Also Published As

Publication number Publication date
KR100713909B1 (en) 2007-05-07

Similar Documents

Publication Publication Date Title
US7923304B2 (en) Integrated circuit packaging system with conductive pillars and method of manufacture thereof
US8375576B2 (en) Method for manufacturing wafer scale heat slug system
US7399658B2 (en) Pre-molded leadframe and method therefor
TWI521614B (en) Drop-mold conformable material as an encapsulation for an integrated circuit package system
US8067825B2 (en) Integrated circuit package system with multiple die
CN107978570B (en) Chip packaging structure and manufacturing method thereof
US20080099910A1 (en) Flip-Chip Semiconductor Package with Encapsulant Retaining Structure and Strip
US20100320584A1 (en) Semiconductor chip laminated body
US8058706B2 (en) Delamination resistant packaged die having support and shaped die having protruding lip on support
US20100225007A1 (en) Integrated circuit packaging system with stacked die and method of manufacture thereof
JP2006261485A (en) Semiconductor device and manufacturing method therefor
KR101352814B1 (en) Multi chip stacked package
KR100713909B1 (en) WBL tape and semiconduct package with WBL tape
US7955897B2 (en) Chip structure and stacked chip package as well as method for manufacturing chip structures
US20080230878A1 (en) Leadframe based flip chip semiconductor package and lead frame thereof
US8981548B2 (en) Integrated circuit package system with relief
KR101538680B1 (en) Package on package and method for manufacturing the same
US7183631B2 (en) Package structure module of bump posited type lead frame
US20070108626A1 (en) Flip-chip integrated circuit packaging method
US20080246142A1 (en) Heat dissipation unit and a semiconductor package that has the heat dissipation unit
JP2005327967A (en) Semiconductor device
KR20100002868A (en) Semicondutor package
KR101204741B1 (en) Semiconductor package including heat sink and manufacturing process thereof
TWI534978B (en) Chip package structure
US8987056B2 (en) Integrated circuit package system with support carrier and method of manufacture thereof

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110325

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee