KR20060136242A - Method for fabricating cmos image sensor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a manufacturing process of a CMOS image sensor in which a defect does not occur during a removal process of a hard mask formed to prevent impurities from being injected into a gate electrode during a semiconductor device manufacturing process. . To this end, the present invention, forming a device isolation film on the substrate through an STI process, recessing the device isolation film to form a recess, filling the first protective film for protecting the device isolation film in the recess And depositing a gate insulating film, a gate conductive film, and a hard mask oxide film sequentially on the substrate, and then selectively etching to form a gate pattern. A photodiode in the substrate is formed by ion implantation using the gate pattern as a mask. And forming a second passivation layer on the sidewalls of the gate pattern to protect the gate insulating layer, and removing the hard mask oxide layer.

Hard mask oxide film, photodiode, photoresist pattern, device isolation film, gate insulating film,

Description

Manufacturing method of CMOS image sensor {METHOD FOR FABRICATING CMOS IMAGE SENSOR}

1 is a circuit diagram showing a unit pixel composed of one photodiode (PD) and four MOS transistors in a conventional CMOS image sensor.

2 is a cross-sectional view showing a manufacturing process of the CMOS image sensor according to the prior art.

3A to 3E are cross-sectional views illustrating a manufacturing process of the CMOS image sensor according to the present invention.

Explanation of symbols on the main parts of the drawings

201: p + type substrate 202: p epi layer

203: semiconductor substrate 206: device isolation film

207: first protective film 208: gate insulating film

209: gate conductive film 213: photodiode

214a: pad oxide film 215: pad nitride film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a process of forming a CMOS image sensor during a semiconductor device manufacturing process.

In general, image sensors are used in a wide range of fields, from home products such as digital cameras and mobile phones, to endoscopes used in hospitals, and to satellite telescopes around the earth. The CMOS image sensor is a device that converts an optical image into an electrical signal, and employs a switching method in which a MOS transistor is formed by the number of pixels and the output is sequentially detected using the MOS transistor. The CMOS image sensor is simpler to drive than the CCD image sensor, which is widely used as a conventional image sensor, enables various scanning methods, and can integrate signal processing circuits onto a single chip. In addition to the use of compatible CMOS technology, the manufacturing cost can be lowered and the power consumption is significantly lower. Therefore, it is used in low cost and low power fields such as mobile phones, PCs and surveillance cameras.

FIG. 1 is a circuit diagram illustrating a unit pixel composed of one photodiode (PD) and four MOS transistors in a conventional CMOS image sensor. And a transfer transistor 11 for transporting the photocharges collected from the photodiode 10 to the floating diffusion region 12, and setting the potential of the floating diffusion region to a desired value and discharging electric charges to discharge the floating diffusion region 12. The reset transistor 13 for resetting), the drive transistor 14 serving as a source follower buffer amplifier by applying the voltage of the floating diffusion region to the gate, and addressing the switching (switching role) And a select transistor 15 which performs an addressing role. Outside the unit pixel, a load transistor 16 is formed to read an output signal.

2 is a cross-sectional view showing a manufacturing process of the CMOS image sensor according to the prior art.

Referring to FIG. 2, a semiconductor substrate 103 having a p epitaxial layer 102 formed on a p + type substrate 101 is prepared.

In this case, the reason for using the low concentration p epi layer 102 on the high concentration p + type substrate 101 is first, since the low concentration p epi layer 102 is present, the depletion region (depletion region) of the photodiode is large, Can be deeply increased to increase the photodiode's ability to collect photocharges, and secondly, having a high concentration of p + type substrate 101 underneath the p-type epilayer 102, neighboring units This is because the charge is quickly recombined before the charge spreads to the pixel, thereby reducing the random diffusion of the photocharge, thereby reducing the change in the transfer function of the photocharge.

Subsequently, an isolation layer 104 defining an active region and an isolation region is formed on the semiconductor substrate 103.

In this case, the device isolation film 104 is formed through an STI process that hardly reduces the areas of electrically separating between devices due to the high integration of the device because there is little Bird's Beak.

Subsequently, the gate insulating film 105, the gate conductive film 106, and the hard mask oxide film 107 are sequentially deposited on the substrate, and then the photoresist pattern 108 is formed on the hard mask oxide film 107. Subsequently, the hard mask oxide layer 107 and the gate conductive layer 106 are etched using the photoresist pattern 108 as an etch barrier to form a gate electrode.

Subsequently, after forming an ion implantation mask covering a portion of the upper portion of the gate electrode, an ion implantation process is performed to automatically align the edge portion of the gate electrode to form an n-type impurity region 109.

Subsequently, after removing the ion implantation mask and the photoresist pattern 108, the hard mask oxide layer 107 is removed.

At this time, the hard mask oxide film 107 is removed using HF gas.

However, when the HF gas is used, not only damage is applied to the gate insulating layer 105, but an attack is also applied to the device isolation layer 104.

The hard mask oxide layer 107 may also be formed of a nitride layer. As described above, the surface and the gate of the semiconductor substrate 103 may be formed during an etching process using phosphoric acid (H ₃ PO ₄ ) to remove the nitride layer. Attacking the conductive film 107 makes it difficult to obtain an effective gate line width, and causes short channel effect defects.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and provides a method of manufacturing a CMOS image sensor in which a defect does not occur during a removal process of a hard mask formed to prevent impurities from being injected into a gate electrode. For that purpose.

According to an aspect of the present invention for achieving the above object, forming a device isolation film on the substrate through an STI process, recessing the device isolation film to form a recess, the device isolation film in the recess Embedding a first passivation layer to protect the gate; sequentially depositing a gate insulating layer, a gate conductive layer, and a hard mask oxide layer on the substrate; forming a gate pattern by selectively etching the gate pattern; Forming a photodiode in the substrate by ion implantation, forming a second passivation layer on the sidewall of the gate pattern to protect the gate insulating layer, and removing the hard mask oxide layer. A method is provided.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3A to 3E are cross-sectional views illustrating a manufacturing process of the CMOS image sensor according to the present invention.

In the manufacturing process of the CMOS image sensor according to the present invention, first, as shown in FIG. 3A, a semiconductor substrate 203 having a p epitaxial layer 202 formed on a p + type substrate 201 is prepared.

In this case, the reason for using the low concentration p epi layer 202 on the high concentration p + type substrate 201 is first, since the low concentration p epi layer 202 is present, the depletion region of the photodiode is large, Can be deeply increased to increase the photodiode's ability to collect photocharges, and secondly, having a high concentration of p + type substrate 201 underneath the p-type epilayer 202, This is because the charge is quickly recombined before the charge spreads to the pixel, thereby reducing the random diffusion of the photocharge, thereby reducing the change in the transfer function of the photocharge.

Subsequently, the pad oxide layer 204 and the pad nitride layer 205 are sequentially deposited on the semiconductor substrate 203 to form first pad layers 204 and 205, and then selectively etched to form the semiconductor substrate 203. Expose

Subsequently, the exposed semiconductor substrate 203 is etched to form a trench, and then an isolation film 206 is formed by filling an insulating film for device isolation in the trench.

Next, as shown in FIG. 3B, the device isolation layer 206 is partially recessed by performing a plasma process.

In this case, the recess process is preferably performed by adding O ₂ gas to the C ₄ F ₈ , C ₅ F ₈ gas.

Subsequently, a first passivation layer 207 for protecting the device isolation layer is deposited on the substrate on which the device isolation layer 206 is recessed.

In this case, the first protective film 207 is preferably a nitride film.

Next, as shown in FIG. 3C, after the chemical mechanical polishing (CMP) process is planarized on the first passivation layer 207, a portion of the first passivation layer 207 and the phosphoric acid are etched with an etching solution. The first pad layers 204 and 205 are removed.

At this time, the first protective film 207 preferably has a thickness of 300 ~ 500 두께.

Subsequently, a gate insulating film 208, a gate conductive film 209, and a hard mask oxide film 210 are sequentially deposited on the substrate, and then a photoresist pattern 211 is formed on the hard mask oxide film 210. .

Subsequently, the hard mask oxide layer 210 and the gate conductive layer 209 are etched using the photoresist pattern 211 as an etch barrier to form a gate electrode.

Subsequently, after forming an ion implantation mask 212 covering a portion of the upper portion of the gate electrode, an ion implantation process is performed to automatically align the edge portion of the gate electrode to form an n-type impurity region 213.

Next, as shown in FIG. 3D, after removing the ion implantation mask 212 and the photoresist pattern 211, the pad oxide layer 214 and the pad nitride layer 215 are formed as a second pad layer on the substrate. ) Is deposited sequentially.

In this case, the pad oxide film 214 may have a thickness of 100 to 200 kPa, and the pad nitride film 215 may have a thickness of 100 to 200 kPa.

Next, as shown in FIG. 3E, the second pad layers 214 and 215 may be etched on the entire surface to protect a portion of both sidewalls of the gate electrode and the gate insulating layer on the gate insulating layer 208. Protective films 214a and 215a are formed.

In this case, the second passivation layers 214a and 215a may be mixed with CHF _x gas and C _x F _y gas to etch the entire surface.

In addition, the second passivation layers 214a and 215a serve to protect the gate insulating layer 208 when the subsequent hard mask oxide layer 210 is removed.

Subsequently, the hard mask oxide film 210 is removed.

At this time, the hard mask oxide film 210 is preferably removed using HF gas.

Next, the second passivation layers 214a and 215a are removed.

The present invention as described above, in order to solve the defects generated during the removal process of the hard mask oxide film 210 formed to prevent the impurities from flowing into the gate electrode during the impurity ion implantation process for forming the photodiode A first passivation layer 207 is formed on the device isolation layer 206 to protect the device isolation layer 206, and a portion of both sidewalls of the gate electrode and the second passivation layer 214a, respectively, on the gate insulating layer 208. 215a is formed to protect the gate insulating film 208.

Therefore, the defect occurring when the hard mask oxide layer 210 is removed is solved to prevent leakage of current and deterioration of device characteristics.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the present invention is to solve the defects generated during the removal process of the hard mask oxide film formed to prevent the impurities from entering the gate electrode during the impurity ion implantation process for forming the photodiode A first passivation layer is formed on the separator to protect the device isolation layer, and a second passivation layer is formed on a portion of both sidewalls of the gate electrode and the gate insulating layer to protect the gate insulating layer.

Therefore, the defect occurring during the removal of the hard mask oxide layer is solved to prevent leakage of current and deterioration of device characteristics.

It is also applicable to 0.15nm technology, which enables continuous miniaturization of the device.

Claims (8)

Forming an isolation layer on the substrate through an STI process; Recessing the device isolation layer to form a recess; Embedding a first passivation layer for protecting the device isolation layer in the recess; Sequentially depositing a gate insulating film, a gate conductive film, and a hard mask oxide film on the substrate, and then selectively etching to form a gate pattern; Forming a photodiode in the substrate by ion implantation using the gate pattern as a mask; Forming a second passivation layer on sidewalls of the gate pattern to protect the gate insulating layer; And Removing the hard mask oxide layer Method of manufacturing a CMOS image sensor comprising a. The method of claim 1, And removing the second passivation layer after removing the hard mask oxide layer. The method of claim 1, And the hard mask oxide film is removed with HF gas. The method of claim 1, The first protective film is a manufacturing method of the CMOS image sensor, characterized in that the nitride film having a thickness of 300 ~ 500Å. The method of claim 1, And the recess part is formed by recessing the device isolation layer by adding O ₂ gas to C ₄ F ₈ and C ₅ F ₈ gas. The method of claim 1, The second protective film is a manufacturing method of the CMOS image sensor, characterized in that the pad oxide film and the pad nitride film is sequentially deposited. The method of claim 6, The pad oxide film has a thickness of 100 ~ 200 kHz, The pad nitride film has a thickness of 100 ~ 200 kHz, The manufacturing method of the CMOS image sensor. The method of claim 1, The second passivation layer is formed by mixing a CHF _x gas and a C _x F _y gas to form a front surface (Blank) etching method of manufacturing a CMOS image sensor.

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