KR20060134563A - Manufacturing method of rram by integrated deposition of insulation film - Google Patents

Abstract

A method for fabricating an RRAM(resistive random access memory) by stacked deposition of an insulation layer is provided to eliminate the necessity of a forming process by forming an insulation thin film and by performing a final high temperature treatment after an insulation thin film has a desired thickness by repeated low-temperature treatments. A substrate is prepared(S401). A barrier layer is deposited on the substrate. A lower electrode is deposited on the resultant structure(S402). An insulation thin film is deposited on the lower electrode(S403). A first heat treatment is performed at a temperature which doesn't cause a phase change in the insulation thin film(S404). The process for depositing the insulation thin film and the first heat treatment are sequentially repeated to form an insulation thin film of a desired thickness. A second heat treatment is performed at a temperature that causes a phase change in the insulation thin film(S406). An upper electrode is deposited on the insulation thin film(S407).

Description

Manufacturing Method of Resistive Memory Device by Lamination of Insulator Film {MANUFACTURING METHOD OF RRAM BY INTEGRATED DEPOSITION OF INSULATION FILM}

1 is a graph for explaining the principle of operation of a resistive memory using high and low switching of the resistance in an insulator;

2 is a flow chart for explaining a conventional manufacturing method of depositing an insulator to form a resistive memory.

FIG. 3 is a graph showing switching characteristics of a MIM resistive memory device having a Pt-TiO ₂ -Pt structure manufactured using the conventional manufacturing method described with reference to FIG. 2.

4 is a flowchart illustrating a method of manufacturing a resistive memory element according to the present invention.

5 is a graph showing the switching characteristics of the MIM resistive memory device manufactured in the embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a resistive memory device. In particular, a method of manufacturing a resistive memory device is unnecessary by forming an insulator thin film and stacking the insulator thin film by repeating heat treatment at low temperature a plurality of times, thereby greatly reducing the operation voltage. It is about.

Recently, due to the development of portable mobile devices, the requirements for the memory used therein are greatly increased.

When volatile memory is used as the memory of the mobile device, when the mobile device is in the standby state, continuous refresh is necessary to maintain the information stored in the memory. This refresh eventually leads to power consumption of the mobile device, which shortens the life of the battery and generates heat, thereby shortening the life of other devices.

However, unlike the volatile memory, since the nonvolatile memory does not require refreshing even in the standby state, it is not necessary to supply power to the memory, thereby reducing power consumption. Nonvolatile memories include flash memory, ferroelectric memory, phase change RAM, and the like.

In particular, a resistive memory using a change in resistance of an insulator has excellent characteristics such as high speed, large capacity, and low power consumption, and is a nonvolatile memory that has been actively studied in recent years. It has a MIM capacitor structure consisting of Metal-Insulator-Metal, and stores information through the high and low change of resistance that changes the resistance of the insulator from high to low depending on the voltage. Resistive Random Access Memory.

FIG. 1 is a graph illustrating a basic operation principle of a resistance memory using high and low switching of resistance in an insulator.

First, in a resistive memory device having a MIM capacitor structure in which an insulator is sandwiched between metal electrodes, a voltage is applied to the insulator to cause a soft breakdown of the insulating film at a specific voltage (V _f ) so that a current flows well through the insulating film. Create (Forming process).

When the voltage is applied again in this state, the current initially increases according to the voltage, but the current decreases above a specific voltage (V _r : Reset voltage) (Differential Negative Resistance: DNR).

If the voltage is continuously applied even after the DNR phenomenon occurs, the current gradually increases, and then a breakdown occurs in which the current rapidly increases at a specific voltage (V _s : Set voltage). At this time, if the voltage is applied in the middle between V _r and V _s, the insulator is changed to a high resistance state (reset process).

If the voltage is applied again after the reset to induce a soft breakdown at V _s , the insulator changes to a low resistance state again (Set process).

In the resistive memory that has been formed as described above, a low resistance state and a high resistance state can be formed through a reset process and a set process, thereby forming a binary information system required for a memory device. In addition, forming is necessary to make a resistive memory, and a reset voltage (V _r ) and a set voltage (V _s ), which are switching voltages that enable switching, are factors that determine an operating voltage of the resistive memory.

By the way, one of the factors that determine the forming voltage, the reset voltage, the set voltage, the ratio of the high resistance and the low resistance, etc., which determine the characteristics of the resistance memory, is the characteristic of the insulator. Binary metal oxide of the TiO _2, NiO, etc. as the insulation material to be used (Binary Metal Oxide) _{or, BaTiO 3, SrTiO 3, LaMnO} 3, SrMnO 3, PrTiO 3, PbZrO 3 , etc. of perop Sky agent (Perovskite) structure perop of Materials such as sky-based oxides, chalcogenide series using GeSbTe (GST), and materials having macromagnetic resistance properties such as PrCaMnO ₃ (PCMO) have been studied.

In addition, as a method of depositing these insulator materials, physical vapor deposition by sputtering, evaporation, etc., atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. There is a chemical vapor deposition method. The chemical vapor deposition method has a problem in that the thin film is excellent, but the deposition rate is slow and it must be deposited at a high temperature. Currently, an insulator is deposited to a thickness of several tens of nm by a physical vapor deposition method to make a resistive memory.

2 is a flowchart illustrating a conventional manufacturing method of forming an insulator memory by depositing an insulator.

According to this, in the conventional manufacturing method, a step of first preparing a semiconductor substrate (S201), depositing a metal lower electrode on the semiconductor substrate (S202), by using an insulator target at room temperature using an insulator thin film by a conventional thin film deposition method Deposition once (S203) to a desired thickness, a high temperature heat treatment step (S204) to the extent that the phase change of the insulator occurs, and the step of depositing the upper electrode (S205).

For example, in the case of using TiO ₂ as a material of an insulator thin film, a lower electrode is deposited on a substrate, and the TiO ₂ thin film is formed by depositing on the lower electrode and then heat-treated at a high temperature of 800 ° C., thereby The electrode is deposited to fabricate a resistive memory device. 3 is a graph showing switching characteristics of a MIM resistive memory device having a Pt-TiO ₂ -Pt structure manufactured using such a conventional manufacturing method.

In particular, US Patent Nos. 6,664,117 (registered on December 16, 2003), 6,774,054 (registered on April 10, 2003), and US Patent Publication No. 2004/0180507 (published on September 16, 2004), which are known in the art, have a large magnetoresistance characteristic as an insulator. A technique of manufacturing a resistive memory by forming an insulator by repeating the step of forming a thin film layer of PCMO composition on a semiconductor substrate and then annealing it at a high temperature is disclosed.

However, as described above, all of the related arts have a problem that they must go through a forming process in order to operate as a resistive memory, which is an obstacle to practical use.

Accordingly, the present invention was devised to solve the above problems, and an object of the present invention is to repeat the formation of the insulator thin film and the heat treatment at low temperature a plurality of times, thereby stacking the insulator thin film so that a normal switching operation can be performed without the forming process. To provide a resistive memory device having a low operating voltage.

In order to achieve the above object, a method of manufacturing a resistive memory device according to the present invention comprises the steps of first preparing a substrate, depositing a lower electrode on the substrate, and depositing an insulator thin film on the lower electrode And a heat treatment at a temperature in a range in which phase change does not occur in the insulator thin film as a first heat treatment step, and repeatedly depositing the insulator thin film and the first heat treatment step a plurality of times to obtain an insulator thin film having a desired thickness. Laminating, heat treating at a temperature in a range in which a phase change occurs in the insulator thin film as a second heat treatment step, and depositing an upper electrode on the insulator thin film. In this case, the method may further include depositing a barrier layer on the substrate between preparing the substrate and depositing the lower electrode.

In addition, the first heat treatment step is carried out within a temperature range of more than the deposition temperature of the insulator thin film below the temperature of the phase change.

In addition, the second heat treatment step is carried out at a temperature of 1000 ° C or less.

In addition, at least one of the first heat treatment step and the second heat treatment step is carried out in at least one or more atmospheres such as nitrogen, oxygen, argon or vacuum.

Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

4 is a flowchart for explaining a method of manufacturing a resistive memory device according to the present invention.

First, a method of manufacturing a resistive memory device according to the present invention includes preparing a semiconductor substrate (S401), depositing a lower electrode on the semiconductor substrate (S402), and forming an insulator thin film on the lower electrode. The step (S403), the step (S404) of performing a heat treatment at a low temperature within a temperature range such that no phase change occurs in the insulator thin film, the step of depositing the insulator thin film (S403) and the low temperature heat treatment step (S404) sequentially Repeating a plurality of times to laminate the insulator thin film of the desired thickness (S403 ~ S405), the step of heat treatment at a high temperature within the temperature range of the phase change of the insulator thin film (S406), and the step of depositing the upper electrode (S407) It consists of.

To describe this in detail for each process, first, the semiconductor substrate is a group IV semiconductor such as Si, SiO ₂ , Poly-Si, Ge, SiGe, Strained Ge, Strained SiGe, Silicon on Insulator (SOI), SiGe On Insulator (GOI), etc. It is prepared as a substrate (S401).

In addition, a lower electrode is formed on the semiconductor substrate (S402), wherein the lower electrode is a metal-based such as Pt, Ru, Al, Ir, or a metal nitride film such as TaN, TiN, HfN, or the like. Or at least any one or more laminated structures or alloy structures among metal oxides such as RuO and SrRuO ₃ . In addition, a barrier layer may be formed between the semiconductor substrate and the lower electrode. The barrier layer may be formed of at least one of Ta, TaN, Ta ₂ O ₅ , Ti, TiN, TiAlN, TaAlN, TiSiN, and TiAl. It is preferable that it consists of.

In addition, an insulator thin film is deposited on the lower electrode (S403), and the insulator thin film is formed of TiO ₂ , NiO, HfO ₂ , SiO ₂ , ZrO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O _5. , combine the Nb ₂ O _5, such as binary metal oxides based on, or _{BaTiO 3, SrTiO 3, LaMnO 3} , SrMnO 3, PrTiO 3, PbZrO 3, KNbO 3, KTaO 3 , or two or more, such as BaSrTiO ₃ of these, or Cr Perovskite-based oxides doped with other metals, such as -doped SrTi (Zr) O ₃ , or chalcogenides containing GeSbTe (GST), or materials with macromagnetic resistance properties such as PrCaMnO ₃ and Cr-doped PrCaMnO At least one or more laminated thin films selected from the above are used. In particular, the binary metal oxide-based material has an advantage that the composition of the thin film can be easily achieved.

After the insulator thin film is formed as described above, low temperature heat treatment is performed in a temperature range where the amorphous phase of the insulator thin film does not change (S404). The temperature depends on the nature of the insulator used. That is, the temperature range of the low temperature heat treatment is preferably set higher than the deposition temperature and smaller than the temperature at which the amorphous phase of the insulator thin film is changed in consideration of the insulating film forming process (S403) by deposition. In addition, the low temperature heat treatment is preferably performed in at least one or more atmospheres such as nitrogen, oxygen, argon or vacuum. In particular, in the case where the insulator is formed of an oxide film, oxygen may be injected into the insulator thin film when heat treatment is performed in an oxygen atmosphere to increase the oxygen content in the thin film. Further, the low temperature heat treatment time is preferably about 10 minutes to 60 minutes in the case of furnace heat treatment, and about 30 seconds to 5 minutes in the case of RTP (Rapid Thermal Process).

Then, the insulator thin film is stacked by sequentially repeating the insulator thin film forming process (S403) and the low temperature heat treatment step (S404) until the insulator thin film has a desired thickness. The number of repetitions is at least two or more times necessary for forming the desired thickness, for example, preferably two to ten times or less.

Then, the high temperature heat treatment is performed at a temperature at which the prepared insulator thin film can be changed from an amorphous state to a crystalline state (S406). At this time, the high temperature heat treatment is preferably performed in at least one or more atmospheres such as nitrogen, oxygen, argon or vacuum. In addition, the temperature of the high temperature heat treatment is preferably made at 1000 ℃ or less in consideration of the thermal stability of the device, more preferably 500 ℃ to 1000 ℃ or less. In addition, the high temperature heat treatment time is preferably about 10 minutes to 3 hours in the case of furnace heat treatment, and about 30 seconds to 5 minutes in the case of RTP.

In operation S407, an upper electrode is deposited on an upper surface of the insulator thin film formed to a desired thickness. At this time, the upper electrode, like the lower electrode, in a metal series such as Pt, Ru, Al, Ir, or a metal nitride layer such as TaN, TiN, HfN, or a metal oxide such as RuO, SrRuO ₃ or the like. It is preferable to have at least one laminated structure or alloy structure, and may have the same or different composition as the lower electrode.

In addition, the process of patterning the resistive memory device to a desired size may be performed using a wet or dry etching process before the lower electrode forming process (S402) or after the upper electrode forming process (S407).

In addition, the upper electrode forming step (S407) may be performed before the high temperature heat treatment step (S406).

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail. However, the embodiments described below are provided to help the overall understanding of the present invention, and the present invention is not limited to the above embodiments.

Example

In this embodiment, a MIM resistive memory device having a Pt-TiO ₂ -Pt structure is manufactured.

First, a Si substrate was prepared and a lower electrode was deposited on the upper portion of Pt, and an insulator thin film having a TiO ₂ composition, which is a binary metal oxide, was formed on the lower electrode. In this case, in addition to the TiO ₂ composition, other binary metal oxides such as NiO, HfO ₂ , SiO ₂ , ZrO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , and Nb ₂ O ₅ may be selected. Do. The TiO ₂ thin film was deposited to a thickness of 10 nm in a sputtering manner at room temperature using a TiO ₂ target. Then, it was subjected to low temperature heat treatment for 10 minutes to 1 hour in an oxygen atmosphere of 100 ° C to 700 ° C. Then, the formation of the TiO ₂ thin film deposition (film thickness 10nm) and the final TiO ₂ thin film of 40nm thickness as in the low temperature heat treatment step performed three times more repetitions of the TiO ₂ thin film performed prior to the desired thickness to be produced It was. Then, this was a high temperature heat treatment for 30 seconds to 5 minutes in a rapid thermal annealing (RTA) method in a nitrogen atmosphere of 700 ℃ to 1000 ℃. In addition, in addition to the high temperature heat treatment by the RTA method, it is also possible to perform a high temperature heat treatment for 10 minutes to 3 hours in a nitrogen atmosphere of 700 ℃ to 1000 ℃ using an electric furnace. Then, a lower electrode was deposited on the upper portion of Pt. However, the forming process was not performed.

5 shows switching characteristics of the MIM resistive memory device manufactured in the embodiment of the present invention.

From this, it can be seen that the resistive memory device according to the present embodiment has already formed a low resistance state even though the forming process has not been performed. In addition, the DNR phenomenon occurs in the low resistance state, and is changed to the high resistance state through the reset process. In addition, the low resistance state may be formed again by the set process, thereby causing a resistance switching phenomenon.

Table 1 compares the switching characteristics of the resistive memory device according to the present embodiment and the resistive memory device according to the prior art. In this case, the resistive memory device according to the related art was manufactured through the steps S201 to S205 of FIG. 2 described above, and the same TiO ₂ was used as the insulator film as in the present embodiment.

Table 1 Operation characteristics of the resistive memory device according to the prior art and this embodiment

Prior art Example Forming process need Unnecessary Reset voltage value (V) 3.4 0.5 Set voltage value (V) 5.1 1.6

That is, according to the prior art, the switching phenomenon of the resistance occurs only through the forming process, in the present embodiment, it is possible to cause the switching phenomenon of the resistance without the forming process.

In addition, as the operating voltage characteristic, the reset voltage and the set voltage are 3.4V and 5.1V, respectively, in the prior art, whereas in this embodiment, the switching phenomenon occurs at a voltage much lower than the prior art, as 0.5V and 1.6V, respectively. This makes it possible to lower the operating voltage of the resistive memory in the present embodiment than in the prior art.

As described above, in the method of manufacturing the resistive memory device by lamination of the insulating film according to the present invention, in forming the insulator thin film in the resistive memory device manufacturing process, the insulator thin film is repeatedly formed and the low temperature heat treatment is repeated to produce the desired thickness. After the final high temperature heat treatment, the switching phenomenon of the resistor is induced even if the forming process, which is necessary for driving the conventional resistive memory device, is omitted, thereby driving the resistive memory device.

In addition, compared with the conventional method, a significantly lower operating voltage and a higher resistance ratio can be obtained, thereby greatly improving the operating characteristics of the resistive memory device.

In addition, the preferred embodiment of the present invention is disclosed for the purpose of illustration, anyone of ordinary skill in the art will be possible to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications, changes, Additions and the like should be considered to be within the scope of the claims.

Claims (20)

Preparing a substrate; Depositing a lower electrode on the substrate; Depositing an insulator thin film on the lower electrode; Heat treatment at a temperature in a range where phase change does not occur in the insulator thin film as a first heat treatment step; Depositing the insulator thin film and repeating the first heat treatment step a plurality of times in order to stack an insulator thin film having a desired thickness; Heat treatment at a temperature in a range in which a phase change occurs in the insulator thin film as a second heat treatment step; And depositing an upper electrode on the insulator thin film. The method of claim 1, And depositing a barrier layer on the substrate between preparing the substrate and depositing the lower electrode. The method according to claim 1 or 2, The insulator thin film may be formed of TiO ₂ , NiO, HfO ₂ , SiO ₂ , ZrO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , Nb ₂ O ₅ , or a binary metal oxide-based, BaTiO ₃ , Chalcogenides comprising SrTiO ₃ , LaMnO ₃ , SrMnO ₃ , PrTiO ₃ , PbZrO ₃ , KNbO ₃ , KTaO ₃ or a perovskite-based oxide that combines at least two or more of these metals or is doped with another metal, or GeSbTe (GST) A method of manufacturing a resistive memory device comprising at least one multilayer thin film selected from a series or a macromagnetic resistance material containing PrCaMnO ₃ or Cr-doped PrCaMnO. The method according to claim 1 or 2, The preparing of the substrate may include preparing the substrate by at least one selected from the group consisting of Si, SiO ₂ , Poly-Si, Ge, SiGe, Strained Ge, Strained SiGe, SOI, and GOI. A method of manufacturing a resistive memory element. The method according to claim 1 or 2, At least one of the first heat treatment step and the second heat treatment step is carried out in at least one or more atmospheres of nitrogen, oxygen, argon or vacuum. The method according to claim 1 or 2, The lower electrode and the upper electrode may include at least one of a metal series including Pt, Ru, Al, and Ir, a metal nitride film series including TaN, TiN, and HfN, or a metal oxide including RuO and SrRuO ₃ . A method of manufacturing a resistive memory device, characterized in that the structure or alloy structure. The method of claim 2, The barrier layer is made of at least one of Ta, TaN, Ta ₂ O ₅ , Ti, TiN, TiAlN, TaAlN, TiSiN, TiAl. The method according to claim 1 or 2, The first heat treatment step is a method of manufacturing a resistive memory device, characterized in that the heat treatment within the temperature range of the deposition temperature of the insulator thin film below the temperature of the phase change. The method of claim 8, The first heat treatment step is a method of manufacturing a resistive memory device, characterized in that carried out in a temperature range of 100 ℃ to 700 ℃. The method of claim 9, The first heat treatment step is carried out for 10 minutes to 1 hour in the case of furnace heat treatment, and 30 seconds to 5 minutes in the case of RTP. The method according to claim 1 or 2, The second heat treatment step is a method of manufacturing a resistive memory device, characterized in that carried out in a temperature range of 500 ℃ to 1000 ℃. The method of claim 11, The second heat treatment step is performed for 10 minutes to 3 hours in the case of furnace heat treatment, and 30 seconds to 5 minutes in the case of RTP. The method according to claim 1 or 2, The second heat treatment step is performed after the step of depositing the upper electrode. The method according to claim 1 or 2, The stacking of the insulator thin film having a desired thickness may include depositing the insulator thin film and performing a first heat treatment step twice to ten times. The method according to claim 1 or 2, The patterning of the resistive memory device to be manufactured to a desired size is further performed before the depositing the lower electrode or after the depositing the upper electrode. Preparing a substrate comprising at least one selected from the group consisting of Si, SiO ₂ , Poly-Si, Ge, SiGe, Strained Ge, Strained SiGe, SOI, GOI; On the substrate, at least one layer or alloy structure of a metal series including Pt, Ru, Al, Ir, or a metal nitride layer including TaN, TiN, HfN, or a metal oxide including RuO, SrRuO ₃ . Depositing a lower electrode; At least one of binary metal oxides including TiO ₂ , NiO, HfO ₂ , SiO ₂ , ZrO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , and Nb ₂ O ₅ on the lower electrode. Depositing an insulator thin film to a predetermined thickness; A first heat treatment step of heat treatment at 100 ° C. to 700 ° C. for 10 minutes to 1 hour or at 100 ° C. to 700 ° C. for 30 seconds to 5 minutes; Depositing the insulator thin film to a predetermined thickness and stacking an insulator thin film having a desired thickness by repeating the first heat treatment step a plurality of times; A second heat treatment step of heat-treating with RTP at 700 ° C. to 1000 ° C. for 30 seconds to 5 minutes or furnace heat treatment at 700 ° C. to 1000 ° C. for 10 minutes to 3 hours; Laminated structure or alloy of at least one of metal based on Pt, Ru, Al, Ir, or metal nitride based on TaN, TiN, HfN, or metal oxide including RuO, SrRuO ₃ on the insulator thin film And depositing an upper electrode having a structure. The method of claim 16, The first heat treatment step is a method of manufacturing a resistive memory device, characterized in that carried out in an oxygen atmosphere. The method according to claim 16 or 17, The second heat treatment step is a method of manufacturing a resistive memory device, characterized in that carried out in a nitrogen atmosphere. 18. A resistive memory device made by the method of any one of claims 1, 2, 16, and 17. The method of claim 19, The resistive memory device has a reset voltage of 0.5V and a set voltage of 1.6V.

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