KR20060133827A - Method for fabricating thin film transistor substrate - Google Patents

Abstract

A method for manufacturing a thin film transistor substrate is provided to minimize the protrusions of an ohmic contact pattern and a semiconductor pattern, thereby improving the aperture ratio, by substantially aligning the lateral portions of the ohmic contact pattern and the semiconductor pattern with the end of an upper conductive layer. A gate insulating layer(30), a semiconductor layer, an ohmic contact layer, and a conductive layer are sequentially deposited on a substrate having a gate wire. A photoresist pattern(112) is formed on the conductive layer. The conductive layer is pattern-etched to expose the ohmic contact layer using the photoresist pattern. The ohmic contact layer and the semiconductor layer are pattern-etched to form an ohmic contact pattern(54) and a semiconductor pattern(44) using the photoresist pattern. The photoresist pattern is downsized to expose the lateral portions of the ohmic contact pattern and the semiconductor pattern. The lateral portions of the ohmic contact pattern and the semiconductor pattern are etched, thereby substantially aligning the outside profiles of the ohmic contact pattern and the semiconductor pattern with the outside profile of the patterned conductive layer(64). The patterned conductive layer and ohmic contact pattern are pattern-etched to expose a channel portion of the semiconductor pattern.

Description

Method for fabricating thin film transistor substrate

1A is a layout view of a thin film transistor substrate manufactured by a manufacturing method according to an embodiment of the present invention.

FIG. 1B is a cross-sectional view taken along the line BB ′ of FIG. 1A,

2A, 4A, and 12A are layout views sequentially illustrating a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention.

2B and 3 are cross-sectional views of the process steps taken along the line BB ′ of FIG. 2A.

4B to 11 are cross-sectional views of the process steps taken along the line BB ′ of FIG. 4A.

FIG. 12B is a cross-sectional view taken along the line BB ′ of FIG. 12A.

<Description of the symbols for the main parts of the drawings>

10: insulating substrate 22: gate line

24: gate end 26: gate electrode

27: sustain electrode 28: sustain electrode line

30: gate insulating film 40: semiconductor layer

55, 56: ohmic contact layer 62: data line

65 source electrode 66 drain electrode

67: drain electrode extension 68: data end

70: protective film 82: pixel electrode

The present invention relates to a method for manufacturing a thin film transistor substrate, and more particularly, to a method for manufacturing a thin film transistor substrate capable of increasing the aperture ratio.

Liquid crystal display is one of the most widely used flat panel displays. It consists of two substrates on which electrodes are formed and a liquid crystal layer interposed between them. The display device is applied to rearrange the liquid crystal molecules of the liquid crystal layer to control the amount of light transmitted.

Among the liquid crystal display devices, a field generating electrode is provided on two substrates. Among them, a plurality of pixel electrodes are arranged in a matrix form on one substrate, and one common electrode covers the entire surface of the substrate on another substrate. In such a liquid crystal display, an image is displayed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal element for switching the voltage applied to the pixel electrode, is connected to each pixel electrode and a gate line and a voltage to be applied to the pixel electrode to transmit a signal for controlling the thin film transistor. A data line for transmitting X is formed on the substrate.

As a method for manufacturing a thin film transistor substrate of such a liquid crystal display device, there are five mask processes using five masks and a four mask process for patterning a semiconductor layer and data wiring using one mask, and dual process efficiency. The trend is to favor this high four-sheet mask process.

In the four-mask process, the data lines of the channel portion and the other portions are patterned by separate etching processes. The etching process of the data line is performed by wet etching using an etchant, and the data line is exposed to the etchant twice. Wet etching by the etchant may cause overetching of the bottom of the etching mask. As described above, when the etching process is performed twice, the overetching phenomenon may be more pronounced. When the data line is over-etched, a portion of the lower ohmic contact layer and the semiconductor pattern may protrude. The ohmic contact layer / semiconductor pattern protrusion may increase the opacity of the thin film transistor substrate, thereby reducing the aperture ratio and the waterfall noise. It may cause malfunction.

Accordingly, there is a need for a method of manufacturing a thin film transistor substrate capable of minimizing the resistive contact layer / semiconductor pattern protrusion to secure an aperture ratio and improve a waterfall noise defect.

An object of the present invention is to provide a method for manufacturing a thin film transistor substrate that can increase the aperture ratio.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate, the method comprising sequentially stacking a gate insulating film, a semiconductor layer, an ohmic contact layer, and a conductive layer on a substrate on which a gate wiring is formed; The resistive contact layer is exposed by etching the conductive layer using a photoresist pattern in which a portion of the semiconductor layer corresponding to the channel portion of the semiconductor layer is formed to be lower than a portion in which other data lines are formed. Forming a resistive contact layer / semiconductor pattern by etching the resistive contact layer and the lower semiconductor layer exposed using the photoresist pattern, and exposing the conductive layer on the channel portion of the semiconductor layer. Downsizing the photoresist pattern so that the sides of the ohmic contact layer / semiconductor pattern Partially exposing, etching side portions of the exposed ohmic contact layer / semiconductor pattern to align the outer profile of the ohmic contact layer / semiconductor pattern to substantially the outer profile of the upper conductive layer and the channel portion. Etching the conductive layer and the ohmic contact layer thereon to expose the channel portion of the semiconductor layer.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention will be described with reference to the accompanying drawings.

First, a unit pixel structure of a thin film transistor substrate manufactured by a manufacturing method according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1A and 1B. 1A is a layout view of a thin film transistor substrate manufactured by a manufacturing method according to an exemplary embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line BB ′ of FIG. 1A.

A plurality of gate wirings for transmitting a gate signal are formed on the insulating substrate 10. The gate wires 22, 24, 26, 27, and 28 are connected to the ends of the gate line 22 and the gate line 22 extending in the horizontal direction, and receive gate signals from the outside and transfer them to the gate line. (24), the gate electrode 26 of the thin film transistor which is connected to the gate line 22 in the form of a projection, and the sustain electrode 27 and the sustain electrode line 28 formed in parallel with the gate line 22. . The storage electrode line 28 extends in the horizontal direction across the pixel region and is connected to the storage electrode 27 having a wider width than the storage electrode line 28. The storage electrode 27 overlaps with the drain electrode extension 67 connected to the pixel electrode 82, which will be described later, to form a storage capacitor that improves the charge storage capability of the pixel. Such shapes and arrangements of the storage electrode 27 and the storage electrode line 28 may be modified in various forms, and may not be formed when the storage capacitance generated by the overlap between the pixel electrode 82 and the gate line 22 is sufficient. It may not.

The gate wirings 22, 24, 26, 27, and 28 are made of molybdenum layers 221, 241, 261 and 271 made of molybdenum (Mo) or molybdenum alloy, aluminum layers 222 and 242 made of aluminum (Al) or an aluminum alloy. , 262, 272 and molybdenum layers 223, 243, 263, and 273 made of molybdenum (Mo) or molybdenum alloy. Although not shown directly in the figure, the storage electrode lines 28 also have the same triple film structure as the other gate wirings 22, 24, 26, and 27. The sustain electrode line 28 is also included in the gate wiring of the triple film structure demonstrated below.

A gate insulating film 30 made of silicon nitride (SiNx) or the like is formed on the substrate 10 and the gate wirings 22, 24, 26, 27, and 28.

On the gate insulating film 30, semiconductor patterns 42, 44 and 48 made of semiconductors such as hydrogenated amorphous silicon or polycrystalline silicon are formed, and n-type impurities such as silicide are formed on the semiconductor patterns 42, 44 and 48. Resistive contact layers 52, 55, 56 and 58 made of a material such as highly doped n + hydrogenated amorphous silicon are formed.

Data wires 62, 65, 66, 67, and 68 are formed on the ohmic contacts 52, 54, 55, 56, and 58. As shown in FIG. The data lines 62, 65, 66, 67, and 68 are formed in the vertical direction and cross the gate line 22 to define the pixel and the branch of the data line 62 and the data line 62 to define a pixel. Is connected to one end of the source electrode 65 and the data line 62 extending to an upper portion of the data source, separated from the data end 68 and the source electrode 65 to which an image signal from the outside is applied, and the gate electrode 26. Or a wide area extending from the drain electrode 66 and the drain electrode 66 formed on the ohmic contact layer 56 opposite to the source electrode 65 with respect to the channel portion of the thin film transistor and overlapping the storage electrode 27. A drain electrode extension 67 of the area.

The data lines 62, 65, 66, 67, and 68 may be formed of a molybdenum layer 621, 651, 661, made of molybdenum (Mo) or a molybdenum alloy like the gate lines 22, 24, 26, 27, and 28 described above. 671, 681, aluminum layers 622, 652, 662, 672, 682 made of aluminum (Al) or aluminum alloys, and molybdenum layers (623, 653, 663, 673, 683) made of molybdenum (Mo) or molybdenum alloys. It is formed of a triple layer of.

The source electrode 65 overlaps at least a portion of the semiconductor layer 44, and the drain electrode 66 faces the source electrode 65 around the gate electrode 26 and at least partially overlaps the semiconductor layer 44. do.

The drain electrode extension 67 is formed to overlap the storage electrode 27, and a storage capacitor is formed with the storage electrode 27 and the gate insulating layer 30 interposed therebetween. When the sustain electrode 27 is not formed, the drain electrode extension 27 is also not formed.

The ohmic contacts 52, 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42, 44, and 48 at the bottom thereof and the data lines 62, 65, 66, 67, and 68 at the top thereof. And has the same shape as the data lines 62, 65, 66, 67, and 68.

Meanwhile, except for the channel portion C of the thin film transistor, the semiconductor patterns 42, 44, and 48 may have upper ohmic contact layers 52, 55, 56, and 58 and data lines 62, 65, 66, 67, and 68. The resistive contact layers 52, 55, 56, and 58 form the resistive contact layer / semiconductor pattern together with the semiconductor patterns 42, 44, and 48. That is, the source electrode 65 and the drain electrode 66 are separated from the channel portion C of the thin film transistor, and the ohmic contact layer 55 under the source electrode 65 and the ohmic contact layer under the drain electrode 66 are separated. Although 56 is also separated, the thin film transistor semiconductor pattern 44 is connected here without being disconnected to form the channel portion C of the thin film transistor. In addition, the outer profile of the ohmic contact layer / semiconductor pattern except for the channel portion C is substantially aligned with the outer profile of the upper data lines 62, 65, 66, 67, and 68 except for the channel portion C. . That is, the outer profile of the ohmic contact layer / semiconductor pattern and the outer profile of the upper data lines 62, 65, 66, 67, and 68 are aligned substantially in the same plane with no step or only fine step. .

The passivation layer 70 is formed on the data wires 62, 65, 66, 67, and 68 and the semiconductor pattern 44 which is not covered by the data lines 62. The protective film 70 may be formed of, for example, a-Si: C: O, a-Si: organic material having excellent planarization characteristics and having photosensitivity, and plasma enhanced chemical vapor deposition (PECVD). Low dielectric constant insulating materials such as O: F, or silicon nitride (SiNx), which is an inorganic material. In addition, when the protective film 70 is formed of an organic material, in order to prevent the organic material of the protective film 70 from contacting a portion where the semiconductor pattern 44 between the source electrode 65 and the drain electrode 66 is exposed. In addition, an insulating film (not shown) made of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) may be further formed below the organic film.

In the passivation layer 70, contact holes 77 and 78 exposing the drain electrode extension 67 and the data line end 68 are formed, respectively, and the passivation line 24 is formed in the passivation layer 70 and the gate insulating layer 30. ), A contact hole 74 is formed.

In addition, an auxiliary gate end 84 and an auxiliary data end 88 connected to the gate end 24 and the data end 68 are formed on the passivation layer 70 through the contact holes 74 and 78, respectively. The pixel electrode 82, the auxiliary gate, and the data ends 86 and 88 are made of ITO or IZO.

Hereinafter, a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1A and 1B and FIGS. 2A to 11B.

First, as shown in FIGS. 2A and 2B, sputtering molybdenum layers 221, 241, 261 and 271, aluminum layers 222, 242, 262 and 272 and molybdenum layers 223, 243, 263 and 273 ( The gate triple layers 22, 24, 26, 27, and 28 sequentially stacked are formed by a method such as sputtering.

Subsequently, the gate triple layer 22, 24, 26, 27, 28 is photo-etched. The etching process is a wet etching.

As a result, as shown in FIGS. 2A and 2B, the gate wirings 22 and 24 including the gate line 22, the gate electrode 26, the gate end 24, the storage electrode 27, and the storage electrode line 28 are formed. 26, 27, 28) are formed.

Subsequently, as shown in FIG. 3, the gate insulating film 30 made of silicon nitride (SiNx) or the like, the semiconductor layer 40 made of intrinsic amorphous silicon, and the ohmic contact layer 50 made of doped amorphous silicon are chemically vapor deposited. And the like are continuously deposited to a thickness of, for example, 1,500 kPa to 5,000 kPa, 500 kPa to 2,000 kPa, 300 kPa to 600 kPa, respectively.

Subsequently, a data triple film 60 in which a molybdenum layer 601, an aluminum layer 602, and a molybdenum layer 603 are sequentially stacked is formed on the ohmic contact layer 50 by a method such as sputtering.

Subsequently, a photosensitive film 110 is coated on the data triple layer 60.

4A to 9, the photoresist film 110 is irradiated with light through a mask and then developed to form photoresist patterns 112 and 114 as illustrated in FIG. 4B. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is a portion where the data line is to be formed (hereinafter, ' The thickness is smaller than the second part 112 positioned in the data wiring part, and the photoresist film of the other part except the channel part C and the data wiring part is removed. In this case, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion may vary depending on the process conditions in the etching process, which will be described later. The thickness of the first portion 114 may be less than 1/2 of the thickness of the second portion 112 and may be 4,000 kPa or less.

As such, there may be various methods of varying the thickness of the photoresist film according to the position. In order to control the amount of light transmission, a mask having a slit or grid pattern is formed or a mask having a semitransparent film region may be used. use.

In this case, it is preferable that the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits, is smaller than the resolution of the exposure machine used for exposure. The thin film may have a thin film or a thin film having a different thickness.

When the light is irradiated to the photoresist film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, but at the part where the slit pattern or the translucent film is formed, the polymer is not completely decomposed because the amount of light is small. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left in the center portion where the light is not irradiated than the portion where the light is not irradiated at all. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It can also be formed by making a part of the photosensitive film flow to the part which is made low and the photosensitive film does not remain.

Subsequently, etching is performed on the data triple layer 60 including the molybdenum layer 603, the aluminum layer 602, and the molybdenum layer 601 using the photoresist patterns 112 and 114 as an etching mask. The etching process of the data triple layer 60 is performed by wet etching. As the etchant used for such wet etching, for example, H ₂ PO ₃ , CH ₃ COOH, HNO ₃ , H ₂ O, etc. may be used alone or in combination.

In this way, as shown in FIG. 5, only the triple layer patterns 62, 64, 67, and 68 of the channel portion C and the data wiring portion remain, and the triple layer of other portions except the channel portion C and the data wiring portion ( 60 are all removed to reveal the underlying ohmic contact layer 50. The triple layer patterns 62, 64, 67, and 68 are formed of the data line (62, 65, 66, 67, and 68 of FIG. 1B) except that the source and drain electrodes 65 and 66 are connected without separation. Same as form At this time, the side portions of the triple layer patterns 62, 64, 67, and 68 of the remaining channel portion C and the data wiring portion are overetched to some extent by the etchant, and the width thereof is narrowed, so as to be narrower than the side portions of the upper photoresist pattern 112. It will show the shape, that is, the critical dimension skew.

Next, as shown in FIG. 6, the exposed resistive contact layer 50 and the semiconductor layer 40 of the other portions except the channel portion C and the data wiring portion using the photoresist patterns 112 and 114 as etching masks. ) Are simultaneously removed by dry etching to form an ohmic contact layer / semiconductor pattern. The etching may be performed under the condition that the gate insulating film 30 is not etched while the ohmic contact layer 50 made of doped amorphous silicon and the semiconductor layer 40 made of intrinsic amorphous silicon are simultaneously etched. As an etching gas, for example, a gas including Cl ₂ and / or SF ₆ may be used, but is not limited thereto. Since the dry etching hardly causes overetching unlike wet etching, the ohmic contact layer / semiconductor pattern is formed to be substantially aligned with the sides of the photoresist pattern 112. That is, in this step, the width of the photoresist pattern 112 and the width of the ohmic contact layer / semiconductor pattern are substantially the same, and are formed relatively larger than the width of the triple layer patterns 62, 64, 67, and 68.

Subsequently, as shown in FIG. 7, the photoresist patterns 112 and 114 are downsized to remove the photoresist region 114 corresponding to the channel portion C, and the source / channel on the channel portion C is removed. The drain triple layer pattern 64 is exposed. Downsizing here may be performed by etch back. Furthermore, downsizing may be performed by dry etching. In this case, as the etching gas, for example, O ₂ gas may be used alone or mixed with SF ₆ , but is not limited thereto. In this case, since the second portion 112 of the photoresist pattern is also etched, the thickness becomes thinner, and the side portion of the second portion 112 of the photoresist pattern is also etched, thereby decreasing the width as a whole. The side portion of the second portion 112 of the photoresist layer pattern is narrowed to the same position as the side portion of the lower triple layer pattern 62, 64, 67, 68, which is narrowed by overetching. Accordingly, as shown in FIG. 7, the resistive contact layer / where the side portions of the resistive contact layer / semiconductor pattern are part not partially covered by the photoresist pattern 112 and the triple layer patterns 62, 64, 67, and 68. The semiconductor pattern protrusion A is formed. This ohmic contact layer / semiconductor pattern protrusion A is again subjected to the triple layer pattern 64 on the ohmic contact layer / semiconductor pattern protrusion A while wet etching the triple layer pattern 64 on the subsequent channel portion C. Overetching increases the CD error, resulting in an increase in relative protrusion. The ohmic contact layer / semiconductor pattern protrusion A reduces the aperture ratio of the thin film transistor substrate or causes a defect such as waterfall noise.

In order to minimize the size of the resistive contact layer / semiconductor pattern protrusion A, dry etching of the resistive contact layer / semiconductor pattern is performed again using the photosensitive film pattern 112 that is downsized and narrowed as an etching mask as shown in FIG. 8. do. The portion to be etched here is the resistive contact layer / semiconductor pattern protrusion A that is a side of the resistive contact layer / semiconductor pattern that is not covered by the photoresist pattern 112. In this case, as the etching gas, the same gas as that of the simultaneous etching of the ohmic contact layer and the lower semiconductor layer may be used, for example, a gas including Cl ₂ and / or SF ₆ , but is not limited thereto. This substantially aligns the outer profile of the resistive contact layer / semiconductor layer pattern with the outer profile of the upper triple layer pattern 62, 64, 67, 68. In other words, the outer profile of the ohmic contact layer / semiconductor pattern and the outer profile of the upper triple layer patterns 62, 64, 67, and 68 are aligned substantially in the same plane, with no steps.

Meanwhile, since the etching of the ohmic contact layer / semiconductor pattern is an etching process for removing only the ohmic contact layer / semiconductor pattern protrusion A, the etching of the ohmic contact layer / semiconductor pattern needs to be performed for the same time as the simultaneous etching of the ohmic contact layer and the semiconductor layer. It is sufficient to proceed for less time. Further, even if some of the resistive contact layer / semiconductor pattern protrusion A remains, it can be removed even during the process of etching the resistive contact layer on the subsequent channel portion C, thereby further minimizing the etching time.

Subsequently, as illustrated in FIG. 9, the triple layer pattern 64 of the channel part C is etched and removed. The etching process is a wet etching using an etching solution, for example, H ₂ PO ₃ , CH ₃ COOH, HNO ₃ , H ₂ O or the like can be used as an etchant. As a result, the ohmic contact layer 54 is exposed on the channel portion C. Subsequently, the ohmic contact layer 54 exposed on the channel portion C is dry etched. Here, as the etching gas, for example, a gas containing Cl ₂ and / or SF ₆ may be used, but is not limited thereto. In this case, in order to completely remove the ohmic contact layer 56 of the channel part C, an overetch process may be performed to partially etch the lower semiconductor layer 44. In this process, if there is a protrusion that is not completely removed during the etching process of the resistive contact layer / semiconductor pattern protrusion described above, it may be removed together.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data wirings 65 and 66 and the ohmic contacts 55 and 56 thereunder.

Subsequently, as shown in FIG. 10, the photosensitive film second portion 112 remaining in the data line portion is removed.

Subsequently, as shown in FIG. 11, a protective film 70 is formed.

12A and 12B, the protective film 70 is photo-etched together with the gate insulating film 30 to expose the drain electrode extension 67, the gate end 24, and the data end 68, respectively. Contact holes 77, 74, and 78 are formed.

Finally, as illustrated in FIGS. 1A and 1B, an ITO layer having a thickness of 400 μs to 500 μs is deposited and etched to assist the pixel electrode 82 connected to the drain electrode extension 67 and the auxiliary end connected to the gate end 24. An auxiliary data end 88 is formed which is connected to the gate end 84 and the data end 68.

On the other hand, it is preferable to use nitrogen as a gas used in the pre-heating process before laminating the ITO, which is the metal film (24, 67, 68) exposed through the contact holes (74, 77, 78) This is to prevent the metal oxide film from being formed on top of the.

In this embodiment, the conductive layer of the gate line and the data line is formed of a triple layer made of a molybdenum layer, an aluminum layer, and a molybdenum layer, but this is merely an example, for example, aluminum or an alloy thereof, copper or an alloy thereof, silver (Ag). ), Or a single film made of an alloy thereof, or a double film in which molybdenum, titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W) or alloys thereof are sequentially stacked, or a triple film in combination thereof. Applicable, but not limited to.

The method of manufacturing a thin film transistor substrate according to the present invention may be easily applied to an array on color filter (AOC) structure in which a thin film transistor array is formed on a color filter in addition to the above-described embodiments.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments but may be manufactured in various forms, and having ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the method of manufacturing the thin film transistor substrate according to the exemplary embodiment of the present invention, the side of the resistive contact layer / semiconductor pattern is etched to substantially align the resistive contact layer / semiconductor pattern to the end of the conductive layer. By including the step of forming a resistive contact layer / semiconductor pattern protrusion, the opening ratio of the thin film transistor substrate can be minimized, and defects such as waterfall noise can be improved.

Claims (13)

Sequentially stacking a gate insulating film, a semiconductor layer, an ohmic contact layer, and a conductive layer on the substrate on which the gate wiring is formed; The resistive contact layer is exposed by etching the conductive layer using a photoresist pattern in which a portion corresponding to the channel portion of the semiconductor layer is formed on the upper portion of the semiconductor layer to be relatively lower than a portion where other data lines are formed. step; Etching the exposed ohmic contact layer and the lower semiconductor layer using the photoresist pattern to form an ohmic contact layer / semiconductor pattern; Downsizing the photoresist pattern to expose the conductive layer on the channel portion of the semiconductor layer to partially expose the side of the ohmic contact layer / semiconductor pattern; Etching the exposed side of the resistive contact layer / semiconductor pattern to align the outer profile of the resistive contact layer / semiconductor pattern with the outer profile of the upper conductive layer substantially; And Etching the conductive layer and the ohmic contact layer on the channel portion to expose the channel portion of the semiconductor layer. According to claim 1, The conductive layer is a triple film of a molybdenum (or molybdenum alloy) layer / aluminum (or aluminum alloy) layer / molybdenum (or molybdenum alloy) layer. According to claim 1, Etching the conductive layer to expose the ohmic contact layer by wet etching. According to claim 1, Etching the resistive contact layer and the semiconductor layer below is performed by dry etching. According to claim 1, Downsizing the photoresist pattern is a step performed by an etch back. According to claim 1, Downsizing the photoresist pattern is a method of manufacturing a thin film transistor substrate by a dry etching. According to claim 1, And etching the side of the ohmic contact layer / semiconductor pattern using the downsized photoresist pattern as an etch mask. The method of claim 7, wherein Etching the side of the ohmic contact layer / semiconductor pattern is performed by dry etching. The method of claim 8, The etching gas used for the dry etching includes a Cl ₂ and / or SF ₆ manufacturing method of a thin film transistor substrate. The method of claim 7, wherein The etching of the side of the ohmic contact layer / semiconductor pattern is performed using the same etching gas as that used in etching the ohmic contact layer and the semiconductor layer below. . The method of claim 7, wherein The etching of the side of the ohmic contact layer / semiconductor pattern has a shorter etching time than the etching of the ohmic contact layer and the semiconductor layer below. According to claim 1, Etching the resistive contact layer on the channel portion to expose the channel portion of the semiconductor layer by dry etching. The method of claim 12, Etching the ohmic contact layer on the channel portion to expose the channel portion of the semiconductor layer may be performed using the same etching gas as that used in etching the side portion of the ohmic contact layer / semiconductor pattern. Method of manufacturing a thin film transistor substrate.

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