KR20060133690A - Method for manufacturing a nonvolatile memory - Google Patents

Abstract

A method for manufacturing a nonvolatile memory device is provided to prevent the generation of moat by reducing a cleaning time for removing a screen oxide layer using an additional dry etching process. A screen oxide layer(11c) is formed on a semiconductor substrate(10). A pad nitride layer is deposited on the screen oxide layer. A trench is formed on the resultant structure by etching partially the pad nitride layer, the screen oxide layer and the substrate. An isolation layer(15) is filled in the trench. The pad nitride layer is removed from the resultant structure. The screen oxide layer is selectively etched by using a dry etching process. Then, a cleaning process is performed on the resultant structure to remove the screen oxide layer therefrom.

Description

Non-volatile memory device manufacturing method {METHOD FOR MANUFACTURING A NONVOLATILE MEMORY}

FIG. 1 is a SEM photograph showing a mort profile after a cleaning process is performed before forming a tunnel oxide layer in manufacturing a flash memory device according to the related art.

FIG. 2 is a SEM photograph showing a mortise profile after tunnel oxide film formation when fabricating a flash memory device according to the related art. FIG.

3 to 8 are cross-sectional views illustrating a process of manufacturing a nonvolatile memory device in accordance with a preferred embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a device after formation of a tunnel oxide film in manufacturing a nonvolatile memory device according to an exemplary embodiment of the present invention. FIG.

<Explanation of symbols for main parts of drawing>

10 semiconductor substrate 11 screen oxide film

12: pad nitride film 13: trench

14 wall oxide film 15 insulating film (or device isolation film)

17: wet etching process 18: dry etching process

11a: pad oxide film 11b: low voltage gate oxide film

11c: high-voltage gate oxide film Cell: cell region

LV: low voltage area HV: high voltage area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile memory, and in particular, a method of manufacturing a 0.06 / 0.07㎛ NAND flash memory device using a shallow trench isolation (STI) device isolation process. It is about.

In manufacturing a flash memory device, a flash memory cell is generally implemented using a shallow trench isolation (STI) process as a device isolation process, and mask patterning is performed. Wafer uniformity is very poor according to the variation of mask critical dimension (CD) during the isolation process of the used floating gate, so that it is not easy to implement a uniform floating gate, and a coupling rate As a result of the change, problems such as program and erase fail of a memory cell occur. Furthermore, when forming a floating gate having a small space of 0.15 μm or less due to the highly integrated design, the mask process becomes more difficult, making the manufacturing process of a flash memory cell more difficult to achieve a uniform floating gate. have.

On the other hand, if the floating gate is not formed uniformly due to the above reasons, the difference in coupling ratio is intensified, causing problems such as over erase during program and erase of the memory cell. Increasingly, the increase of the mask process causes the lowering of product yields and the cost increase. In addition, as the moat is generated in the upper corner portion of the trench during the STI process, when the tunnel oxidation process is subsequently performed, the tunnel oxide layer in the upper corner portion of the trench becomes an active region. Gate oxide thinnging, which is formed thinner than the oxide thickness of the tunnel oxide or is not normally formed, occurs. As a result, the tunnel oxide film is not formed to have a uniform thickness on the upper surface of the semiconductor substrate, but is formed to have a thickness smaller than that of the deposition target at the upper corner portion of the trench. Accordingly, leakage current occurs in the upper corner portion of the trench, thereby lowering the threshold voltage Vth characteristic of the flash memory cell.

Typically, the mort is generated when the screen oxide film is formed to prevent damage to the substrate during the ion implantation process for forming the well and adjusting the threshold voltage during the STI process. Process conditions for the removal of the screen oxide film should ensure that the critical dimension of the appropriate device isolation region (or active region) and the screen oxide film removal are satisfied at the same time. For example, the oxide film-based device isolation film must be etched to have an appropriate critical dimension and the screen oxide film must be removed.

However, when the screen oxide film is thinly formed during the removal of the screen oxide film, the screen oxide film is excessively etched to generate mort along the interface between the device isolation film and the screen oxide film. In addition, even when the screen oxide film is formed thick, the screen oxide film remains on the substrate after the device isolation film is etched, so that the screen oxide film must be removed through a subsequent cleaning process. This is due to the longer cleaning process time for removing the thick screen oxide film.

FIG. 1 is a SEM (Scanning Electron Microscope) photograph showing a mort profile after the cleaning process for removing the screen oxide film. FIG. 2 is a tunnel oxide film on the entire surface of the substrate after the cleaning process is performed. It is the SEM photograph which showed the mort profile after forming. 1 and 2, it can be seen that a mott (see 'M' region) occurs in the upper corner portion of the trench.

Accordingly, the present invention has been proposed to solve the above-mentioned problems. In the manufacture of a nonvolatile memory device using the STI device isolation process, a nonvolatile memory device may be manufactured to suppress the generation of mott at the upper corner of the trench to improve device characteristics. The purpose is to provide a method.

According to an aspect of the present invention, there is provided a semiconductor substrate including a screen oxide film, depositing a pad nitride film on the screen oxide film, the pad nitride film, the screen oxide film, and the like. Etching a portion of the substrate to form a trench, forming a device isolation film in which the trench is embedded, removing the pad nitride film, and performing an etching process so that the screen oxide film remains a predetermined thickness. A method of manufacturing a nonvolatile memory device includes etching a screen oxide film and removing the screen oxide film by performing a cleaning process.

According to another aspect of the present invention, there is provided a semiconductor substrate defined by a cell region, a low voltage region, and a high voltage region, and a thickness of the cell in the high voltage region on the front surface of the substrate. Forming a screen oxide film thicker than the thickness in the region and the low voltage region, depositing a pad nitride film on the screen oxide film, etching the pad nitride film, the screen oxide film, and a portion of the substrate to form the cell region, Forming a trench for each of the low voltage region and the high voltage region, forming a device isolation film in which the trench is embedded, removing the pad nitride film, and etching the screen oxide film by a predetermined thickness; The first and second screen oxides in the cell region and the low voltage region Residue and provides a non-volatile memory device manufacturing method comprising the cleaning step is carried out the screen oxide film in the high voltage domain to residue to a second thickness.

Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. . In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween.

Example

3 to 8 are cross-sectional views illustrating a process of manufacturing a nonvolatile memory device in accordance with a preferred embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 3 to 8 are the same elements having the same function. Hereinafter, for convenience of description, a NAND flash memory device manufacturing process will be described as an example, a cell region is represented by 'Cell', a high voltage region is represented by 'HV', and a low voltage region is represented by 'LV'.

First, as shown in FIG. 3, a semiconductor substrate 10 subjected to a pretreatment cleaning process is provided. Here, the pretreatment cleaning process is washed with DHF (Diluted HF; for example, HF solution diluted with H ₂ 0 at a ratio of 50: 1) and then SC-1 (NH ₄ OH / H ₂ O ₂ / H ₂ O the solution is washed with a solution) were mixed at a predetermined ratio or, BOE (Buffer Oxide Etchant; for example, 100: 1 or 300: the ratio of a mixed solution of HF and NH ₄ F diluted in H ₂ O of 1 [HF and NH ₄ The ratio of F can be washed with SC-1 after washing with 1: 4 to 1: 7].

Subsequently, a screen oxide 11 is formed on the semiconductor substrate 10. Here, the screen oxide film 11 is formed to prevent the surface of the semiconductor substrate 10 from being damaged during the well and threshold voltage ion implantation processes performed in a subsequent process.

In this case, the screen oxide layer 11 is formed to be thick enough to prevent the mort, and is formed thicker in the high voltage region HV than in the cell region Cell and the low voltage region LV. Preferably, the thickness of the screen oxide film 11 formed in the cell region Cell and the low voltage region LV is 230 kPa, and the thickness of the screen oxide film 11 formed in the high voltage region HV is 370 kPa. Hereinafter, a method of forming the screen oxide film 11 will be briefly described as an example. First, a thin film oxide film 11 is formed on the entire structure including a cell region, a low voltage region LV, and a high voltage region HV by performing an oxidation process using a radical method. The radical oxidation process using the mask in which the region HV is opened is performed once again to form the screen oxide film 11 thickly in the high voltage region HV. The screen oxide film 11 may be formed by performing a wet oxidation process within a temperature range of 750 ° C to 800 ° C and then performing an annealing process using N ₂ at a temperature range of 900 ° C to 910 ° C.

In the process step, although not described for convenience of description, the cleaning process may be performed using DHF and SC-1 at least one time during the process steps.

Hereinafter, for convenience of description, the screen oxide film 11 formed in the cell region Cell is referred to as a pad oxide film 11a, and the screen oxide film 11 formed in the low voltage region LV is referred to as a low voltage gate oxide film 11b. The screen oxide film 11 formed in the high voltage region HV is referred to as a high voltage gate oxide film 11c.

Subsequently, a well ion implantation process using the screen oxide film 11 is performed in the semiconductor substrate 10 to form a well (not shown). When the semiconductor substrate 10 is a p-type substrate, the well may be formed of a triple N-well and a P-well. The TN-well is formed by performing an ion implantation process using phosphorus (P), and the P-well is formed by performing an ion implantation process using boron (B). In addition, a threshold voltage ion implantation process is performed on the semiconductor substrate 10 to form a channel.

Subsequently, a pad nitride film 12 is deposited over the entire structure including the pad oxide film 11a, the low voltage gate oxide film 11b, and the high voltage gate oxide film 11c. The pad nitride layer 12 may be deposited by a low pressure chemical vapor deposition (LPCVD) method.

Subsequently, a shallow trench isolation (STI) etching process is performed to etch the pad nitride layer 12, the screen oxide layer 11, and the substrate 10. As a result, trenches 13 are formed in the cell region Cell, the low voltage region LV, and the high voltage region HV, respectively. The trench 13 may be formed to a depth capable of securing isolation characteristics such that the memory cells and / or transistors are electrically independent of each other.

Subsequently, as illustrated in FIG. 4, a wall oxidation process is performed to form a wall in the trench 13 (see FIG. 3) formed in the cell region, the low voltage region LV, and the high voltage region HV, respectively. An oxide film 14 is formed. The month oxidation process is performed by a dry oxidation process in order to compensate for the sidewall of the trench 13 damaged during the trench 13 forming process, and is formed by using a radical method.

Subsequently, an insulating film for device isolation film 15 is deposited over the entire structure including the wall oxide film 14. In this case, the insulating film 15 may be formed of an HDP (High Density Plasma) oxide film, and gap filling may be performed so that voids do not occur in the trench 13.

Subsequently, as shown in FIG. 5, a planarization process is performed to planarize the entire upper portion. At this time, the planarization process is performed by a chemical mechanical polishing (CMP) method. As a result, an insulating film 15 (hereinafter referred to as an element isolation film) embedded in the trench 13 (see FIG. 3) is formed.

Subsequently, as shown in FIG. 6, a wet etching process 17 using phosphoric acid (H ₃ PO ₄ ) is performed to completely remove the pad nitride layer 12 (see FIG. 5) remaining after the planarization process. At this time, the wet etching process 17 is preferably performed by performing the screen oxide film 11 as an etch stop layer so as not to damage the substrate 10. At this time, the pad oxide film 11a and the low voltage gate oxide film 11b remain at a thickness of H _1a . The high voltage gate oxide film 11c remains at a thickness of H _1b . H _1a is preferably 200 kPa with a thickness lost by about 30 m from the thicknesses of the pad oxide film 11a and the low voltage gate oxide film 11b formed first. This is due to the loss of the screen oxide film 11 by a certain thickness when the pad nitride film 12 is removed. Similarly, H _1b is a thickness that is lost by about 30 m from the thickness of the first high-voltage gate oxide film 11c formed.

Next, as shown in FIG. 7, the dry etching process 18 is performed to etch the remaining pad oxide film 11a, the low voltage gate oxide film 11b, and the high voltage gate oxide film 11c. For example, the pad oxide film 11a, the low voltage gate oxide film 11b, and the high voltage gate oxide film 11c are etched by a thickness of 100 to 200 Å. Preferably, the pad oxide film 11a, the low voltage gate oxide film 11b, and the high voltage gate oxide film 11c have a thickness of 150 kV so that the pad oxide film 11a and the low voltage gate oxide film 11b remain by the thickness H _2a of 50 kV. Etch as much as Accordingly, H _{2b, which} is the thickness of the high voltage gate oxide film 11c, becomes H _1b -150 kPa. Here, H _2a and H _2b are thicknesses that can minimize plasma damage caused by the dry etching process 18.

Subsequently, as shown in FIG. 8, a cleaning process is performed to clean the remaining pad oxide film 11a, the low voltage gate oxide film 11b, and the high voltage gate oxide film 11c. As a result, the pad oxide film 11a and the low voltage gate oxide film 11b remain by the thickness of 1 to 7 k? And the high voltage gate oxide film 11c remains by the thickness of 250 to 350 k?

At this time, the cleaning process is a FN cleaning process, a cleaning process using DHF (Diluted HF; HF solution diluted to H ₂ 0 at a ratio of 100: 1) and BOE (Buffered Oxide Etchant; HF and NH ₄ F is 100: 1 or Solution in a 300: 1 solution). In one example, the FN cleaning step is a cleaning step of washing with DHF followed by SC-1 (Standard Cleaning-1), which is performed for approximately 50 to 150 seconds. Preferably, it is carried out for 100 seconds.

Subsequently, although not shown in the figure, a tunnel oxide film is formed according to a general process and a polysilicon film for floating gate is formed. At this time, the tunnel oxide film is formed by performing an oxidation process using a radical method, and the polysilicon film is formed to have a space critical dimension of 40 to 60 nm. Preferably, it is formed to have a critical dimension (CD) of 50 nm. Here, the critical dimension of the polysilicon film has the same value as the critical dimension of the device isolation film 15.

Since a subsequent process is performed in the same manner as a general flash device process, a description thereof will be omitted.

That is, according to a preferred embodiment of the present invention, the thickness of the first screen oxide film is formed thick to the extent that no mort occurs, and then the screen oxide film is etched by a predetermined dry etching process (about 150,). Thereby reducing the cleaning time for removing the screen oxide film. As a result, it is possible to prevent the mote generated due to the increase in the cleaning time.

FIG. 9 is a cross-sectional view illustrating a device after formation of a tunnel oxide layer when a nonvolatile memory device is manufactured according to an exemplary embodiment of the present invention. Referring to FIG. 9, the nonvolatile memory device according to the preferred embodiment of the present invention prevents occurrence of mort. Therefore, it can be seen that the tunnel oxide film is formed to have a uniform thickness.

As described above, the gate oxide film thinning phenomenon can be suppressed by preventing the mort so that the tunnel oxide film is uniformly formed, thereby improving operation characteristics of the semiconductor device.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the thickness of the first screen oxide film to be formed to a thickness such that the mote does not occur thick and then etching the screen oxide film to a certain thickness (approximately, 150Å) through a separate dry etching process Thereby reducing the cleaning time for removing the screen oxide film. As a result, it is possible to prevent the mote generated due to the increase in the cleaning time.

As described above, the gate oxide film thinning phenomenon can be suppressed by preventing the mort so that the tunnel oxide film is uniformly formed, thereby improving operation characteristics of the semiconductor device.

Claims (13)

Providing a semiconductor substrate having a screen oxide film formed thereon; Depositing a pad nitride film on the screen oxide film; Etching a portion of the pad nitride film, the screen oxide film, and the substrate to form a trench; Forming an isolation layer in which the trench is buried; Removing the pad nitride film; Etching the screen oxide film by performing an etching process such that the screen oxide film remains a predetermined thickness; And Performing a cleaning process to remove the screen oxide film Nonvolatile memory device manufacturing method comprising a. The method of claim 1, The etching of the screen oxide film may include etching the screen oxide film by a thickness of about 100 to about 200 microseconds. The method according to claim 1 or 2, And etching the screen oxide layer using a dry etching process. The method of claim 1, The cleaning process is a nonvolatile memory device manufacturing method using the FN cleaning process. The method of claim 4, wherein The FN cleaning process is performed for 50 to 150 seconds. The method of claim 1, The cleaning process is a nonvolatile memory device manufacturing method using a DHF solution. The method of claim 1, The cleaning process is a nonvolatile memory device manufacturing method using a BOE solution. The method of claim 1, wherein after removing the screen oxide film, Forming a tunnel oxide film on the substrate surface; And Forming a polysilicon film for a floating gate on the tunnel oxide film Non-volatile memory device manufacturing method further comprising. The method of claim 8, The tunnel oxide film is formed in a radical manner nonvolatile memory device manufacturing method. The method according to claim 8 or 9, And said polysilicon film has a space critical dimension of 50 nm. Providing a semiconductor substrate defined by a cell region, a low voltage region and a high voltage region; Forming a screen oxide film on the front surface of the substrate, the screen oxide layer having a thickness in the high voltage region greater than the thickness in the cell region and the low voltage region; Depositing a pad nitride film on the screen oxide film; Etching portions of the pad nitride layer, the screen oxide layer, and the substrate to form trenches for the cell region, the low voltage region, and the high voltage region, respectively; Forming an isolation layer in which the trench is buried; Removing the pad nitride film; Etching the screen oxide layer by a predetermined thickness; And Performing a cleaning process such that the screen oxide film in the cell region and the low voltage region remains at a first thickness and the screen oxide film in the high voltage region remains at a second thickness Nonvolatile memory device manufacturing method comprising a. The method of claim 11, The step of performing the cleaning step is a non-volatile memory device manufacturing method performed so that the first thickness is 1 to 7Å. The method of claim 11, The step of performing the cleaning step is a non-volatile memory device manufacturing method performed so that the second thickness is 250 to 350Å.

Images