KR20060130936A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20060130936A
KR20060130936A KR1020050049290A KR20050049290A KR20060130936A KR 20060130936 A KR20060130936 A KR 20060130936A KR 1020050049290 A KR1020050049290 A KR 1020050049290A KR 20050049290 A KR20050049290 A KR 20050049290A KR 20060130936 A KR20060130936 A KR 20060130936A
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South Korea
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film
patterning
mask
patterned
semiconductor device
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KR1020050049290A
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Korean (ko)
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공근규
손민석
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주식회사 하이닉스반도체
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Priority to KR1020050049290A priority Critical patent/KR20060130936A/en
Publication of KR20060130936A publication Critical patent/KR20060130936A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

Abstract

A method for fabricating a semiconductor device is provided to reduce a manufacturing cost by pattering a lower structure without using a high-priced exposure system. A pattern layer forming process is performed to form a pattern layer on an entire surface of a substrate. A first patterning process is performed by using a first mask of a line type. The first mask has a width corresponding to a width of the active region. A second patterning process is performed by using a second mask of a line type. The pattern layer is patterned by using the second mask having the width corresponding to the length of the active region.

Description

반도체 장치의 제조방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

도1 내지 도4는 본 발명의 바람직한 실시예에 따른 반도체 장치의 제조방법을 나타내는 평면도.1 to 4 are plan views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1 : 활성영역으로 정의된 영역1: Area defined as active area

2 : 소자분리영역으로 정의된 영역2: area defined as device isolation area

3 : 제1 활성영역으로 정의된 영역3: area defined as the first active area

4 : 제1 소자분리영역으로 정의된 영역4: region defined as the first device isolation region

5 : 제2 활성영역으로 정의된 영역5: area defined as the second active area

6 : 제2 소자분리영역으로 정의된 영역6: area defined as the second device isolation area

본 발명은 반도체 장치의 제조방법에 관한 것으로 특히 활성영역을 형성하기 위한 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an active region.

최근 반도체 장치의 초고집적화 추세는 미세패턴 형성 기술의 발전에 큰 영향을 받고 있다. Recently, the trend of ultra high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology.

반도체 장치를 제조할 때에는 패턴에 대응하는 마스크를 제조한다음, 기판상에 감광막을 도포하고, 마스크를 이용한 사진식각공정으로 도포된 감광막을 패터닝한다.In manufacturing a semiconductor device, a mask corresponding to a pattern is manufactured, and then a photoresist film is applied onto the substrate, and the photoresist film applied by the photolithography process using the mask is patterned.

이어서 패터닝된 감광막을 이용하여 하부구조를 건식각 또는 습식각을 이용하여 패터닝하게 된다. 이어서 감광막 패턴을 제거한다. 이어서 다음 패터닝된 층을 형성하고, 전술한 과정을 반복하게 된다. Subsequently, the substructure is patterned using dry or wet etching using the patterned photoresist. Subsequently, the photoresist pattern is removed. The next patterned layer is then formed, and the above process is repeated.

반도체 장치를 이루는 회로부분을 제조하기 위해서는 회로부분이 형성되지 않는 부분을 정의해야 하며, 이 영역을 소자분리 영역이라 하고, 회로가 형성되는 영역, 특히 모스트랜지스터가 형성되는 영역을 활성영역이라 한다.In order to manufacture a circuit portion constituting a semiconductor device, a portion where a circuit portion is not formed must be defined, and this region is called an element isolation region, and an region where a circuit is formed, particularly an region where a MOS transistor is formed, is called an active region.

따라서 감광막 패턴 형성공정은 반도체 장치의 제조공정에 있어서 매우 중요한 공정이다. Therefore, the photosensitive film pattern formation process is a very important process in the manufacturing process of a semiconductor device.

소자의 집적도가 증가되면서 감광막 패턴의 크기도 줄어들기 때문에 신뢰성있게 감광막 패턴을 형성하기 점점 더 어려워지고 있다. 특히 감광막 패턴을 사선형태로 형성하는 것은 더욱 어려워지고 있다.As the integration degree of the device increases, the size of the photoresist pattern decreases, making it difficult to form a photoresist pattern reliably. In particular, it is becoming more difficult to form the photosensitive film pattern in a diagonal form.

감광막 패턴이 제대로 형성이 않되면, 그 하단의 패턴이 제대로 형성되지 않고, 결국 반도체 장치를 제대로 제조할 수 없게 되는 것이다.If the photoresist pattern is not formed properly, the pattern at the bottom thereof is not formed properly, and eventually the semiconductor device cannot be manufactured properly.

본 발명은 전술한 문제점을 해결하기 위해 제안된 것으로, 미세패턴을 형성할 때 보다 용이하게 패턴을 형성할 수 있는 반도체 장치의 제조방법을 제공함을 목적으로 한다.The present invention has been proposed to solve the above-described problem, and an object of the present invention is to provide a method of manufacturing a semiconductor device which can form a pattern more easily when forming a fine pattern.

본 발명은 기판상의 소정영역에 형성되는 활성영역을 형성하기 위한 반도체 장치의 제조방법에 있어서, 상기 기판 전면에 패턴용 막을 형성하는 단계; 상기 활성영역의 폭에 대응하는 폭을 가지며 라인형태의 제1 마스크를 이용하여 상기 패턴용 막을 제1 패터닝하는 단계; 및 상기 활성영역의 길이에 대응하는 폭을 가지는 라인형태의 제2 마사크를 이용하여 패터닝된 상기 패턴용 막을 제2 패터닝하는 단계를 포함하는 반도체 장치의 제조방법을 제공한다.A method of manufacturing a semiconductor device for forming an active region formed in a predetermined region on a substrate, the method comprising: forming a patterned film on the entire surface of the substrate; First patterning the pattern film using a first mask having a width corresponding to the width of the active region and having a line-shaped mask; And second patterning the patterned film for patterning by using a line-shaped second mask having a width corresponding to the length of the active region.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도1 내지 도4는 본 발명의 바람직한 실시예에 따른 반도체 장치의 제조방법을 나타내는 평면도이다.1 to 4 are plan views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

본 발명의 가장 큰 특징은 반도체 장치의 활성영역을 형성하는 방법으로 하나의 패턴을 2개로 나누어 패터닝하는 것이다. 즉 감광막 패터닝이 가능하도록 2차 에 나누어 반도체 기판상에 활성영역을 만드는 것이다.The biggest feature of the present invention is a method of forming an active region of a semiconductor device and dividing a pattern into two patterns. In other words, the active region is formed on the semiconductor substrate by dividing into secondary to enable photoresist patterning.

이렇게 하면, 고가의 장비인 ArF 장비를 투자하지 않고 종래에 사용하는 KrF 광원을 이용하여 패터닝이 가능하게 되며, 종래의 방법대로 하나의 패터닝으로 활성영역으로 형성하는 것보다 CD 균일성을 향상시킬 수 있다.This enables patterning using conventional KrF light sources without investing expensive ArF equipment, and improves CD uniformity than forming active regions with one patterning in the conventional manner. have.

마스크를 제조할 때에 차광 패턴으로 크롬(Cr)이 사용될 수 있지만, 반드시 여기에 한정되는 것은 아니다. 또한 차광패턴을 이용한 노광공정시 광원은 VUV, ArF, KrF, EUV, E-빔, X-선 및 이온빔중 선택된 하나를 이용할 수 있다.Chromium (Cr) may be used as the light shielding pattern in manufacturing the mask, but is not necessarily limited thereto. In addition, during the exposure process using the light shielding pattern, the light source may use one selected from VUV, ArF, KrF, EUV, E-beam, X-ray and ion beam.

도1은 최종적으로 형성될 활성역역의 평면도이며, 활성영역(1)과 소자분리영역(2)이 도시되어 있다.Fig. 1 is a plan view of the active area to be finally formed, and the active area 1 and the device isolation area 2 are shown.

먼저 첫번째 패터닝을 위한 제1 마스크는 도2에 도시되어 있는데, 각각 제1 활성영역(3)과 제1 소자분리영역(4)이 배치되어 있다.First, a first mask for first patterning is illustrated in FIG. 2, in which a first active region 3 and a first device isolation region 4 are disposed.

도2를 참조하여 살펴보면, 제1 마스크로 KrF 6% Halt tone PSM을 제조한다.Referring to FIG. 2, KrF 6% Halt tone PSM is manufactured using a first mask.

이것은 패턴의 피치가 줄어들수록 해상력의 한계가 있기 때문에 종래에 사용하던 크롬 마스크로는 해상력이 나오지 않기 때문에, 크롬 대신 6% 광이 통과하는 H/T PSM을 제작하게 된다.This is because as the pitch of the pattern decreases, there is a limit of resolution, so the resolution of the chromium mask used in the past does not come out, and thus instead of chromium, 6% light passes through H / T PSM.

이 때 마스크상에 패턴이 있는 부분을 크롬 처리하여 웨이퍼 상에서 감광막 라인 패턴이 형성되도록 제작한다. At this time, the portion having the pattern on the mask is chrome-treated to form a photoresist line pattern on the wafer.

또한 제1 마스크 제작시 후속 두번째 마스크인 제2 활성영역(5)과 제2 소자분리영역(6)이 있는 제2 마스크와 얼라인될 수 있도록 얼라인키 및 오버레이 키 어미자를 삽입한다.In addition, an alignment key and an overlay key mother are inserted to align the second mask including the second active region 5 and the second device isolation region 6, which are the second mask, when the first mask is manufactured.

실리콘 기판상에 완충용 실리콘산화막을 15nm로 완충용 실리콘질화막을 60nm 두께로 형성한 후 난반사 방지막인 DUV44-7을 60nm 두께로 도포 및 가열한 후SL4000(Rohm 및 hass사)감광제를 215nm 두께로 도포한다. 이후 전술한 제1 마스크를 이용하여 노광 후 현상하여 감광막 패턴을 형성하고, 감광막 패턴을 이용하여 완충용 실리콘질화막, 완충용 실리콘산화막을 순차적으로 식각한다.A buffer silicon oxide film was formed to a thickness of 15 nm on a silicon substrate, and a buffer silicon nitride film was formed to a thickness of 60 nm. Then, DUV44-7, an anti-reflective film, was applied and heated to a thickness of 60 nm, and a SL4000 (Rohm and hass) photosensitive agent was applied to a thickness of 215 nm. do. Subsequently, the substrate is developed after exposure using the first mask as described above to form a photoresist pattern, and the buffer silicon nitride film and the buffer silicon oxide film are sequentially etched using the photoresist pattern.

이 때 실리콘 웨이퍼의 표면상에서 식각이 정지되도록 한 다음, 감광막 패턴을 제거한다.At this time, the etching is stopped on the surface of the silicon wafer, and then the photoresist pattern is removed.

이어서 도3에 도시된 바와 같이, 제2 마스크로 KrF 6% Halt tone PSM을 제조한다. 이 때 마스크상에 패턴이 있는 부분을 No 크롬 처리하여 웨이퍼상에서 감광막 스페이서 패턴이 형성되도록 제작한다.3, KrF 6% Halt tone PSM is manufactured with a second mask. At this time, a portion having a pattern on the mask is subjected to No chromium treatment so as to form a photoresist spacer pattern on the wafer.

제2 마스크는 제1 마스크와 얼라인 될수 있도록 오버레이 아들자를 삽입한다.The second mask inserts an overlay sonar so that it can be aligned with the first mask.

제2 마스크가 제조된 상태에서 전술한 패턴이 형성된 실리콘 웨이퍼 상에 난반사 방지막인 DUV44-7을 60nm 두께로 도포하고 SL4000((Rohm 및 hass사)감광제를 280nm 두께로 도포한다. 이어서 가열공정을 한 후, 제2 마스크를 이용하여 노광 및 현상공정은 진행한다.In the state where the second mask was prepared, DUV44-7, an anti-reflective film, was applied to the silicon wafer on which the above-described pattern was formed at a thickness of 60 nm, and a SL4000 (Rohm and Hass) photoresist was applied to a thickness of 280 nm. Subsequently, the exposure and development processes proceed using the second mask.

현상 후 DICD(감광막 패터닝후의 CD)를 100nm 스페이스로 패터닝한 후, 레지스터 플로우(Resist flow) 공정을 도입하여 2스텝으로 진행하는데, 제1 스텝으로 120℃/90초, 제2 스텝으로 140℃/90초로 진행하여 최종 DICD 80nm 스페이로 형성한다.After development, the DICD (CD after photoresist patterning) is patterned into a 100 nm space, and then a resist flow process is introduced to proceed to two steps, 120 ° C./90 seconds in the first step, and 140 ° C. / in the second step. Proceed to 90 seconds to form the final DICD 80 nm spade.

이렇게 2단계로 감광막을 패터닝하는 것은 감광막의 CD 균일성을 확보하기 위해 먼저 100nm로 패터닝한 후, 다음 단계에서 리플로우로 원하는 패턴의 감광막을 형성시키는 것이다.The patterning of the photoresist in two steps is to first pattern the photoresist to 100 nm in order to ensure CD uniformity of the photoresist, and then to form a photoresist having a desired pattern by reflow in the next step.

상기 형성된 감광막을 이용하여, 완충용 실리콘질화막 및 완충용 실리콘산화막을 식각한다. 이 때 식각은 실리콘 웨이퍼의 표면상에서 정지되도록 하며, 감광막 패턴을 제거한다.By using the formed photosensitive film, the buffer silicon nitride film and the buffer silicon oxide film are etched. At this time, the etching is stopped on the surface of the silicon wafer, and the photoresist pattern is removed.

이어서 도4에 도시된 바와 같이 제1 마스크와 제2 마스크에서 크롬이 중첩되어진 부분은 완충용 실리콘질화막 및 완충용 실리콘산화막이 남아 있게 된다.Subsequently, as shown in FIG. 4, in the portion where the chromium is overlapped in the first mask and the second mask, the buffer silicon nitride film and the buffer silicon oxide film remain.

남아 있는 완충용 실리콘질화막 및 완충용 실리콘산화막을 방벽으로 소정두께의 반도체 기판을 식각하여 트랜치를 형성하고, 트랜치에 절연막을 매립하여 소자분리막을 형성하여 최종적으로 활성영역을 형성한다.A trench is formed by etching the semiconductor substrate having a predetermined thickness with the remaining buffered silicon nitride film and the buffered silicon oxide film as a barrier. An insulating film is embedded in the trench to form an isolation layer to finally form an active region.

이상과 같이 활성영역을 형성하게 되면, 소자분리막을 2차로 나누어 패터닝이 쉬운 라인 및 스페이스 타입으로 마스크를 제작함으로서 감광제 패터닝이 용이하게 되어 추가적인 고가장비인 ArF 노광장비를 사용하지 않고 KrF 노광장비를 사용하여도 충분히 고집적의 반도체 장치를 제조할 수 있다.When the active region is formed as described above, by dividing the device isolation film into secondary lines, a mask is manufactured in a line and space type that is easy to pattern, so that the photoresist patterning becomes easy, and KrF exposure equipment is used without using an additional expensive ArF exposure equipment. Even if it is, a highly integrated semiconductor device can be manufactured.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명에 의해서 고집적화된 반도체 장치를 제조할 때에 고가 노광장비를 사용하지 않고도 신뢰성있게 하부구조를 패터닝할 수 있게 되었다. 따라서 반도체 장치의 제조에 투입되는 비용을 줄일 수 있게 되었다.According to the present invention, it is possible to reliably pattern the substructure without using expensive exposure equipment when manufacturing a highly integrated semiconductor device. Therefore, the cost of manufacturing the semiconductor device can be reduced.

Claims (7)

기판상의 소정영역에 형성되는 활성영역을 형성하기 위한 반도체 장치의 제조방법에 있어서,In the method of manufacturing a semiconductor device for forming an active region formed in a predetermined region on a substrate, 상기 기판 전면에 패턴용 막을 형성하는 단계;Forming a patterned film on the entire surface of the substrate; 상기 활성영역의 폭에 대응하는 폭을 가지며 라인형태의 제1 마스크를 이용하여 상기 패턴용 막을 제1 패터닝하는 단계; 및First patterning the pattern film using a first mask having a width corresponding to the width of the active region and having a line-shaped mask; And 상기 활성영역의 길이에 대응하는 폭을 가지는 라인형태의 제2 마사크를 이용하여 패터닝된 상기 패턴용 막을 제2 패터닝하는 단계Second patterning the patterned patterned film using a second mask in a line shape having a width corresponding to the length of the active region 를 포함하는 반도체 장치의 제조방법.Method for manufacturing a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제1 패터닝하는 단계는The first patterning step 상기 패턴용 막상에 제1 감광막을 형성하는 단계;Forming a first photosensitive film on the patterned film; 상기 제1 마스크를 이용하여 상기 제1 감광막을 패터닝하는 단계; 및Patterning the first photoresist film using the first mask; And 상기 패터닝된 제1 감광막을 이용하여 상기 패턴용 막을 일차로 패터닝하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.And patterning the patterned film primarily using the patterned first photosensitive film. 제 2 항에 있어서,The method of claim 2, 상기 제1 감광막을 패터닝하는 단계는The step of patterning the first photoresist film VUV, ArF, KrF, EUV, E-빔, X-선 및 이온빔중 선택된 하나를 이용하여 공정을 진행하는 것을 특징으로 하는 반도체 장치의 제조방법.A process for manufacturing a semiconductor device, characterized in that the process is carried out using one selected from VUV, ArF, KrF, EUV, E-beam, X-ray and ion beam. 제 2 항에 있어서,The method of claim 2, 상기 제2 패터닝하는 단계는The second patterning step 상기 제1 패터닝하는 단계에 의해 패터닝된 상기 패턴용 막상에 제2 감광막을 형성하는 단계;Forming a second photosensitive film on the patterned film patterned by the first patterning; 상기 제2 마스크를 이용하여 상기 제2 감광막을 패터닝하는 단계; 및Patterning the second photoresist film using the second mask; And 상기 패터닝된 제2 감광막을 이용하여 상기 패턴용 막을 2차로 패터닝하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.And patterning the patterned film secondarily by using the patterned second photosensitive film. 제 4 항에 있어서,The method of claim 4, wherein 상기 제2 감광막을 패터닝하는 단계는Patterning the second photosensitive film VUV, ArF, KrF, EUV, E-빔, X-선 및 이온빔중 선택된 하나를 이용하여 공정을 진행하는 것을 특징으로 하는 반도체 장치의 제조방법.A process for manufacturing a semiconductor device, characterized in that the process is carried out using one selected from VUV, ArF, KrF, EUV, E-beam, X-ray and ion beam. 제 1 항에 있어서,The method of claim 1, 상기 제1 및 제2 마스크는 크롬을 이용하여 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.The first and second masks are formed using chromium. 제 1 항에 있어서,The method of claim 1, 상기 패턴용 막은The pattern film 실리콘산화막 또는 실리콘질화막이거나, 이들을 적측하여 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.A silicon oxide film or a silicon nitride film, or a method of manufacturing a semiconductor device, characterized in that the formation is carried out.
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