KR20060116726A - Ferrodielectric memory device and manufacturing method thereof - Google Patents

Abstract

A ferroelectric memory device and a manufacturing method thereof are provided to simplify manufacturing processes and to reduce fabrication costs by using a channel forming layer made of an organic semiconductor layer. A ferroelectric memory device comprises a substrate(10), a gate electrode, drain/source electrodes, a ferroelectric layer, and a channel forming layer. The gate electrode(21) is formed on the substrate. The drain/source electrodes(24,25) are formed both sides of the gate electrode on the substrate. The ferroelectric layer(23) is formed on the gate electrode. The ferroelectric layer is made of a PVDF layer. The channel forming layer(22) is interposed between the gate electrode and the ferroelectric layer. The channel forming layer is made of an organic semiconductor layer.

Description

Ferroelectric memory device and manufacturing method

1 is a characteristic graph showing characteristics of general PVDF.

Figure 2 is a characteristic graph showing the polarity characteristics according to the applied voltage with PVDF manufactured according to the present invention.

3 is a structural diagram showing an example of the structure of a ferroelectric memory device according to the present invention;

4 is an equivalent circuit configuration of a ferroelectric memory device according to the present invention;

5 is a view for explaining a manufacturing process of the ferroelectric memory device according to the present invention.

6 is a structural diagram showing another structural example of the ferroelectric memory device according to the present invention;

*** Brief description of the main parts of the drawing ***

10: substrate, 21: gate electrode,

22: insulating layer, 23: ferroelectric layer,

24: drain electrode, 25: source electrode.

The present invention relates to a memory device using a ferroelectric and a method of manufacturing the same.

At present, memory devices are essentially adopted in most electronic devices including personal computers. These memory devices are mainly ROMs such as EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable PROM), Flash ROM (Flash ROM), Static Random Access Memory (SRAM), Dynamic RAM (DRAM), and Ferroelectric RAM (FRAM). RAM). These memory devices are usually made by forming a capacitor and a transistor on a semiconductor wafer such as silicon.

Conventional memory devices have been mainly studied for ways to increase the density of memory cells. However, in recent years, as the interest in non-volatile memory that can maintain stored data even when the power supply is cut off, a lot of researches on the use of ferroelectric material as a material of the memory device.

Currently, inorganic materials such as lead zirconate titanate (PZT), strontium bismuth tantalite (SBT), and lanthanum-substituted bismuth titanate (BLT) are mainly used as ferroelectric materials used in memory devices. However, in the case of such inorganic ferroelectric, its price is high first, and the deterioration of polarity characteristics is caused over time, and high temperature treatment is required as well as expensive equipment is required.

Accordingly, the present invention has been made in view of the above circumstances, and an object thereof is to provide a memory device using an organic material which is easy to manufacture, low cost, and has excellent polarity characteristics, and a method of manufacturing the same.

A ferroelectric memory device according to a first aspect of the present invention for realizing the above object comprises a substrate, a gate electrode, a drain and source electrode, a channel forming layer, and a ferroelectric layer, wherein the ferroelectric layer has a β-phase crystal structure. It is made of a PVDF layer, characterized in that the channel forming layer is formed between the gate electrode and the ferroelectric layer.

In addition, the ferroelectric memory device according to the second aspect of the present invention includes a substrate, a gate electrode, a drain and a source electrode, a channel forming layer, and a ferroelectric layer, and the ferroelectric layer is formed of a PVDF layer having a β-phase crystal structure. A ferroelectric layer is formed between the gate electrode and the channel forming layer.

In addition, the channel forming layer is characterized in that the organic semiconductor layer.

In addition, the channel forming layer is characterized in that the insulating layer.

In addition, the substrate is polyimide (PI), polycarbonate (PC), polyether sulfone (PES), polyether ether ketone (PEEK), polybutylene terephthalate (PBT), polyethylene terephthalate (PET), polychloride Vinyl (PVC), Polyethylene (PE), Ethylene Copolymer, Polypropylene (PP), Propylene Copolymer, Poly (4-methyl-1-pentene) (TPX), Polyarylate (PAR), Polyacetal (POM) , Polyphenylene oxide (PPO), polysulfone (PSF), polyphenylene sulfide (PPS), polyvinylidene chloride (PVDC), polyvinyl acetate (PVAC), polyvinyl alcohol (PVAL), polyvinyl acetal, polystyrene (PS), AS resin, ABS resin, polymethyl methacrylate (PMMA), fluorine resin, phenol resin (PF), melamine resin (MF), urea resin (UF), unsaturated polyester (UP), epoxy resin ( EP), diallyl phthalate resin (DAP), polyurethane (PUR), polyamide (PA), silicone resin (SI) or mixtures and compounds thereof And that is characterized.

In addition, the substrate is characterized in that it is made of a material containing paper.

In addition, the insulating layer is characterized in that the organic material.

In addition, a method of manufacturing a ferroelectric memory device according to a third aspect of the present invention includes forming a gate electrode in a method of manufacturing a semiconductor device including a substrate, a gate electrode, a drain and source electrode, a channel forming layer, and a ferroelectric layer. And forming a channel forming layer, forming a ferroelectric layer, forming a drain and a source electrode, and a ferroelectric layer phase transition step of setting the ferroelectric layer to β phase.

In addition, the channel forming layer is formed between the gate electrode and the ferroelectric layer.

In addition, the ferroelectric layer is formed between the gate electrode and the channel forming layer.

In addition, the ferroelectric layer phase transition step is a first step of raising the temperature of the ferroelectric layer above the temperature of the β-phase crystal, a second step of monotonically reducing the temperature of the ferroelectric layer to the β-phase crystal temperature, And a third step of rapidly lowering the temperature of the ferroelectric layer.

In addition, the phase transition step of the ferroelectric layer is characterized in that it comprises a first step of raising the temperature of the ferroelectric layer to a temperature forming a β phase crystal, and a second step of rapidly lowering the temperature of the ferroelectric layer do.

In addition, the ferroelectric layer is characterized in that the PVDF layer.

In addition, the ferroelectric layer phase transition step is performed after forming the gate electrode, the source and the drain electrode.

Hereinafter, an embodiment according to the present invention will be described with reference to the drawings.

First, the basic concept of the present invention will be described.

At present, various kinds of organic materials having ferroelectric properties are known. Typical examples thereof include polyvinylidene (PVDF), polymers, copolymers, or terpolymers containing PVDF, and odd number nylon, cyano polymers, and polymers and copolymers thereof. . Among the ferroelectric organic materials described above, PVDF and polymers, copolymers, or terpolymers thereof have been studied as a material for organic semiconductors.

In general, in order to use a ferroelectric organic material as a material of a memory device, the organic material must have hysteretic polarity with respect to voltage. However, in the case of the above-described PVDF, as shown in FIG. 1, its capacitance increases with applied voltage, and does not have hysteretic characteristics suitable for use in a memory device.

According to the present inventors, PVDF has four types of crystal structures of α, β, γ, and δ, and it is confirmed that the PVDF has good hysteresis polarity in the crystal structure of β phase. At this time, in order to determine the phase crystal of PVDF as β phase, PVDF is deposited on a semiconductor electrode and then phase transition occurs to β phase, for example, a temperature of 60 to 70 ° C., preferably a temperature of approximately 65 ° C., or PVDF is β phase PVDF is determined to be β phase by rapid cooling of PVDF at the temperature indicated by.

2 is a graph showing the polarity characteristics with respect to the voltage of the PVDF thin film produced according to the present invention. 2 is a result of forming a PVDF thin film having a β phase between a lower electrode and an upper electrode made of a conductive metal, and applying a predetermined voltage between the lower electrode and the upper electrode. The PVDF thin film is formed on a lower electrode, for example, by forming a PVDF thin film of 1 μm or less through spin coating at 3,000 rpm or lower and annealing at 120 ° C. or higher, and then forging the temperature of the PVDF thin film on a hot plate. Reduced to form, for example, by rapid cooling of the PVDF thin film at a temperature of 65 ° C.

As can be seen in Figure 2, the PVDF thin film produced in accordance with the present invention has a polarity increases as the applied voltage increases between about 0 ~ 1V, showing a polarity of about 5μC / ㎠ or more at about 1V, again As the applied voltage falls between 0 and -1 V, the polarity decreases, and has a good hysteresis characteristic showing a polarity of about -5 µC / cm 2 or less at about -1 V.

Therefore, the PVDF thin film according to the present invention shown in FIG. 2 has the following characteristics.

First, the PVDF thin film according to the present invention has a polarity of 5 μC / cm 2 or more or -5 μC / cm 2 or less at 0V. This means that the polarity of the PVDF thin film is maintained unchanged at 0V where no voltage is applied externally. That is, the PVDF thin film according to the present invention may be usefully used as a material of a nonvolatile memory.

Second, the polarity of the PVDF thin film according to the present invention is changed within the range of -1 to 1V. In other words, data can be written and erased at a very low voltage. That is, the PVDF thin film according to the present invention can be usefully used to implement a memory device operating at a low voltage.

Hereinafter, the embodiment according to the present invention will be described in more detail.

3 is a structural diagram illustrating a structure of a ferroelectric memory device according to an embodiment of the present invention.

In FIG. 3, the memory cell 20 is formed on the substrate 10. Here, the substrate 10 is made of a conductive material such as general silicon or metal. In addition, the substrate 10 may be formed of an organic material such as paper coated with a coding material such as parylene or a plastic having flexibility. The organic materials usable here include polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyether ether ketone (PEEK), polybutylene terephthalate (PBT), polyethylene terephthalate (PET), Polyvinyl chloride (PVC), polyethylene (PE), ethylene copolymer, polypropylene (PP), propylene copolymer, poly (4-methyl-1-pentene) (TPX), polyarylate (PAR), polyacetal ( POM), polyphenylene oxide (PPO), polysulfone (PSF), polyphenylene sulfide (PPS), polyvinylidene chloride (PVDC), polyvinyl acetate (PVAC), polyvinyl alcohol (PVAL), polyvinyl acetal , Polystyrene (PS), AS resin, ABS resin, polymethyl methacrylate (PMMA), fluorine resin, phenol resin (PF), melamine resin (MF), urea resin (UF), unsaturated polyester (UP), epoxy Resin (EP), diallyl phthalate resin (DAP), polyurethane (PUR), polyamide (PA), silicone resin (SI) or mixtures and compounds thereof It can be used.

The gate electrode 21 is formed as a lower electrode on the substrate 10 by a known method. In this case, the gate electrode 21 is based on gold, silver, aluminum, platinum, indium tin compound (ITO), strontium titanate compound (SrTiO ₃ ), other conductive metal oxides, alloys and compounds thereof, or conductive polymers. For example, a mixture such as polyaniline, poly (3,4-ethylenedioxythiophene) / polystyrenesulfonate (PEDOT: PSS), a compound, or a multilayered material is used.

Subsequently, the organic semiconductor layer 22 is formed as a channel forming layer while coating the gate electrode 21 and the substrate 10 as a whole. Examples of the organic semiconductor layer 22 include Cu-phthalocyanine, polyacetylene, merocyanine, polythiophene, phthalocyanine, and poly (3-hexylthiophene). ) [Poly (3-hexylthiophene)], poly (3-alkylthiophene) [Poly (3-alkylthiophene), α-sexithiophene, pentacene, α-ω-dihexyl -Sexythiophene (α-ω-dihexyl-sexithiophene), Polythienylenevinylene, Bis (dithienothiophene), α-ω-dihexyl-quaterthiophene, dihexyl Anthadithiophene (Dihexyl-anthradithiophene), α-ω-dihexyl-quinquethiophene, F8T2, Pc ₂ Lu, Pc ₂ Tm, C ₆₀ / C ₇₀ , TCNQ, C ₆₀ , PTCDI-Ph, TCNNQ, NTCDI, NTCDA, PTCDA, F16CuPc, NTCDI-C8F, DHF-6T, PTCDI-C8 and the like can be used.

In addition, an insulating layer may be used as the channel forming layer, that is, the organic semiconductor layer 22. At this time, as the insulating layer, inorganic materials such as ZrO ₂ , SiO ₄ , Y ₂ O ₃ , CeO ₂ , or organic materials such as BCB, polyimide, acryl, parylene C, PMMA, CYPE, etc. Can be used.

The organic semiconductor lamp 22 or the insulating layer is for channel formation of the present ferroelectric memory device.

The ferroelectric layer 23 is formed in a region corresponding to the gate electrode 21 on the organic semiconductor layer 22. At this time, the ferroelectric layer 23 is preferably composed of PVDF having β-phase crystals.

A drain electrode 24 and a source electrode 25 are formed on both sides of the ferroelectric layer 23 as upper electrodes.

In this case, as the drain electrode 24 and the source electrode 25, gold, silver, aluminum, platinum, indium tin compound (ITO), strontium titanate compound (SrTiO ₃ ), other conductive metal oxides, and alloys thereof And materials such as polyaniline, poly (3,4-ethylenedioxythiophene) / polystyrenesulfonate (PEDOT: PSS), compounds, or multilayers based on the compound or conductive polymer.

In the above structure, the ferroelectric layer 23 has a polarization characteristic according to the voltage applied to the gate electrode 21. In this case, the polarization characteristic of the ferroelectric layer 23 exhibits a polarity of approximately 5 μC / cm 2 to −5 μC / cm 2 with respect to the case where the applied voltage is 1 V to 1 V as described in FIG. 2. As a result, a predetermined channel is formed in the organic semiconductor layer 22 due to the polarization characteristic of the ferroelectric layer 23, so that the drain electrode 24 and the source electrode 25 are in a conductive or non-conductive state through the channel region. Will be set.

In general, a commercially available memory device has a 1T-1C (One Transistor-One Capacitor) structure. In these memory devices, data is written to or read from a capacitor through a method of charging or discharging a predetermined voltage to the capacitor through on / off of a transistor.

In the structure of this embodiment, the ferroelectric layer 23 has a predetermined polarization characteristic according to the voltage applied to the gate electrode 21, and this polarization characteristic is kept constant even when the voltage is cut off. Therefore, in the memory device according to the present embodiment, as shown in FIG. 4, the non-volatile memory device has a simple 1T structure in which the source electrode of the ferroelectric memory device 40 is grounded and data is read through the drain electrode. You can configure it.

Next, a manufacturing process of the ferroelectric memory device according to the present invention will be described with reference to FIG. 5.

A conductive layer 51 such as, for example, gold (Au) is deposited on a substrate 10 made of a paper or a plastic coated with a coding material such as a semiconductor wafer, parylene, or the like (FIGS. 5A and 5B), and spin is formed thereon. The photoresist 52 is applied by the coating method (FIG. 5C).

Subsequently, the photoresist 52 is removed except for only a portion for forming the gate electrode using a remover such as acetone, and the gate electrode 21 is formed by etching the conductive layer 51 using the mask as a mask. (FIG. 5D, FIG. 5E).

After removing the photoresist 52 on the gate electrode 21, an inorganic or organic semiconductor layer 22 is formed on the entire surface of the structure by spin coating (FIG. 5F), and the organic semiconductor layer 22 is formed. Is formed on the PVDF ferroelectric layer 23. In the formation of the ferroelectric layer 23, PVDF is formed at a temperature of, for example, 60 to 70 ° C, preferably about 65 ° C, or a temperature at which PVDF exhibits a beta phase as described above. PVDF is determined to be β by rapid cooling.

Subsequently, the ferroelectric layer except for the portion corresponding to the gate electrode 21 is removed using the photoresist 53 (FIGS. 5H to 5J). The photoresist 53 formed on the ferroelectric layer 23 is removed (FIG. 5K). Then, the photoresist 54 is applied on the ferroelectric layer 23 by the same method as described above, and the resulting conductive electrode made of gold, for example, is deposited on the drain electrode 24 and the source electrode 25. ), The photoresist 54 and the conductive layer 55 on the ferroelectric layer 23 are removed in a lift-off manner to form a memory device (FIGS. 5L to 5O).

In the above-described embodiment, the manufacturing process of the capacitor, which is generally required when manufacturing the memory device, is omitted. Therefore, manufacturing becomes easy, the manufacturing process is simplified, and the number of memory devices manufactured in a certain area can be greatly increased.

On the other hand, in the above embodiment, after the ferroelectric layer 23, i.e., the PVDF layer is formed, the crystal structure of the PVDF layer is determined to be beta phase by rapidly cooling the substrate 10 at a temperature at which the PVDF layer exhibits a beta phase. Done.

However, when the memory device is manufactured by the above method, the ferroelectric layer is formed by the heat applied to the substrate 10 when the ferroelectric layer 22 is formed and then the drain electrode 24 and the source electrode 25 are formed thereon. There is a fear that the crystal structure of the layer 23 is changed.

Therefore, the ferroelectric layer 23 is formed after all the memory manufacturing processes are completed by forming the drain electrode 24 and the source electrode 25 without setting the crystal structure of the ferroelectric layer 23 immediately after forming the ferroelectric layer 23. It may be desirable to establish a crystal structure. In other words, the structure after the drain electrode 24 and the source electrode 25 are formed is monotonously reduced to a temperature representing the β phase after the ferroelectric layer 23 is heated above the temperature representing the β phase, or the structure It is preferable to set the crystal structure of the ferroelectric layer 23 by heating the ferroelectric layer 23 to a temperature exhibiting the β phase and then rapidly cooling the structure.

The embodiment according to the present invention has been described above. However, the above-described embodiment shows one preferred embodiment according to realizing the present invention, the present invention can be carried out in various modifications within the scope without departing from the basic concept and spirit.

For example, in the above-described embodiment, the structure in which the ferroelectric layer 23 is bonded to the gate electrode 21 through the organic semiconductor layer 22 as the structure of the semiconductor device is described as an example.

However, the ferroelectric memory device according to the present invention may be implemented by adopting various structures in addition to the above-described structure.

For example, FIG. 6 illustrates various structures of a semiconductor device that can be implemented according to the present invention.

6 shows the organic semiconductor layer 22 formed on the opposite side of the ferroelectric layer 23 facing the gate electrode 21 while directly coupling the gate electrode 21 and the ferroelectric layer 23. 6a shows a staggered structure, FIG. 6b shows an inverted staggered structure, FIG. 6c shows a coplanar structure, and FIG. 6d shows an inverted coplanar structure. It is shown. In FIG. 6, the same reference numerals are added to the corresponding parts in FIG. 3.

In the structure shown in FIG. 6, when a constant voltage is applied to the gate electrode 21, polarization occurs in the steel dielectric layer 23, so that a channel is formed in the organic semiconductor layer 22. The drain electrode 24 and the source electrode 25 are set to the conductive state or the non-conductive state through the channel formed as described above.

In the structure of FIG. 6, an insulating layer may be used instead of the organic semiconductor layer 22. That is, the organic semiconductor layer 22 may be in any form that can form a channel according to the voltage applied thereto.

In addition, in the embodiment of FIG. 3, the present invention has been described using the inverted staggered structure as an example, but the same applies to the staggered structure, the coplanar structure, and the inverted coplanar structure. .

As described above, according to the present invention, an organic substance is used as the ferroelectric material. As a result, it is easier to manufacture and lower in cost than a ferroelectric memory device using a conventional inorganic material. In addition, PVDF having a crystal structure of β phase according to the present invention exhibits a polarization characteristic at a low voltage, thereby realizing a nonvolatile memory capable of operating at a very low voltage.

Claims (19)

A substrate, a gate electrode, a drain and source electrode, a channel forming layer, and a ferroelectric layer, The ferroelectric layer is composed of a PVDF layer having a crystal structure of β phase, And a channel forming layer is formed between the gate electrode and the ferroelectric layer. The method of claim 1, And the channel forming layer is an organic semiconductor layer. The method of claim 1, And the channel forming layer is an insulating layer. The method of claim 1, The substrate is polyimide (PI), polycarbonate (PC), polyether sulfone (PES), polyether ether ketone (PEEK), polybutylene terephthalate (PBT), polyethylene terephthalate (PET), polyvinyl chloride ( PVC), polyethylene (PE), ethylene copolymer, polypropylene (PP), propylene copolymer, poly (4-methyl-1-pentene) (TPX), polyarylate (PAR), poly acetal (POM), poly Phenylene oxide (PPO), polysulfone (PSF), polyphenylene sulfide (PPS), polyvinylidene chloride (PVDC), polyvinyl acetate (PVAC), polyvinyl alcohol (PVAL), polyvinyl acetal, polystyrene (PS ), AS resin, ABS resin, polymethyl methacrylate (PMMA), fluorine resin, phenol resin (PF), melamine resin (MF), urea resin (UF), unsaturated polyester (UP), epoxy resin (EP) Consisting of diallyl phthalate resin (DAP), polyurethane (PUR), polyamide (PA), silicone resin (SI) or mixtures and compounds thereof A ferroelectric memory device, characterized in that. The method of claim 1, And the substrate is made of a material including paper. The method of claim 1, And the insulating layer is an organic material. A substrate, a gate electrode, a drain and source electrode, a channel forming layer, and a ferroelectric layer, The ferroelectric layer is composed of a PVDF layer having a crystal structure of β phase, A ferroelectric memory device, characterized in that a ferroelectric layer is formed between the gate electrode and the channel forming layer. The method of claim 7, wherein And the channel forming layer is an organic semiconductor layer. The method of claim 7, wherein And the channel forming layer is an insulating layer. The method of claim 7, wherein The substrate is polyimide (PI), polycarbonate (PC), polyether sulfone (PES), polyether ether ketone (PEEK), polybutylene terephthalate (PBT), polyethylene terephthalate (PET), polyvinyl chloride ( PVC), polyethylene (PE), ethylene copolymer, polypropylene (PP), propylene copolymer, poly (4-methyl-1-pentene) (TPX), polyarylate (PAR), polyacetal (POM), poly Phenylene oxide (PPO), polysulfone (PSF), polyphenylene sulfide (PPS), polyvinylidene chloride (PVDC), polyvinyl acetate (PVAC), polyvinyl alcohol (PVAL), polyvinyl acetal, polystyrene (PS ), AS resin, ABS resin, polymethyl methacrylate (PMMA), fluorine resin, phenol resin (PF), melamine resin (MF), urea resin (UF), unsaturated polyester (UP), epoxy resin (EP) Consisting of diallyl phthalate resin (DAP), polyurethane (PUR), polyamide (PA), silicone resin (SI) or mixtures and compounds thereof The ferroelectric memory device according to claim. The method of claim 7, wherein And the substrate is made of a material including paper. The method of claim 7, wherein And the insulating layer is an organic material. A semiconductor device manufacturing method comprising a substrate, a gate electrode, a drain and source electrode, a channel forming layer, and a ferroelectric layer, Forming a gate electrode; Forming a channel forming layer, Forming a ferroelectric layer, Forming a drain and a source electrode, And a ferroelectric layer phase transition step of setting the ferroelectric layer to β phase. The method of claim 13, And the channel forming layer is formed between the gate electrode and the ferroelectric layer. The method of claim 13, And the ferroelectric layer is formed between the gate electrode and the channel forming layer. The method of claim 13, The ferroelectric layer phase transition step may include a first step of raising the temperature of the ferroelectric layer to a temperature higher than or more to form a β phase crystal; A second step of monotonically reducing the temperature of the ferroelectric layer to the β phase crystal temperature; And a third step of rapidly lowering the temperature of the ferroelectric layer. The method of claim 13, The phase transition step of the ferroelectric layer is a first step of raising the temperature of the ferroelectric layer to a temperature forming a β phase crystal, And a second step of rapidly lowering the temperature of the ferroelectric layer. The method of claim 13, The ferroelectric layer is a method of manufacturing a ferroelectric memory device, characterized in that the PVDF layer. The method of claim 13, And the ferroelectric layer phase transition step is performed after forming a gate electrode, a source and a drain electrode.

Images