KR20060113810A - Method for fabricating cmos image sensor - Google Patents

Abstract

A method for manufacturing a CMOS image sensor is provided to reduce the capacitance of a floating diffusion region and to increase a conversion gain by using an ion implantation barrier layer. A plurality of gate electrodes(208) are formed on a semiconductor substrate(201). An ion implantation barrier layer(210) for blocking a photodiode region and a floating diffusion region is formed on the resultant structure. A low ion implantation and a halo ion implantation are sequentially performed on the resultant structure. Then, the ion implantation barrier layer is eliminated therefrom. A spacer is formed at both sidewalls of each gate electrode.

Description

Manufacturing method of CMOS image sensor {METHOD FOR FABRICATING CMOS IMAGE SENSOR}

1A to 1C are cross-sectional views illustrating a manufacturing process of the CMOS image sensor according to the prior art.

2A to 2C are cross-sectional views illustrating a CMOS image sensor according to an exemplary embodiment of the present invention.

3a and 3b are plan views showing the manufacturing process of the CMOS image sensor according to the present invention.

4A and 4B show simulation results for charge transfer efficiency.

Explanation of symbols on the main parts of the drawings

201: p + substrate 202: p- epi layer

203 p-type wafer 204 device isolation film

205 well 206 gate insulating film

207: gate conductive film 208: gate electrode

209: photodiode 211: low concentration impurity region

213: second impurity implantation prevention film 214: high concentration impurity region

215 halo impurity region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a manufacturing process of CMOS image sensors during a semiconductor device manufacturing process.

In general, image sensors are used in a wide range of fields, from home products such as digital cameras and mobile phones, to endoscopes used in hospitals, and to satellite telescopes around the earth. The CMOS image sensor is a device that converts an optical image into an electrical signal, and employs a switching method in which a MOS transistor is formed by the number of pixels and the output is sequentially detected using the MOS transistor. The CMOS image sensor is simpler to drive than the CCD image sensor, which is widely used as a conventional image sensor, enables various scanning methods, and can integrate signal processing circuits onto a single chip. In addition to the use of compatible CMOS technology, the manufacturing cost can be lowered and the power consumption is significantly lower. Therefore, it is used in low cost and low power fields such as mobile phones, PCs and surveillance cameras.

1A to 1C are cross-sectional views illustrating a manufacturing process of the CMOS image sensor according to the prior art.

The manufacturing process of the CMOS image sensor according to the prior art first, as shown in Figure 1a, the active region and the device isolation on the p-type wafer 103, the p- epi layer 102 is formed on the p + type substrate 101 An isolation layer 104 is formed to separate regions.

At this time, the reason for using the low concentration of the p- type epi layer 102 on the high concentration p + type substrate 101, first, because the low concentration of p- epi layer 102 is present in the depletion region (Depletion region) of the photodiode Can be increased greatly and deeply to increase the photodiode's ability to collect photocharges. Secondly, having a high concentration of the p + type substrate 101 under the p-type epilayer 102, This is because the charge is quickly recombined before the charge spreads to the neighboring pixel, thereby reducing the random diffusion of the photocharge, thereby reducing the change in the transfer function of the photocharge.

In addition, although the device isolation layer 104 is formed through the STI process in the drawing, the device isolation layer 104 may be formed by a LOCOS process or the like.

Subsequently, a p well region 105 in which the gate electrode for the drive transistor Dx and the gate electrode for the select transistor Sx are formed is formed on the p-type wafer 103 on which the device isolation film 104 is formed.

Subsequently, the gate insulating film 106 and the gate conductive film 107 are sequentially deposited on the p-type wafer 103 on which the device isolation film 104 is formed, and then selectively etched to form four transistor gate electrodes 108. To form.

In this case, the gate electrodes 018 for the four transistors are the gate electrode for the transfer transistor Tx, the gate electrode for the reset transistor Rx, the gate electrode for the drive transistor Dx, and the gate electrode for the select transistor Sx. It is said to be aligned.

Subsequently, an impurity is implanted to self-align with an edge portion of the gate electrode for the transfer transistor Tx among the gate electrodes 108 to form a photodiode 109.

Subsequently, an impurity implantation prevention layer 110 covering a portion of the photodiode 109 and the gate electrode for the transfer transistor Tx is formed.

Subsequently, a low concentration impurity implantation process is performed on the p-type wafer 201 on which the impurity implantation prevention film 110 is formed, so that low concentration impurities are formed on the p-type wafer 103 on both sides of the four transistor gate electrodes 208. The region 111 is formed.

Next, a halo impurity region 112 is formed by performing a halo impurity implantation process on the substrate on which the low concentration impurity region 111 is formed, and spacers 114 are formed on both sidewalls of the four transistor gate electrodes 208. do.

Subsequently, a high concentration impurity implantation process is performed on the p-type wafer 101 by using the impurity implantation prevention film 110, so that the gate electrodes 208 of the four transistors except for one side of the gate electrode for the transfer transistor Tx are removed. High concentration impurity regions 113 are formed in the p-type wafers 103 on both sides.

That is, in the related art, although the transfer transistor Tx can sufficiently increase the channel length of the transfer transistor Tx to a certain level in relation to charge transfer efficiency and uniformity, punch-through characteristics In consideration of this concern, a low concentration impurity implantation process and a halo impurity implantation process were performed in the transfer transistor Tx.

Thus, not only does a potential barrier defect from the photodiode 109 to the transfer transistor Tx, but also the capacitance of the floating diffusion region increases.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and an object thereof is to provide a method for manufacturing a CMOS image sensor that increases charge transfer efficiency.

According to an aspect of the present invention for achieving the above object, forming a plurality of gate electrodes including a gate electrode for the transfer transistor on a semiconductor substrate, the photodiode region and the other side of one side of the gate electrode for the transfer transistor Forming an impurity implantation prevention film to prevent low concentration impurity implantation and halo impurity implantation on a substrate in the floating diffusion region, and sequentially performing a low concentration impurity implantation process and a halo impurity implantation process on the substrate on which the impurity implantation prevention film is formed Removing the impurity implantation prevention film, forming spacers on both sidewalls of the transfer transistor gate electrode and the plurality of gate electrodes, and forming both spacers on both sides of the gate electrode and the plurality of gate electrodes of the transfer transistor on which the spacer is formed. On board It is also provided a method for manufacturing a CMOS image sensor for performing a doping process.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A to 2C are cross-sectional views illustrating a CMOS image sensor according to an exemplary embodiment of the present invention.

In the CMOS image sensor according to an exemplary embodiment of the present invention, first, as shown in FIG. 2A, an active region and a device are separated on a p-type wafer 203 having a p− epitaxial layer 202 formed on a p + type substrate 201. An isolation layer 204 is formed to separate regions.

At this time, the reason why the low concentration of the p-type epi layer 202 is used on the high concentration p + type substrate 201 is as follows. First, since the low concentration of the p-type epitaxial layer 202 exists, a depletion region of the photodiode is used. Can be increased greatly and deeply to increase the photodiode's ability to collect photocharges, and secondly, having a high concentration of p + type substrate 201 under the p-type epilayer 202, This is because the charge is quickly recombined before the charge spreads to the neighboring pixel, thereby reducing the random diffusion of the photocharge, thereby reducing the change in the transfer function of the photocharge.

In addition, although the device isolation layer 204 is formed through the STI process in the drawing, it may be formed by a LOCOS process or the like.

Subsequently, a p well region 205 on which the gate electrode for the drive transistor Dx and the gate electrode for the select transistor Sx are to be formed is formed on the p-type wafer 203 on which the device isolation layer 204 is formed.

Subsequently, the gate insulating film 206 and the gate conductive film 207 are sequentially deposited on the p-type wafer 203 on which the device isolation film 204 is formed, and then selectively etched to form four transistor gate electrodes 208. To form.

In this case, the gate electrodes 208 for the four transistors are a gate electrode for a transfer transistor (Tx), a gate electrode for a reset transistor (Rx), a gate electrode for a drive transistor (Dx), and a gate electrode for a select transistor (Sx). It is said to be aligned.

Subsequently, an impurity is implanted to self-align with an edge portion of the gate electrode for the transfer transistor Tx among the gate electrodes 208 to form a photodiode 209.

Subsequently, the first impurity includes the photodiode 209 and the gate electrode for the transfer transistor Tx, and also includes a substrate between the gate electrode for the transfer transistor Tx and the gate electrode for the reset transistor Rx. An injection barrier 210 is formed.

In this case, the first impurity implantation prevention film 210 is a prevention film for improving charge transfer efficiency by preventing low concentration impurity implantation and halo impurity implantation into the p-type wafer 201 on both sides of the gate electrode for the transfer transistor Tx.

Subsequently, a low concentration impurity implantation process is performed on the p-type wafer 201 on which the first impurity implantation prevention film 210 is formed, so that the gate electrodes 208 of the three transistors except for the gate electrode for the transfer transistor Tx are formed. Low concentration impurity regions 211 are formed in the p-type wafers 203 on both sides.

Next, a halo impurity region 215 is formed by performing a halo impurity implantation process on the substrate on which the low concentration impurity region 211 is formed.

Subsequently, the first impurity implantation prevention film 210 is removed.

Next, as illustrated in FIG. 2C, the second impurity implantation prevention film including the photodiode 209 on the substrate from which the first impurity implantation prevention film 210 is removed and covering a part of the gate electrode for the transfer transistor ( 213).

Subsequently, a high concentration impurity implantation process is performed on the p-type wafer 201 on which the second impurity implantation prevention film 213 is formed, so that four transistor gate electrodes 208 except one side of the gate electrode for transfer transistor Tx are formed. A high concentration impurity region 214 is formed in the p-type wafer 203 on both sides of the substrate.

3A and 3B are plan views illustrating a manufacturing process of the CMOS image sensor according to the present invention.

In the manufacturing process of the CMOS image sensor according to the present invention, first, as shown in FIG. 3A, all regions except for the region where the reset transistor Rx, the driver transistor Dx, and the select transistor Sx are formed are covered. It can be seen that the first impurity implantation prevention mask 301 is formed.

Next, as shown in FIG. 3B, the second impurity implantation prevention mask covering all regions except for the region in which the transfer transistor Tx, the reset transistor Rx, the driver transistor Dx, and the select transistor Sx are formed ( It can be seen that 302 is formed.

That is, low concentration and halo impurity regions are not formed by the first impurity implantation prevention mask 301 on one side of the transfer transistor Tx, and high concentration impurity regions are formed by the second impurity implantation prevention mask 302.

If the low concentration and halo impurity regions are not formed on one side of the transfer transistor Tx as described above, the floating diffusion region is reduced in the saturation level and sensitivity due to the limitation of the pixel size. By reducing the capacitance of the (FD) it can increase the conversion margin (Conversion Gain), it can also maximize the efficiency of charge transfer from the photodiode (PD) to the transfer transistor (Tx).

Here, the conversion margin will be described. The CMOS image sensor transfers the photocharge generated in the photodiode to the floating diffusion region, and reproduces the image by using the charge displacement of the floating diffusion region.

In this case, the smaller the capacitance of the floating diffusion region is, the larger the potential change amount of the floating diffusion region changed by the photocharges transmitted from the photodiode is. In other words, the rate at which the photocharge generated by light changes to an electrical signal increases. This is also called a conversion margin, which is one of the important performance factors that determine the characteristics of the CMOS image sensor.

4A and 4B show simulation results of charge transfer efficiency, and compare the present invention with the prior art through this drawing.

First, as shown in FIG. 4A, the CMOS image sensor according to the related art forms a low concentration impurity region and a halo impurity region on one side of a gate electrode for a transfer transistor for the purpose of defending against punch through.

In this case, the punch-through characteristic improvement cannot be considered independently due to the increase in the length of the transfer transistor Tx channel, and the halo impurity region is formed on the charge transfer path from the photodiode PD to the transfer transistor Tx. It acts as a Potential Barrier (see a dotted circle), degrading dead zone characteristics.

Next, as shown in FIG. 4B, the CMOS image sensor according to the present invention can eliminate the potential barrier defects by forming a low concentration impurity region and a halo impurity region in the transfer transistor. Therefore, by improving the fringing field on the path from the photodiode PD to the transfer transistor Tx and significantly reducing the potential barrier, the dead zone characteristic directly related to the low light characteristic of the image sensor is improved. Let's do it.

In addition, the capacitance of the floating diffusion region is reduced to a considerable level (10 to 20%), thereby increasing the dynamic range of the image sensor (maximum voltage change at which the output stage outputting the sensing result of the unit pixel can be moved). And direct improvement in photosensitivity.

In this case, the channel length of the transfer transistor Tx preferably has a size of 0.5 μm or more sufficient to exclude the influence of punch-through.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the present invention does not form the low concentration impurity region and the halo impurity region on one side of the transfer transistor, thereby lowering the capacitance of the floating diffusion region to increase the conversion margin.

Therefore, the charge transfer efficiency is increased due to the increased conversion margin.

In addition, the potential barrier defect caused by the halo impurity region is removed to improve the fringing field on the path from the photodiode PD to the transfer transistor Tx and the direct zone characteristic directly related to the low light characteristic of the image sensor. Improves.

In addition, the capacitance of the floating diffusion region is reduced to a considerable level (10-20%), which contributes directly to the increase of the dynamic range of the image sensor and the improvement of the photosensitivity.

Claims (2)

Forming a plurality of gate electrodes including gate electrodes for transfer transistors on the semiconductor substrate; Forming an impurity implantation prevention film to prevent low concentration impurity implantation and halo impurity implantation in a substrate of a photodiode region on one side of the transfer transistor gate electrode and a floating diffusion region on the other side; Sequentially performing a low concentration impurity implantation process and a halo impurity implantation process on the substrate on which the impurity implantation prevention film is formed; Removing the impurity implantation prevention film; Forming a spacer on both sidewalls of the transfer transistor gate electrode and the plurality of gate electrodes; And Performing a high concentration impurity implantation process on a gate electrode of the transfer transistor having the spacer formed thereon and a substrate on both sides of the gate electrode; Method of manufacturing a CMOS image sensor comprising a. The method of claim 1, And the transfer transistor has a channel length of 0.5 μm or more.

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