KR20060113287A - Semiconductor device with step gate and method for manufacturing the same - Google Patents

Abstract

A semiconductor device with a step gate is provided to avoid a slope phenomenon of a step gate by shifting a step gate to a portion over an isolation layer such that the step gate is defined as a wave type. An isolation layer and an active region are formed in a predetermined region of a semiconductor substrate. The active region has a first area(23a) with a high step and a second area(23b) with a low step by a recess(27). A step gate is formed on the first and second areas, vertically crossing the active region. A part(SG1) of the step gate passing through a portion over the active region is of a line type, and a part(SG2) of the step gate passing through a portion over the isolation layer is of a wave type that doesn't overlap the edge of an adjacent active region. A polysilicon layer, a silicide layer and a gate hard mask are sequentially stacked in the step gate.

Description

A semiconductor device having a step gate, and a manufacturing method therefor {SEMICONDUCTOR DEVICE WITH STEP GATE AND METHOD FOR MANUFACTURING THE SAME}

1 is a plan view of a semiconductor device according to the prior art,

2A is a cross-sectional view taken along the line II ′ of FIG. 1;

Figure 2b is a view showing the slope shape of the step gate according to the prior art,

3A is a plan view showing the structure of a semiconductor device according to an embodiment of the present invention;

3B is a cross-sectional view taken along line II ′ of FIG. 3A;

4A and 4B are cross-sectional views of the manufacturing process of the semiconductor device, taken along line II ′ of FIG. 3A.

Figure 5a is a result of checking the slope shape of the step gate and its line width variation,

Figure 5b is the result of measuring the line width of the step gate inline and the value of each wafer position.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 device isolation film

23: active area 23a: first zone

23b: Second Area 27: Recess

SG1, SG2: Step Gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a semiconductor device using a STAR process.

As the integration of semiconductor devices such as DRAM increases, the increase in cell charge and the improvement of refresh characteristics have a direct relationship with the reliability of the semiconductor device, and refresh improvement is essential to overcome the limitations of the device.

In the general semiconductor device process, the gate size should be increased to improve the refresh characteristics, but it is limited in design rules, and the boron concentration of the channel region is limited.

Therefore, a method of increasing the gate length in order to maintain the concentration of boron and improve refresh has been proposed.

As a method of increasing the gate length as described above, a semiconductor device using a STAR (STep gated asymmetry recess) process is proposed in which an active region under a gate has a step.

1 is a plan view of a semiconductor device according to the prior art, FIG. 2A is a cross-sectional view taken along the line I-I 'of FIG. 1, and FIG. 2B is a view showing the slope shape of the step gate according to the prior art.

As shown in FIG. 1 and FIG. 2A, the semiconductor device according to the related art includes a semiconductor substrate 11, a device isolation film 12 having a trench structure formed in a predetermined region of the semiconductor substrate, and a step difference between the semiconductor substrate 11. An active region 13 having a first region 13a and a second region 13b, and is formed on the upper boundary region of the first region 13a and the second region 13b of the active region 13, and one side The step gate 100 extends to a portion of the first region 13a and the other side extends to a portion of the second region 13b and has a step structure.

1 and 2A, the first region 13a and the second region 13b of the active region 13 are different from each other by forming the recess 101 by the STAR process. ) Is the region where the bit line is to be contacted, and the second region 13b is the region to which the storage node is connected.

In the prior art as shown in FIGS. 1 and 2A, since the active region has an asymmetrical structure, the step gate 100 has an asymmetrical shape, a portion passing over the active region has a line shape, and an upper portion of the boundary region between the active region and the device isolation layer. The passing portion has a wave shape (Wave, W) that is curved in the form of a wave (Wave).

However, the prior art has a problem that LPC not open occurs due to lack of space in the LPC contact opening due to the deformation of the step gate.

The reason why the LPC may open is due to the etching of the semiconductor substrate 11 for improving the refresh, and the thickness of the polysilicon 14 and the silicide 15 increases in part of the active region by the etching of the semiconductor substrate 11. As the number of the etch targets increases, the silicide 15 and the polysilicon 14 forming the step gate 100 have a slope shape (see FIG. 2B).

Simultaneously with this reason, the slope degree increases as the end of the gate line overlaps the FOX bordering area in the active region as shown in FIG. 2B. In the case of a gate line overlapped with an active region, even a polysilicon / silicide having the same thickness shows a more vertical shape.

This abnormal slope shape reduces the spacing between the step gates and provides a cause for the subsequent opening of subsequent LPC contact hole definitions.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor device and a method of manufacturing the same, which can prevent slope profile degradation of silicide / polysilicon constituting a step gate.

The semiconductor device of the present invention for achieving the above object is to provide a semiconductor substrate, an element isolation film and an active region formed in a predetermined region of the semiconductor substrate, the active region has a first region having a high step and a second region having a low step. A recess and a cross-section perpendicular to the active region over the first region and the second region, wherein the portion passing over the active region is in a line shape and the portion passing over the device isolation layer is an adjacent active region. It characterized in that it comprises a step gate having a wave shape so as not to overlap the edge.

In the method of manufacturing a semiconductor device of the present invention, a device isolation film is formed in a predetermined region of a semiconductor substrate, and the active region defined by the device isolation film is divided into a first region having a high step and a second region having a low step. Forming a recess, and a portion of the first region and the second region passing through the upper portion of the active region has a line shape, and a portion of the portion passing through the upper portion of the device isolation layer does not overlap an edge of an adjacent active region. Forming a step gate having a shape is characterized in that it comprises.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3A is a plan view showing the structure of a semiconductor device according to an embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along line II to II 'of FIG. 3A.

As shown in FIG. 3A, a semiconductor device according to an exemplary embodiment of the present inventive concept may include an isolation layer 22 and an active region 23 having a trench structure to define an active region 23 in a predetermined region of a semiconductor substrate 21. A wave form formed over the recess 27 and the first region 23a and the second region 23b, which provide a first region 23a and a second region 23b having different steps by etching a portion of the Step gates SG1 and SG2 are included.

Referring to FIG. 3B, a device isolation layer 22 having a trench structure defining an active region 23 is formed in a predetermined region of the semiconductor substrate 21, and the first region 23a having a high step height between the active regions 23 is formed. And a recess 27 is formed over the edge portion of the active region 23 and a predetermined portion of the device isolation film 22, and is formed by the recess 27. Step gates SG and 1 SG2 are formed over the first region 23a and the second region 23b. Here, the step gates SG1 and SG2 are stacked in the order of the polysilicon layer 29, the silicide layer 30, and the gate hard mask nitride layer 31, and the gate oxide layer 28 is formed under the step gates SG1 and SG2. ) Is formed.

As shown in FIGS. 3A and 3B, in the semiconductor device of the present invention, the active region 23 is divided into a first region 23a and a second region 23b by the recess 27, and the first region ( Step gates SG1 and SG2 having a step structure are formed above the boundary area between 23a) and the second region 23b.

Here, the step gates SG1 and SG2 are divided into 'SG1' passing through the active region 23 and 'SG2' passing through the device isolation layer 22, and 'SG2' passing through the upper portion of the device isolation layer 22 is active. In the region bordering between the region 23 and the device isolation layer 22, the shifter S is shifted toward the device isolation layer 22. In addition, 'SG1' passing through the active region 23 has a line shape, and 'SG2' passing through the device isolation layer 22 has a wave shape, and 'SG2' becomes a device isolation film 22 by further strengthening the wave shape. You will have a structure that is shifted toward). That is, 'SG2' is shifted so as not to overlap the edge of the adjacent active region.

4A and 4B are cross sectional views of the manufacturing process of the semiconductor device, taken along line II-II ′ of FIG. 3A.

As shown in FIG. 4A, the device isolation layer 22 is formed in a predetermined region of the semiconductor substrate 21 using an STI process. The active region 23 is defined by the device isolation layer 22.

Subsequently, after the sacrificial oxide film 24 is formed on the semiconductor substrate 21, the anti-reflection film 25 is formed on the sacrificial oxide film 24.

Next, a photosensitive film is coated on the antireflection film 25 and patterned by exposure and development to form a STAR mask 26. Here, the photoresist used as the STAR mask 26 is made of a cyclo Olefin-Maleic Anhydric (COMA) or an acrylate (Acrylate) polymer material.

Subsequently, the anti-reflection film 25 is etched using the STAR mask 26 as an etch barrier, and the sacrificial oxide film 24 is subsequently etched to open the surface of the active region 23 of the semiconductor substrate 21.

Next, the active region 23 of the semiconductor substrate 21 exposed after the sacrificial oxide film 24 is etched using the STAR mask 26 as an etch barrier is etched to a predetermined depth to form a recess 27 for the step gate. At this time, the etching process for forming the recess 27 proceeds with a mixed gas of HBr / Cl ₂ / O ₂ .

As described above, when the recess 27 is formed, the active region 23 is divided into a first region 23a having a high surface and a second region 23b having a lower surface than the first region 23a. In the DRAM, the first region 23a is an active region to which a bit line is connected, and the second region 23b is an active region to which a storage node is connected, and the active region 23 has an asymmetric structure.

Preferably, the depth d of the recess 27 is in the range of 200 kPa to 600 kPa.

As shown in FIG. 4B, the STAR mask 26 and the antireflection film 25 are simultaneously stripped, and the sacrificial oxide film 24 is successively removed.

Next, the ion implantation process for adjusting the threshold voltage on the front. In this case, although the ion implantation process for adjusting the threshold voltage is not shown, the screen oxide film is formed in a dry oxidation process in a temperature range of 800 ° C. to 1000 ° C., and the screen oxide film is formed after the ion implantation process. Strip.

Next, after the screen oxide film is stripped, the gate oxide film pre-cleaning process is performed, and the gate oxide film 28 is formed on the entire surface. At this time, the gate oxide film 28 is formed to a thickness of 100 ~ 150Å by a dry oxidation process at a temperature in the range of 850 ℃ to 1000 ℃.

Subsequently, a polysilicon film 29, a silicide film 30, and a gate hard mask nitride film 31 are formed on the gate oxide film 28 by lamination.

Next, a photoresist film is applied on the gate hard mask nitride film 31 and patterned by exposure and development to form a gate mask 32.

Subsequently, the gate hard mask nitride layer 31, the silicide layer 30, and the polysilicon layer 39 are sequentially etched using the gate mask 32 as an etch barrier to form step gates SG1 and SG2.

As such, the step gate SG1 formed on the active region 23 among the step gates SG1 and SG2 is formed over a predetermined portion in the first region 23a and the second region 23b having different steps. In addition, the step gate SG2 formed at the border region between the active region 23 and the device isolation layer 22 is formed at a position different from that of the conventional step gate. The step gates SG1 and SG2 are divided into 'SG1' passing through the active region 23 and 'SG2' passing through the device isolation layer 22, and 'SG2' passing through the upper portion of the device isolation layer 22 is active. In the region bordering between the region 23 and the device isolation layer 22, the shifter S is shifted toward the device isolation layer 22. In addition, 'SG1' passing through the active region 23 has a line shape, and 'SG2' passing through the device isolation layer 22 has a wave shape, and 'SG2' becomes a device isolation film 22 by further strengthening the wave shape. You will have a structure that is shifted toward). That is, the 'SG2' formed at the boundary between the active region 23 and the device isolation layer 22 is shifted toward the device isolation layer 23 (see Shift, 'S') so as not to span the adjacent active region 23. .

FIG. 5A shows that the step gate is artificially finely defined so that the step gate is finely defined on the device isolation layer, and the slope shape of the step gate and the variation of the line width are checked through the cross-sectional analysis and the inline line width measuring apparatus. to be.

Referring to FIG. 5A, it can be seen that when the step gate is shifted over the device isolation layer in the existing active region / device isolation region, it shows a more vertical shape.

5B is a line width of the step gate is measured inline, and the value is measured for each wafer position.

Referring to FIG. 5B, it can be seen that the solid line is the present invention and the dotted line is the prior art, and the amplitude is reduced from about 25 nm to 20 nm or less, that is, the amplitude is improved. This indicates the degree of slope change of the step gate. If the slope degree is severe, the line width of the step gate increases, and if the slope degree decreases, the line width of the step gate decreases.

The decrease in line width increases and decreases the effect of the change in the conventional active region / device isolation region.

In the prior art, as shown in FIG. 2A, the step gate is laid out so that two lines are positioned over the active region and the gate line passes over the active region and the device isolation region.

However, in the present invention, the step gate positioned in the active region and the region of the device isolation layer is completely shifted onto the device isolation layer 22 ('S'). That is, the slope of the step gate is prevented by defining the step gate on the device isolation layer in the form of more waves as shown in FIG. 3B.

The prevention of slope increases the open area of subsequent LPC contact holes and decreases the fluctuations to have a stable value of the open area, thereby increasing the process margin for existing LPC better open.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has the effect of preventing the wide open of the LPC contact by shifting the step gate above the device isolation layer and defining a wave shape to prevent the slope of the step gate to widen the gap between the step gates. .

Claims (6)

Semiconductor substrates; An isolation layer and an active region formed in a predetermined region of the semiconductor substrate; A recess such that the active region has a first region having a high step and a second region having a low step; And The first region and the second region are formed in a shape perpendicular to the active region, wherein a portion passing over the active region is in a line shape and a portion passing over the device isolation layer overlaps an edge of an adjacent active region. Step gates with a wave shape to prevent Semiconductor device comprising a. The method of claim 1, The wave shape of the step gate is And a predetermined distance from an edge of the adjacent active region. The method of claim 1, The step gate, A semiconductor device characterized by being laminated in the order of a polysilicon film, a silicide film, and a gate hard mask. Forming an isolation layer in a predetermined region of the semiconductor substrate; Forming a recess that divides the active region defined by the device isolation layer into a first region having a high step and a second region having a low step; And A portion of the first region and the second region passing through the upper portion of the active region has a line shape, and a portion of the portion passing through the upper portion of the device isolation layer forms a wave shaped step gate so as not to overlap an edge of an adjacent active region. step Method for manufacturing a semiconductor device comprising a. The method of claim 4, wherein Forming the step gate, Stacking a polysilicon film, a silicide film, and a gate hard mask nitride film on the entire surface including the recess in order; Forming a gate mask on the gate hard mask nitride layer; And Etching the gate hard mask nitride layer, the silicon layer, and the polysilicon layer using the gate mask as an etch barrier Method for manufacturing a semiconductor device comprising a. The method according to claim 4 or 5, The wave shape of the step gate is And a predetermined distance from an edge of the adjacent active region.

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