KR20060111791A - Method for fabricating cmos image sensor - Google Patents

Abstract

A method for fabricating a CMOS image sensor is provided to prevent a threshold voltage from being lowered by forming an etch compensation layer so that a gate electrode of a transfer transistor with an effective line width is formed. A gate conductive layer(203) for a transfer transistor and a hard mask layer are sequentially deposited on a substrate. The hard mask layer is selectively etched. An etch compensation layer(207) made of a SiON-based layer is formed on the sidewall of the hard mask layer to compensate for the line width reduced by the etch process. By using the hard mask layer having the etch compensation layer as an etch barrier, the gate conductive layer for the transfer transistor is etched to form a gate electrode of the transfer transistor. By an ion implantation process using the hard mask layer as a barrier, a photodiode impurity region(209) aligned with the edge of the gate electrode of the transfer transistor is formed in the substrate.

Description

Manufacturing method of CMOS image sensor {METHOD FOR FABRICATING CMOS IMAGE SENSOR}

1A to 1C are cross-sectional views illustrating a manufacturing process of the CMOS image sensor according to the prior art.

2a to 2c are cross-sectional views showing the manufacturing process of the CMOS image sensor according to the present invention.

Explanation of symbols on the main parts of the drawings

201: semiconductor substrate 202: gate insulating film

203: conductive film for gate of transfer transistor

204: nitride film for hard mask 205: antireflection film

207: etching compensation layer 209: photodiode impurity region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a manufacturing process of a CMOS image sensor during a semiconductor device manufacturing process.

In general, image sensors are used in a wide range of fields, from home products such as digital cameras and mobile phones, to endoscopes used in hospitals, and to satellite telescopes around the earth. The CMOS image sensor is a device that converts an optical image into an electrical signal, and employs a switching method in which a MOS transistor is formed by the number of pixels and the output is sequentially detected using the MOS transistor. The CMOS image sensor is simpler to drive than the CCD image sensor, which is widely used as a conventional image sensor, enables various scanning methods, and can integrate signal processing circuits onto a single chip. In addition to the use of compatible CMOS technology, the manufacturing cost can be lowered and the power consumption is significantly lower. Therefore, it is used in low cost and low power fields such as mobile phones, PCs and surveillance cameras.

1A to 1C are cross-sectional views illustrating a manufacturing process of the CMOS image sensor according to the prior art.

In the manufacturing process of the CMOS image sensor according to the related art, first, as shown in FIG. 1A, a gate insulating layer 102 and a gate conduction are formed on a semiconductor substrate 101 on which an isolation layer separating an active region and an isolation region is formed. The film 103, the hard mask nitride film 104, and the antireflection film 105 are sequentially deposited.

At this time, the anti-reflection film 105 is preferably a SiON film.

The hard mask nitride film 104 and the antireflection film 105 are designated as hard mask layers.

Subsequently, a photoresist pattern 106 is formed on the antireflection film 105.

Next, as shown in FIG. 1B, the hard mask layer is etched using the photoresist pattern 106 as an etch barrier.

At this time, due to the difference in the etching selectivity between the photoresist pattern 106 and the hard mask layer, the photoresist pattern 106 is damaged to form a hard mask layer having a line width smaller than a desired line width.

Subsequently, the gate conductive layer 103 and the gate insulating layer 102 are etched using the etched hard mask layer as an etch barrier to form a gate electrode of a transfer transistor.

As mentioned above, the gate electrode of the transfer transistor is also formed with a line width smaller than the desired line width A by the difference in the etching selectivity between the photoresist pattern 106 and the hard mask layer.

Next, as shown in FIG. 1C, an impurity is implanted into the semiconductor substrate 101 to be automatically aligned with the gate electrode edge portion of the transfer transistor to form a photodiode impurity region 108.

At this time, the length of the channel through which electrons flow from the photodiode impurity region 108 to the floating diffusion region to be formed in a subsequent process is reduced due to the decrease in the line width of the gate electrode of the transfer transistor (collective effect). Cause.

In addition, when the photoresist pattern 106 is formed to have a line width considering loss of line width, defects such as a short with an adjacent pattern are generated.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a CMOS image sensor that can secure a line width of an effective gate electrode.

According to an aspect of the present invention for achieving the above object, the step of sequentially depositing a conductive layer and a hard mask layer for the gate of the transfer transistor on the substrate, selectively etching the hard mask layer, due to the etching Forming an etch compensation layer on the sidewall of the hard mask to compensate for the line width reduction, and etching the conductive film for the gate of the transfer transistor using the hard mask having the etch compensation layer as an etch barrier to form a gate electrode of the transfer transistor And forming a photodiode impurity region aligned with a gate electrode edge of the transfer transistor on the substrate by ion implantation using the hard mask as a barrier.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A to 2C are cross-sectional views illustrating a manufacturing process of the CMOS image sensor according to the present invention.

In the manufacturing process of the CMOS image sensor according to the present invention, first, as shown in FIG. 2A, a gate insulating film 202 and a gate conduction are formed on a semiconductor substrate 201 on which a device isolation film separating an active region and a device isolation region is formed. A film 203, a hard mask nitride film 204, and an antireflection film 205 are sequentially deposited.

At this time, the anti-reflection film 205 is preferably a SiON film.

The hard mask nitride film 204 and the anti-reflection film 105 are designated as hard mask layers.

Next, a photoresist pattern 206 is formed on the antireflection film 205.

Next, as shown in FIG. 2B, the hard mask layer is etched using the photoresist pattern 206 as an etch barrier.

At this time, due to the difference in the etching selectivity between the photoresist pattern 206 and the hard mask layer, the photoresist pattern 206 is damaged to form a hard mask layer having a line width smaller than a desired line width.

Subsequently, after the etching compensation layer 207 is deposited on the substrate including the hard mask layer having the lost line width, the etching compensation layer 207 is formed on the sidewall of the hard mask layer, except for the etching compensation layer 207. The etching compensation layer 207 formed on the substrate is removed.

Next, as shown in FIG. 2C, the gate conductive layer 203 and the gate insulating layer 202 are etched using the hard mask layer as an etch barrier to form a gate electrode of a transfer transistor.

In this case, the gate electrode of the transfer transistor having a desired line width may be secured by the hard mask layer including the etching compensation layer 207.

Subsequently, an impurity is implanted into the semiconductor substrate 201 to automatically align with the gate electrode edge portion of the transfer transistor to form a photodiode impurity region 209.

That is, in the present invention, in order to secure the effective line width of the gate electrode of the transfer transistor, the etch compensation layer 207 is formed with the line width lost by the etching selectivity to secure the effective line width.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the present invention forms an etching compensation layer to form a gate electrode of a transfer transistor having an effective line width.

Therefore, the channel of the gate electrode of the transfer transistor is shortened due to the loss of the line width, thereby solving the problem of lowering the threshold voltage.

In addition, stability and process ease can be obtained without etching equipment to secure an effective line width.

Claims (3)

Sequentially depositing a gate conductive film and a hard mask layer on the substrate; Selectively etching the hard mask layer; Forming an etch compensation layer on sidewalls of the hard mask layer to compensate for the reduction in line width due to the etching; Forming a gate electrode of the transfer transistor by etching the conductive film for the gate of the transfer transistor using the hard mask layer on which the etch compensation layer is formed as an etch barrier; And Forming a photodiode impurity region in the substrate aligned with an edge portion of a gate electrode of the transfer transistor by ion implantation into the hard mask layer barrier Method of manufacturing a CMOS image sensor comprising a. The method of claim 1, Selective etching of the hard mask layer, Depositing a hard mask nitride film over the gate conductive film of the transfer transistor; Depositing an anti-reflection film on the hard mask nitride film; Forming a photoresist pattern on the anti-reflection film; And And etching the anti-reflection film and the hard mask nitride film using the photoresist pattern as an etch barrier. The method of claim 1, The etching compensation layer is a method of manufacturing a CMOS image sensor, characterized in that the SiON film series.

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