KR20060111305A - The fabrication of wafer level chip scale package with solder bumps located on the back side of wafer through vertical interconnection - Google Patents

Abstract

A method for fabricating a wafer-level chip scale package with an external connection terminal formed on the back surface of a wafer through a penetration electrode is provided to minimize generation of thermal stress and variation of a direct circuit device by forming a penetration electrode before a direct circuit is formed and by forming a bump as an external connection terminal on the back surface of the wafer. After a penetration electrode(30) is formed in a bare wafer and a direct circuit(35) is formed on the upper surface of a wafer through a wafer fabricating process, the penetration electrode is connected to the direct circuit. After an external connection terminal connected to the penetration electrode is formed on the back surface of the wafer, a passivation layer is formed to protect the direct device. The wafer is sawed along a wafer sawing region to fabricate a wafer-level chip scale package. The external connection terminal is a solder bump(55) or a solder ball.

Description

The fabrication of wafer level chip scale package with solder bumps located on the back side of wafer through vertical interconnection}

1 (a) to 1 (b) are cross-sectional views showing a wafer level chip scale package according to the prior art.

2 is a cross-sectional view showing a conventional semiconductor inspection method.

3 is a cross-sectional view of a completed wafer level chip scale package according to the present invention.

4 (a) to 4 (d) are views sequentially showing a wafer level chip scale package manufacturing process according to the present invention.

5 is a cross-sectional view illustrating that solder bumps or solder balls, which are external connection terminals, are formed on the through electrode.

6 is a cross-sectional view showing that the solder bumps or solder balls, which are external connection terminals, are formed through a rearrangement process.

FIG. 7 is a diagram illustrating semiconductor inspection through an external connection terminal under the wafer.

8 (a) to 8 (b) are cross-sectional views of an image sensor package according to the present invention as an application example.

9 is a cross-sectional view of the chip stack package according to the present invention as an application example.

10 is a view showing a laser working condition for processing a multi-layer material layer.

Description of the main parts of the drawing

20 silicon wafer

25: via hole, 26: through hole, 30: through electrode

35: integrated circuit, 37: die pad, 38: rearrangement

41: inert layer 43: protective film, 54: metal wiring

55 solder bump, 56 UBM, 61 insulation layer

71: probe, 72, probe card

80: wafer level package (WL PKG), 85: substrate

Wafer Level Chip Scale Package (WL CSP; Wafer Level Chip Size Package) has the advantages of CSP, and it is a technology that completes the package structure after individualizing the package structure in wafer state. It is attracting much attention because it is cheaper to manufacture and more reliable than CSP.

The core technology of the conventional WL CSP can be broadly divided into a technology for redistributing circuits and a technology for forming external connection terminals. Representative WL CSP types are divided into six types as shown in Table 1.

Method Advantage Disadvantage Non-redistribution Simplest application Limited application; die must be designed for bump Redistribution Fab-like processes Higher bump count capability Adequate reliability May require underfill High bump count requires expensive PCB technology Redistribution w / encapsulation Encapsulation can be enhance reliability, extend die size Precise manufacturing and / or robust cleaning required at inner metal-bump interface Complian lead High reliability Compatible with high speed test and burn-in Existing solutions require licensing Lead carrier Interposer-like structure may enhance reliability Complex; tends to deviate from "WLP-ness" Difficult to maintain low cost Warp-around lead Appeal for niche applications Complex Limited to periphal I / O Can grow die

Source: www.patentmap.or.kr

In FIG. 1, (a) is a WL CSP structure without rearrangement, which is usually applied to a small device having 50 or less leads, and (b) is a WL CSP which is most used, and is mainly manufactured by wire bonding. It is applied to a device having a large number of leads by rearranging / O devices in an area array 38 to form solder bumps 55. The package method uses a copper / polyimide rearrangement (38) structure on the upper surface of the wafer 19 after finishing the semiconductor integrated circuit formation, and includes a solder bump 55 frited into 100 um copper bumps.

The conventional WL CSP includes a process for forming a plurality of metal wires for the rearrangement 38, a via hole 25, an insulating film 60, and a solder bump 55, as described above. . In the case of high-density memory semiconductors, line widths have entered the 50-100nm era, with direct circuit layers of dozens of layers and total thickness of only a few um. Many problems occur when the solder bumps 55, which are rearrangements and external connection terminals for the WL CSP, are formed on the precise integrated circuit 35.

Problems that occur in the existing WL CSP include thermal stress due to the difference in thermal expansion coefficient between the package and the substrate 85 due to temperature change, and stress and deformation caused by the solder ball reflow process cause stress and damage to the high-integrated circuit. This results in lowered reliability, and many metallization layers, insulating layers and polymer forming processes under high temperature, corrosive chemical environments can cause damage, physical and thermal deformation, directly or indirectly, on already formed integrated circuits. In terms of electrical reliability, electrical characteristics such as noise, cross-talk, and parasitic capacitors can be degraded between peripheral circuits including solder bumps and integrated circuits.

In the existing WL CSP, a polymer collar was formed around the solder ball to reduce solder ball deformation (K & S Ultra CSP), or a double bump structure, and a special stress relaxation layer made of polymer was used to relieve stress. (WLCSP from Motorola). In addition, Tessera Wide Area Vertical Expansion (WAVE) and FormFactor's MOST have adopted a unique structure to reduce stress. Since the attempt is made to the insulating film 60, the stress relaxation layer on the integrated circuit, there is a fundamental limit to preventing damage to the integrated circuit 35 from thermal stress and deformation.

The semiconductor chip has a fuse structure in order to replace it with a spare (or redundancy) chip through a laser repair process when each integrated circuit 35 failure occurs. The rearrangement 38 and solder bumps 55 process for the conventional WL CSP may oxidize and contaminate the fuse structure.

FIG. 2 illustrates a conventional method of inspecting semiconductors. Since the inspection is performed while the probe 71 is in contact with the die pad 37, contamination may occur due to particles generated when the die pad 37 is in contact with the damage. do. In addition, the rearrangement 38 and solder bumps 55 process for the WL CSP requires additional inspection to ensure reliability.

Existing WL CSP manufacturing process for rearrangement and forming bumps as external connection terminals after the formation of the integrated circuit has various problems. To solve this problem, through electrodes were formed before the formation of the integrated circuit and bumps as external connection terminals were formed. The formation process is formed on the lower surface of the wafer to minimize thermal stress and deformation of the integrated circuit device, and to enable semiconductor inspection through the external connection terminals. This shortens the process, reduces the cost, and provides a manufacturing method that can improve productivity.

The wafer level chip scale package manufacturing method according to the present invention for achieving the above object is (a) forming a mask using an alignment mask in the bare wafer step and then through holes or via holes matching the position of the die pad. (B) forming a through electrode by filling an electrically conductive metal in the hole, (c) forming a semiconductor integrated circuit according to a normal wafer manufacturing process on a wafer having the through electrode, (d) a wafer Forming an inert layer to protect the integrated circuit formed on the top surface and connecting the integrated circuit to the through electrode; (e) removing the bottom surface of the wafer by a predetermined thickness to expose the through electrode; and (f) the through electrode. Bump is formed directly at and used as external connection terminal, or redistribution through metal wiring layer from through electrode under wafer Forming, (g) Testing a semiconductor chip using an external connection terminal formed on the bottom of the wafer, (h) Encapsulation process with an insulator protective layer to protect the chip on the top surface of the wafer, (i) Chip After cutting into a package, characterized in that it comprises mounting on the substrate.

3 is a cross-sectional view of a completed wafer level chip scale package in accordance with the present invention.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. 4A is a cross-sectional view of the via hole 25 or the through hole 26 being processed in a bare wafer state. The via hole 25 or the through hole 26 is formed using a laser drill or deep reactive ion etching (RIE). In the case of a laser, holes smaller than the size of the die pad 37 are machined at the center of the die pad 37. In the case of deep RIE, the hole is etched using a mask having a circular pattern. Hole drilling depth is machined in the form of a through hole (25) through or drilled to a certain depth. In the case of a laser drill, holes of 25 to 40 μm or less may be formed in the silicon wafer 20 having a thickness of 1.5 mm due to technology development. The advantage of laser processing is that it does not need mask and photo process, it can produce high aspect ratio micro hole at high speed and does not place any limitation on the existing wafer manufacturing process. In addition to silicon, it can be applied to various materials such as metal layers, oxide films, nitride films and protective polymers. Deep RIE has the advantage of precision machining of high aspect ratio holes, but it adds mask and photo processing costs and requires a change in chip design for hole placement. If the via holes 25 are not the same, there is a disadvantage that it is difficult to maintain processing uniformity.

4B is a cross-sectional view illustrating a process of forming the through electrode 30. In the case of the via hole 25, the bottom surface 21 of the wafer may be removed by a predetermined thickness in a later process to form the through electrode 30. Prior to forming the through electrode 30, the barrier metal layer 28 and the seed metal layer 29 are formed, and then the through electrode 30 is formed by using a paste or electroplating. Figure showing that. As the through material, tungsten, molybdenum, molybdenum aluminum alloy or the like which can be used as a high temperature electrode is used. The material used for the barrier metal layer 28 may be formed of tungsten nitride (WNx), tantalum nitride (TaN), or titanium / titanium nitride (TiN) alloy material.

FIG. 4C is a cross-sectional view illustrating that a die pad is formed to connect the completed semiconductor integrated circuit 35 to the through electrode 30. The inactive layer 41 serves to protect the silicon 20 and the metal electrode, and mainly consists of an oxide film and a nitride film.

FIG. 4 (d) shows the through electrode 30 by removing the lower surface 21 of the wafer by a predetermined thickness after forming the protective film 43 using a photoresist which is easy to remove to protect the completed integrated circuit. The figure shows what is revealed. The method of removing the wafer lower surface 21 uses lapping 44. The photoresist is easily removed with the ability to buffer contamination and physical damage protection during wrapping, providing a convenient advantage in post processing.

5 is a cross-sectional view showing that the through electrode 30 and the solder bumps 55 or the solder balls 56 which are external connection terminals are directly formed. The insulating layer 61 is first formed on the lower surface of the wafer 21, and then the place where the solder bumps 55 are to be formed is opened. Then, the UBM 56 is formed and the solder bumps 55 are formed. The insulating layer 61 is preferably formed of polyimide or benzo cyclobutene (BCB), which is an organic material having good stress absorption.

FIG. 6 is a cross-sectional view of the through electrode 30 forming solder bumps 55 as external connection terminals through the rearrangement 38. First, the first insulating layer 61 and the second insulating layer 62 on the lower surface of the wafer 21 are preferably formed of polyimide or benzo cyclobutene (BCB), which is an organic material having good stress absorption. Meanwhile, before forming the metallization layer 54, the metal base layer 56 is formed under the region where the metallization layer 54 is to be formed. The metal base layer 56 serves as a seed layer, a diffusion barrier layer, and an adhesive layer to increase adhesion. The metal base layer 56 includes titanium / copper (Ti / Cu), titanium / titanium-copper / copper (Ti / Ti-Cu / Cu), chromium / copper (Cr / Cu), chrome / chromium-copper / copper ( Use one of Cr / Cr--Cu / Cu), titanium tungsten / copper (TiW / Cu), aluminum / nickel / copper (Al / Ni / Cu), aluminum / nickel vanadium / copper (Al / NiV / Cu) .

FIG. 7 shows a semiconductor inspection performed through the solder bumps 55, which are external connection terminals of the lower wafer 21. As shown in FIG. The probe card 72 serves as a core function of a semiconductor inspection device that inspects whether chips are defective or not in the state of the wafer 20, and the probe 71 performs electrical inspection while contacting the die pad 37. The probe 71 has various forms such as a needle, a micro pin, a MEMS type cantilever, and a micro spring. In the conventional method of inspecting the semiconductor, since the inspection is performed while the probe 71 contacts the die pad 37, a contamination problem occurs due to particles generated when the die pad 37 contacts with the damage. In addition, the rearrangement 38 and solder bumps 55 process for the WL CSP requires additional inspection to ensure reliability. However, since the inspection method according to the WL CSP manufacturing method of the present invention is not a method of contacting and inspecting the die pad 37, no additional inspection is required after the inspection-laser repair-inspection process. The process can be secured. In addition, inspection costs and time can be reduced, increasing semiconductor competitiveness.

8 is a cross-sectional view of an image sensor package according to an embodiment.

FIG. 8 (a) shows the packaging process of the image sensor in a wafer level state with a plurality of chips prior to the individual packaging process as an embodiment of the present invention. In the state of the wafer level 90 where the image sensor chip manufacturing process is completed, the transparent substrate 95 and the wafer 91 are bonded using the bonding material 97 to prevent contamination of the image sensor chip 92 from the external environment. . The junction between the transparent substrate 95 and the wafer 91 is made at the chip cutout 98. In the conventional method, the wafer level package process is not possible due to the limitation due to the formation of the external connection terminal 94 in the wafer level 90 state. According to the present invention, the inspection process is possible using the external output terminal 94 on the lower surface of the wafer 93 in the wafer level state, rather than individually packaged state. The existing method has a structure in which contamination may occur during the inspection process, and there is a problem of detecting contamination generated only when the final camera module 100 is reached. According to the present invention, it is possible to prevent contamination during the inspection process, thereby fundamentally preventing contamination of the image sensor in a later process, thereby providing a breakthrough method that can greatly shorten the process and increase productivity efficiency.

8 (b) shows a process of modularizing the image sensor 100 after individual package 101 after the package process is completed. The package method according to the present invention may be a chip scale package (CSP) closer to the chip size than the conventional case.

9 is a cross-sectional view of the chip stack package 81 in practical use.

 In the conventional chip stack package manufacturing process, after the integrated circuit 35 is completed, the electrode penetrates the wafer upper surface 19 and the lower surface 21 at the die pad 37 or at an arbitrary position connected with the die pad 37. 30 and the plurality of semiconductor chips are vertically mounted by bonding between the through electrodes 30. At this time, the processing of the through hole 26 uses a laser drill or a deep RIE, which requires continuous processing of a plurality of different material layers consisting of a multilayer insulating layer 60, a metal wiring layer, a protective polymer layer, and the like, which are already formed. do. In the above process, the laser beam and the material react to remove the material through ablation, which reduces productivity due to oxidation and deformation of the die pad 37 and contamination and damage of the integrated circuit 35. Holding it. For example, when the via holes 25 are processed in the state where three layers (oxide film, first and second insulating films) are formed on the upper surface 19 of the wafer, as shown in FIG. 10, four continuous lasers are shown as shown in FIG. 10. Pulse processing conditions are required. Optimized ablation conditions that control the number of laser pulses must be applied to each layer, resulting in reduced productivity and process uniformity.

A feature of the chip stack package 81 according to the practical example of the present invention is that the solder bumps 55, the through electrodes 30, and the die pads 37 are vertically bonded in a plurality of chips without rearrangement. Stack chip package 81 structure can be implemented. By eliminating the rearrangement process, the chip stack package 81 according to the present invention can produce a large number of chips having good production cost reduction effect and reliability, and thus can improve the yield of the chip stack package 81.

The present invention is a structure in which a semiconductor integrated circuit located on the wafer is connected to a bump, which is an external connection terminal located on the bottom of the wafer, through the through electrode, and the entire surface of the wafer can be utilized within the bonding pad area, thereby increasing the pad pitch. Thermal stress and deformation occurring during mounting can be minimized, which can greatly reduce the defective rate. In addition, there is an advantage that can remove the back end process, which is a semiconductor post-process. Since the semiconductor inspection is performed using the bumps under the wafer, the Known Good Die process can be established after the inspection-laser repair-inspection process without the need for an additional inspection process. In addition, probe card inspection cost can be greatly reduced and reliability can be greatly improved, and all probe cards (cold / room / high / burn-in) can be shared.

Claims (14)

The through electrode is formed in a bare wafer state, and an integrated circuit is formed on the upper surface of the wafer through a wafer fabrication process. The through electrode is connected to the integrated circuit, and an external connection terminal connected to the through electrode is formed on the lower surface of the wafer. And forming a wafer level chip scale package by cutting the wafer along the wafer cutting region after forming a protective layer. The wafer level chip scale package of claim 1, wherein the integrated circuit and the penetrating electrode are directly connected to the die pad without rearrangement when the upper circuit is connected to the upper surface of the wafer. The wafer level chip scale package of claim 1, wherein an integrated circuit on the upper surface of the wafer and an external connection terminal on the lower surface of the wafer are directly connected through the through electrode without rearrangement. The wafer level chip scale package of claim 1, wherein the through-electrode connects the integrated circuit on the upper surface of the wafer and the external connection terminals on the lower surface of the wafer through rearrangement. The wafer level chip scale package of claim 1, wherein each of the semiconductor chips has an external connection terminal formed on the lower surface after removing the wafer lower surface by a predetermined thickness. The wafer level chip scale package of claim 1, wherein the forming of the through electrode comprises forming a bare wafer, an epidex or an oxidation process. The wafer level chip scale package of claim 1, wherein the external connection terminals are solder bumps or solder balls. The method of claim 1, further comprising providing a method of inspecting at a wafer level through an external connection terminal formed at a lower portion of the wafer, rather than performing inspection on a die pad at the top of the wafer during semiconductor inspection. The method of claim 1, wherein a wafer level package process for forming a through electrode before the integrated circuit forming process is applicable to a multi chip, a stack chip, and an image sensor chip package.  (a) forming a mask using an alignment mask at a bare wafer level, and then forming a through hole or via hole matching the position of the die pad; (b) filling the hole with an electrically conductive metal to form a through electrode; (c) forming a semiconductor integrated circuit on the wafer with through electrodes according to a normal wafer fabrication process, (d) forming an inert layer to protect the integrated circuit formed on the top surface of the wafer and connecting the integrated circuit to the through electrode; (e) removing the lower surface of the wafer by a predetermined thickness to expose the through electrode; (f) forming a bump directly from the through electrode to use the external connection terminal, or redistributing through the metal wiring layer from the through electrode under the wafer to form a bump, (g) conducting a test on the semiconductor chip using an external connection terminal formed under the wafer; (h) encapsulation with an insulator polymer to protect the chip on the top surface of the wafer, (i) A method of manufacturing a wafer level chip scale package comprising cutting a chip package and mounting the chip on a substrate.        The method of claim 8, wherein step (a) is performed by a laser drill or Deep RIE. 9. The method of claim 8, wherein the hole of step (a) is a through hole or is processed into two types of via holes. The wafer level chip scale package of claim 8, wherein the step (b) comprises forming a barrier metal layer and a seed metal layer on the inner wall of the hole, and then forming a through electrode by electroplating. Manufacturing method. The method of forming a bump when directly connecting the through electrode and the external connection terminal in step 8, step (g) includes UBM, screen printing method, electroplating or solder ball after the first and second polymer (BCB, PI) passivation treatment. Wafer level chip scale package manufacturing method characterized in that for forming bumps. The method of forming a bump when the through electrode and the external connection terminal are connected through rearrangement in steps 8 and (g) includes forming a first insulating film having exposed through electrodes and forming a metal wiring on the first insulating film. A method of manufacturing a wafer level chip scale package, comprising: forming a second insulating film thereon, exposing a place where an external connection terminal is to be formed, and then forming UBM and solder bumps.

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