KR100886709B1 - Semiconductor package and method of manufacturing thereof - Google Patents

Abstract

A semiconductor package and a method of manufacturing the same are disclosed. The semiconductor package includes a semiconductor chip body having a bonding pad formed on a first surface, a first electrode formed in a first recess disposed on the first surface, and facing the first surface and electrically connected to the bonding pad. And a semiconductor chip formed in a second recess disposed on a second surface and having a second electrode connected to the first electrode. On both sides of the semiconductor chip, a first electrode including a high melting point metal and a second electrode connected to the first electrode and forming a low melting point metal are formed, respectively, thereby preventing damage to the first and second electrodes and the semiconductor chip. As a result, the time required for forming the first and second electrodes may be shortened, and the bonding force between the semiconductor chips may be greatly improved in a state in which at least two semiconductor chips are stacked.

Description

Semiconductor package and manufacturing method therefor {SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THEREOF}

1 is a plan view of a semiconductor package according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

3 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention.

4 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention.

5 is a cross-sectional view illustrating a semiconductor package according to still another embodiment of the present invention.

6 is a cross-sectional view illustrating a semiconductor package according to still another embodiment of the present invention.

7 to 12 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.

The present invention relates to a semiconductor package and a method of manufacturing the same.

In recent years, semiconductor packages including semiconductor devices for storing massive data and processing stored data in a short time have been developed. BACKGROUND Semiconductor packages containing semiconductor devices have been widely applied to personal computers, television receivers, home appliances, information and communication devices, and the like.

In general, a semiconductor package is a semiconductor chip manufacturing process for forming a semiconductor chip by integrating devices such as transistors, resistors, capacitors, and the like on a wafer, and a semiconductor chip having a weak electrical connection and brittleness with an external circuit board by individualizing the semiconductor chip from the wafer. It is manufactured by a package process that protects it from externally applied shocks and / or vibrations.

Recently, in order to improve data storage capacity and data processing speed, a multilayer semiconductor package in which a plurality of semiconductor chips are stacked is developed.

In order to form the stacked semiconductor package, the lower semiconductor chip and the upper semiconductor chip disposed on the lower semiconductor chip must be electrically connected.

In order to electrically connect the plurality of stacked semiconductor chips, each semiconductor chip has an electrode penetrating the semiconductor chip, and the plurality of semiconductor chips are electrically connected by using an electrode penetrating the semiconductor chip.

However, when forming the electrodes penetrating through the semiconductor chips, the through holes penetrating the semiconductor chips are deep, making it difficult to uniformly form the through holes, and the damage of the semiconductor chips frequently occurs during the formation of the through holes. Various defects also occur when metals are formed in the electrodes to form electrodes.

In addition, electrodes penetrating through the semiconductor chips are mainly formed by a plating method, and a very long plating time is required to form an electrode in a through hole having a deep depth in the through hole by a plating method.

In addition, since electrodes having high melting points such as copper are mainly used for the electrodes penetrating through the semiconductor chips, it is difficult to electrically connect the electrodes of each of the stacked semiconductor chips.

The present invention provides a semiconductor package in which defects generated during the formation of the electrode are reduced by changing the structure of the electrode penetrating the semiconductor chip.

The present invention provides a method of manufacturing the semiconductor package.

The semiconductor package according to the present invention includes a semiconductor chip body having a bonding pad formed on a first surface, a first electrode formed in a first recess disposed on the first surface, and electrically connected to the bonding pad. And a semiconductor chip formed in a second recess disposed on a second surface facing the surface and having a second electrode connected to the first electrode.

The first electrode of the semiconductor package includes a first electrode portion disposed in the first recess and a second electrode portion disposed on the first surface.

The second electrode of the semiconductor package has a truncated conical shape in the second recess.

The first electrode of the semiconductor package includes a metal seed pattern.

The first electrode of the semiconductor package includes a first metal and the second electrode includes a second metal.

The semiconductor package includes a substrate having a connection pad on which the semiconductor chip is mounted, and the second electrode of the semiconductor chip is connected to the connection pad.

The semiconductor package includes a substrate having a connection pad on which the semiconductor chip is mounted, and the first electrode of the semiconductor chip is connected to the connection pad.

The semiconductor package includes a substrate on which at least two semiconductor chips are mounted, a second electrode of a lower semiconductor chip contacting the substrate is connected to a connection pad of the substrate, and a first electrode of the lower semiconductor chip is connected to the lower It is electrically connected with the 2nd electrode of the upper semiconductor chip arrange | positioned above the semiconductor chip.

The semiconductor package includes a substrate on which at least two semiconductor chips are mounted, a first electrode of a lower semiconductor chip contacting the substrate is connected to a connection pad of the substrate, and a second electrode of the lower semiconductor chip is connected to the lower It is electrically connected with the 1st electrode of the upper semiconductor chip arrange | positioned above the semiconductor chip.

A method of manufacturing a semiconductor package according to the present invention includes forming a first electrode in a first recess formed on a first surface of a semiconductor chip, and forming the first electrode in a second recess formed on a second surface opposite to the first surface. Forming a second electrode electrically connected with the first electrode.

In the method of manufacturing a semiconductor package, the forming of the first electrode may include forming a metal seed layer covering the first surface and the first recess and openings exposing the first recess on the first surface. Forming a photoresist pattern having;

In the method of manufacturing a semiconductor package, the first electrode includes a copper layer formed by plating, and the second electrode includes solder.

Between the step of forming the first electrode and the second electrode of the method for manufacturing a semiconductor package, the step of grinding the second surface facing the first surface to reduce the thickness of the semiconductor chip.

The forming of the second electrode in the method of manufacturing a semiconductor package may include forming a second recess exposing the first electrode, filling a solder into the second recess, and melting the solder. Include.

In the forming of the second recess in the method of manufacturing a semiconductor package, an inner surface of the semiconductor chip formed by the second recess is formed to be inclined with respect to the second surface.

In the method of manufacturing a semiconductor package, the second electrode protrudes from the second surface.

A method of manufacturing a semiconductor package includes mounting the semiconductor chip on the substrate, wherein at least two semiconductor chips are stacked on the substrate and the first and second electrodes of the semiconductor chips are electrically connected to each other.

In the method of manufacturing a semiconductor package, the substrate has a connection pad, and the first electrode of the semiconductor chip in contact with the substrate among the stacked semiconductor chips is electrically connected to the connection pad.

In the method of manufacturing a semiconductor package, the substrate has a connection pad, and the second electrode of the semiconductor chip in contact with the substrate among the stacked semiconductor chips is electrically connected to the connection pad.

Hereinafter, a semiconductor package and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and the general knowledge in the art. Those skilled in the art can implement the present invention in various other forms without departing from the technical spirit of the present invention.

1 is a plan view of a semiconductor package according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

1 and 2, the semiconductor package 100 includes a semiconductor chip 40 having a semiconductor chip body 10, a first electrode 20, and a second electrode 30.

The semiconductor chip body 10 has a rectangular parallelepiped shape, for example. The semiconductor chip body 10 having a rectangular parallelepiped shape has a first face 1, a second face 2 and side faces 3 facing the first face 1.

The semiconductor chip body 10 includes a data storage unit (not shown), a data processing unit (not shown), and a bonding pad 6.

The data storage unit serves to store data, and the data processing unit serves to process data. The bonding pads 6 are formed on the first surface 1 of the semiconductor chip body 10. The bonding pads 6 are electrically connected to the data storage unit and / or the data processing unit.

The semiconductor chip body 10 has a first recess 4 and a second recess 5. The first recess 4 extends from the first face 1 into the interior of the semiconductor chip body 10, and the second recess 5 extends from the second face 2 of the semiconductor chip body 10. It extends into the chip body 10. The first and second recesses 4, 5 are, for example, holes and the first recesses 4 and the second recesses 5 communicate with each other.

In the present embodiment, the depth of the first recess 4 may be about 10% to about 80% of the thickness of the semiconductor chip body 10. The depth of the second recess 5 may be about 90% to about 20% of the thickness of the semiconductor chip body 10.

The first recess 4 has, for example, a cylindrical shape while the second recess 5 has, for example, a truncated cone shape. The shape of the first recesses 4 and the second recesses 5 may have various shapes in addition to the cylindrical shape and the truncated cone shape.

The first electrode 20 includes a first metal. Examples of the metal that can be used as the first electrode 20 include copper, which is a high melting point metal that can be plated.

The first electrode 20 is divided into a first electrode portion 22 and a second electrode portion 24 in structural aspect. The first electrode portion 22 is disposed inside the first recess 4, and the second electrode portion 24 is disposed on the first surface 1 of the semiconductor chip body 10.

The first electrode portion 22 has a shape corresponding to the shape of the first recess 4, for example. For example, when the first recess 4 has a cylindrical shape, the first electrode portion 22 has a cylindrical shape.

A portion of the second electrode portion 24 is electrically connected to the first electrode portion 22, and a portion of the second electrode portion 24 is disposed on the first surface 1 of the semiconductor chip body 10. It is electrically connected to the bonding pad 6. The second electrode portion 24 may have a line shape when viewed on a plane.

When the first metal used as the first electrode 20 is copper, a metal seed pattern 26 may be interposed between the first and second electrode portions 22 and 24 and the semiconductor chip body 10. . Examples of materials that can be used as the metal seed pattern 26 include titanium, nickel, vanadium, and the like.

The second electrode 20 is disposed inside the second recess 5, and the second electrode 20 includes a second metal. In this embodiment, examples of the material that can be used as the second electrode 20 include a low melting point metal such as solder or the like.

In this embodiment, since the second recess 5 has a truncated conical shape, the solder used as the second electrode 20 can be more easily provided into the second recess 5. Meanwhile, an end portion of the second electrode 20 may protrude a predetermined height from the second surface 2.

3 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention. The semiconductor package according to another embodiment of the present invention is substantially the same as the semiconductor package described above with reference to FIGS. 1 and 2 except for a substrate. Therefore, duplicate descriptions of the same parts will be omitted, and the same reference numerals and names will be given to the same parts.

Referring to FIG. 3, the semiconductor package 100 includes a semiconductor chip 40 and a substrate 50.

The semiconductor chip 40 is mounted on the substrate 50. The substrate 50 on which the semiconductor chip 40 is mounted includes a substrate body 51, a connection pad 52, a ball land 54, and a solder ball 56.

The substrate body 51 has an area and a shape suitable for mounting the semiconductor chip 40. For example, the substrate body 51 has a cuboid plate shape. In this embodiment, the substrate body 51 may be a printed circuit board.

The connection pads 52 are disposed on one side of the substrate body 51 facing the semiconductor chip 40. The connection pad 52 is disposed at a position corresponding to the first electrode 20 or the second electrode 30.

The ball land 54 is disposed on the other side facing one side of the substrate body 51. Each ball land 54 is electrically connected to the connection pad 52 using the substrate body 51.

The solder balls 56 are electrically connected to the respective ball lands 54.

In the present embodiment, for example, the second electrode 30 of the semiconductor chip 40 is electrically connected to the connection pad 52 of the substrate 50.

In the present embodiment, since the second electrode 30 has, for example, a truncated cone shape, connection failure due to misalignment of the second electrode 30 and the connection pads 52 can be suppressed. In addition, since the second electrode 30 includes solder, which is a low melting point metal, the second electrode 30 and the connection pad 52 may be electrically connected at a low temperature.

4 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention. The semiconductor package according to another embodiment of the present invention is substantially the same as the semiconductor package described with reference to FIG. Therefore, duplicate descriptions of the same parts will be omitted, and the same reference numerals and names will be given to the same parts.

Referring to FIG. 4, the semiconductor package 100 includes a semiconductor chip 40 and a substrate 50.

The semiconductor chip 40 is mounted on the substrate 50. The substrate 50 on which the semiconductor chip 40 is mounted includes a substrate body 51, a connection pad 52, a ball land 54, and a solder ball 56.

In the present embodiment, for example, the first electrode 20 of the semiconductor chip 40 is electrically connected to the connection pad 52 of the substrate 50. In this case, the connection pad 52 and the first electrode 20 may be electrically connected to each other by solder, which is a low melting point metal.

5 is a cross-sectional view illustrating a semiconductor package according to still another embodiment of the present invention. The semiconductor package according to another embodiment of the present invention is substantially the same as the semiconductor package described with reference to FIG. 3 except for the stacked semiconductor chips. Therefore, duplicate descriptions of the same parts will be omitted, and the same reference numerals and names will be given to the same parts.

Referring to FIG. 5, the semiconductor package 100 includes stacked semiconductor chips 45 and a substrate 50.

The stacked semiconductor chips 45 include a lower semiconductor chip 41 and an upper semiconductor chip 42.

The lower semiconductor chip 41 includes a lower semiconductor chip body 10a, a first electrode 20a, and a second electrode 30a.

The first electrode 20a extends from the first surface 1a of the lower semiconductor chip body 10a into the lower semiconductor chip body 10a. The second electrode 30a extends from the second surface 2a of the lower semiconductor chip body 10a into the lower semiconductor chip body 10a. The first electrode 20a and the second electrode 30a are electrically connected inside the lower semiconductor chip body 10a.

The first electrode 20a includes a first metal, and the second electrode 30a includes a second metal. The first metal may be copper, for example, and the second metal may be solder, for example.

The upper semiconductor chip 42 is disposed above the lower semiconductor chip 41.

The upper semiconductor chip body 10b, the first electrode 20b, and the second electrode 30b are included.

The first electrode 20b extends from the first surface 1b of the upper semiconductor chip body 10b into the upper semiconductor chip body 10b. The second electrode 30b extends into the upper semiconductor chip body 10b from the second surface 2b of the upper semiconductor chip body 10b. The first electrode 20b and the second electrode 30b are electrically connected inside the upper semiconductor chip body 10b.

The first electrode 20b includes a first metal, and the second electrode 30b includes a second metal. The first metal may be copper, for example, and the second metal may be solder, for example.

In the present embodiment, the second electrode 30a of the lower semiconductor chip 41 is electrically connected to the connection pad 52 of the substrate 50, and the second electrode 30b of the upper semiconductor chip 42 is lower It is electrically connected to the first electrode 20a of the semiconductor chip 41.

In the present embodiment, although the stacked semiconductor chip 45 composed of the two semiconductor chips 41 and 42 is illustrated and described on the substrate 50, the stacked semiconductor chips 45 are different from each other. It may include semiconductor chips.

6 is a cross-sectional view illustrating a semiconductor package according to still another embodiment of the present invention. The semiconductor package according to another embodiment of the present invention is substantially the same as the semiconductor package described with reference to FIG. 5 except for the stacked semiconductor chips. Therefore, duplicate descriptions of the same parts will be omitted, and the same reference numerals and names will be given to the same parts.

Referring to FIG. 6, the semiconductor package 100 includes stacked semiconductor chips 45 and a substrate 50.

The stacked semiconductor chips 45 include a lower semiconductor chip 41 and an upper semiconductor chip 42.

The lower semiconductor chip 41 includes a lower semiconductor chip body 10a, a first electrode 20a, and a second electrode 30a.

The upper semiconductor chip 42 is disposed above the lower semiconductor chip 41 and includes an upper semiconductor chip body 10b, a first electrode 20b, and a second electrode 30b.

In the present embodiment, the first electrode 20a of the lower semiconductor chip 41 is electrically connected to the connection pad 52 of the substrate 50, and the first electrode 20b of the upper semiconductor chip 42 is lower It is electrically connected to the second electrode 30a of the semiconductor chip 41.

In the present embodiment, although the stacked semiconductor chip 45 composed of the two semiconductor chips 41 and 42 is illustrated and described on the substrate 50, the stacked semiconductor chips 45 are different from each other. It may include semiconductor chips.

7 to 12 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 7, a first recess 4 is formed on the first surface 1 of the semiconductor chip body 10 having the bonding pads. In the present embodiment, the first recess 4 may be formed by a drilling process, a laser drilling process and a photolithography process. The first recesses 4 are formed at about 10% to about 80% of the thickness D of the semiconductor chip body 10.

Referring to FIG. 8, after the first recess 4 is formed on the first surface 1 of the semiconductor chip body 10, the metal seed layer 26a is formed on the first surface 1. In this embodiment, the metal seed layer 26a is formed by a chemical vapor deposition process or a sputtering process. Examples of materials that can be used as the metal seed layer 26a include titanium, nickel, vanadium, and the like.

Referring to FIG. 9, after the metal seed layer 26a is formed on the first surface 1, a photoresist pattern 29 having an opening 28 is formed on the metal seed layer 26a.

In order to form the photoresist pattern 29, a photoresist film (not shown) covering the metal seed layer 26a is formed on the first surface 1. The photoresist film may be formed by a spin coating process or the like. After the photoresist film is formed, the photoresist film is patterned by a photo process including an exposure process and a development process to form a photoresist pattern 29 on the metal seed layer 26a.

The opening 28 of the photoresist pattern 29 is formed in the same shape as the first electrode 20 shown in FIG. 1.

Referring to FIG. 10, after the photoresist pattern 29 having the opening 28 is formed, a plating process is performed using the metal seed layer 26a exposed by the opening 28. By the plating process, a first metal, for example, copper is plated on the metal seed layer 26a to form the first electrode 20. The first electrode 20 is formed integrally with the first electrode portion 22 and the first electrode portion 22 disposed inside the first recess 4, and the first surface of the semiconductor chip body 10. It has the 2nd electrode part 22 electrically connected with the bonding pad formed on (1).

After the first electrode 20 is formed, the photoresist pattern 29 is removed from the metal seed layer 26a by an ashing process and / or a strip process.

After the photoresist pattern 29 is removed, the metal seed layer 26a is patterned using the first electrode 20 as a pattern mask so that the metal seed pattern 26 is formed of the first electrode 20 and the semiconductor chip body ( 10) is formed between.

Referring to FIG. 11, after the metal seed pattern 26 is formed, a process of reducing the thickness of the semiconductor chip body 10 is performed. The thickness of the semiconductor chip body 10 may be a chemical mechanical polishing (CMP) process or an etching of the second surface 2 to polish the second surface 2 facing the first surface 1 of the semiconductor chip body 10. It can be reduced by the etching back etching process.

Referring to FIG. 12, after reducing the thickness of the semiconductor chip body 10, a second recess 5 is formed in the second surface 2 of the semiconductor chip body 10. The second recess 5 is formed at a position corresponding to the first electrode 20. The second recess 5 may be formed by, for example, a photolithography process. The inner surface of the semiconductor chip body 10 formed by the second recess 5 is formed to be inclined with respect to the second surface 2. For example, the inner surface of the semiconductor chip body 10 formed by the second recess 5 may have a truncated cone shape.

After the second recess 5 is formed, a second electrode 30 made of, for example, a second metal is formed in the second recess 5. In this embodiment, the second metal may be, for example, a solder. In order to form the second electrode 30, a solder paste (not shown) including solder is filled in the second recess 5, and the solder paste is melted by a reflow process or the like to form the second recess 5. ), A second electrode 30 electrically connected to the first electrode 20 is formed.

Meanwhile, an end portion of the second electrode 30 including the solder may protrude from the second surface 2 to a predetermined height.

Referring back to FIG. 3, after the semiconductor chip 40 having the first electrode 20 and the second electrode 30 is manufactured, the semiconductor chip 40 may be connected to the connection pad 52 and the ball land 54. It is mounted on the substrate 50 including.

For example, the second electrode 30 of the semiconductor chip 40 may be electrically connected to the connection pad 52 of the substrate 50. Alternatively, the second electrode 30 of the other semiconductor chip 40 is electrically connected to the first electrode 30 of the semiconductor chip 40 with the second electrode 30 electrically connected to the connection pad 52. To produce a stack package.

Meanwhile, referring back to FIG. 4, the first electrode 20 of the semiconductor chip 40 may be electrically connected to the connection pad 52 of the substrate 50. Alternatively, the first electrode 20 of the other semiconductor chip 40 is electrically connected to the second electrode 30 of the semiconductor chip 40 with the first electrode 20 electrically connected to the connection pad 52. To produce a stack package.

As described above in detail, first and second electrodes are formed on both surfaces of the semiconductor chip, respectively, to form a first electrode including a high melting point metal and a second electrode including a low melting point metal, respectively. And a reduction in the time required to form the first and second electrodes, and to greatly improve the bonding force between the semiconductor chips in a state in which at least two semiconductor chips are stacked.

In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

Claims (19)

A semiconductor chip body having a bonding pad formed on the first surface; A first electrode formed in a first recess disposed on the first surface and electrically connected to the bonding pad; And And a semiconductor chip formed in a second recess disposed on a second surface opposite to the first surface, the semiconductor chip having a second electrode connected to the first electrode and protruding from the second surface. The method of claim 1, And the first electrode includes a first electrode portion disposed in the first recess and a second electrode portion disposed on the first surface. The method of claim 1, And the second electrode has a truncated conical shape in the second recess. The method of claim 1, The first electrode is a semiconductor package, characterized in that it comprises a metal seed pattern. The method of claim 1, And the first electrode comprises a first metal and the second electrode comprises a second metal. The method of claim 1, And a substrate having a connection pad on which the semiconductor chip is mounted, wherein the second electrode of the semiconductor chip is connected to the connection pad. The method of claim 1, And a substrate having a connection pad on which the semiconductor chip is mounted, wherein the first electrode of the semiconductor chip is connected to the connection pad. The method of claim 1, And a substrate on which at least two semiconductor chips are mounted, wherein a second electrode of a lower semiconductor chip contacting the substrate is connected to a connection pad of the substrate, and a first electrode of the lower semiconductor chip is connected to the lower semiconductor chip. A semiconductor package, wherein the semiconductor package is electrically connected to a second electrode of an upper semiconductor chip disposed above. The method of claim 1, And a substrate on which at least two semiconductor chips are mounted, wherein a first electrode of a lower semiconductor chip in contact with the substrate is connected to a connection pad of the substrate, and a second electrode of the lower semiconductor chip is formed of the lower semiconductor chip. And a semiconductor package electrically connected to the first electrode of the upper semiconductor chip disposed above. Forming a first electrode in a first recess formed in the first surface of the semiconductor chip; And Forming a second electrode electrically connected to the first electrode in a second recess formed in a second surface opposite to the first surface, And the second electrode protrudes from the second surface. The method of claim 10, wherein forming the first electrode Forming a metal seed layer covering the first surface and the first recess; And Forming a photoresist pattern having an opening exposing the first recess on the first surface. The method of claim 10, And the first electrode comprises a copper layer formed by plating and the second electrode comprises solder. The method of claim 10, wherein the step of forming the first electrode and the second electrode, And reducing a thickness of the semiconductor chip by grinding the second surface opposite to the first surface. The method of claim 10, wherein forming the second electrode Forming a second recess exposing the first electrode; Filling solder into the second recess; And And melting the solder. The method of claim 14, wherein in the forming of the second recess, The inner surface of the semiconductor chip formed by the second recess is formed inclined with respect to the second surface. delete The method of claim 10, And mounting the semiconductor chip on the substrate, wherein at least two of the semiconductor chips are stacked on the substrate, and the first and second electrodes of the semiconductor chips are electrically connected. Way. The method of claim 17, And the substrate has a connection pad, wherein the first electrode of the semiconductor chip which is in contact with the substrate among the stacked semiconductor chips is electrically connected to the connection pad. The method of claim 17, And the substrate has a connection pad, and wherein the second electrode of the semiconductor chip in contact with the substrate among the stacked semiconductor chips is electrically connected to the connection pad.

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