KR101069283B1 - Semiconductor package - Google Patents

Abstract

The semiconductor package according to the present invention has a lower surface and an upper surface facing the lower surface, a groove formed at an edge of the lower surface and a through hole penetrating through a portion corresponding to the groove, and the first bonding pads are provided on the upper surface. A first package unit including a first semiconductor chip, a through electrode disposed in the through hole, and a first wiring disposed on the upper surface and connected to the through electrode and the bonding pad; A second semiconductor chip facing the bottom surface of the first semiconductor chip of the first package unit and disposed on one surface of the second semiconductor chip which is connected to the second bonding pad and the second bonding pad and faces the through electrode; A second package unit including a second wiring line; And a connection member disposed in the groove and electrically connecting the through electrode and the second wiring.

Description

Semiconductor Package {Semiconductor package}

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package that can reduce the overall height and improve the electrical characteristics.

The packaging technology for semiconductor integrated devices has been continuously developed in accordance with the demand for miniaturization and high capacity, and recently, various technologies have been developed in the form of a stack package that can satisfy the miniaturization, high capacity, and mounting efficiency. .

The term "stack" in the semiconductor industry refers to a technology of vertically stacking at least two semiconductor chips or packages, and in the case of a memory device, a product having a memory capacity larger than the memory capacity that can be realized in a semiconductor integration process may be implemented and mounted. The efficiency of the use of the area can be improved.

Stacked packages can be classified into stacking individual semiconductor chips according to a manufacturing technology, and then stacking stacked semiconductor chips at a time, and stacking and stacking packaged individual semiconductor chips. Are electrically connected through metal wires, bumps or through-silicon vias formed between the semiconductor chips or packages.

In the conventional stack package, after attaching a plurality of first semiconductor chips on a substrate, a first wire bonding process is performed, and a space is secured by using a spacer tape or a space die on the first semiconductor chips. On the first semiconductor chips, the second semiconductor chips are attached, a second wire bonding process, an encapsulation portion forming process, and an external connection terminal forming process are formed.

However, since a conventional stack package is mostly electrically connected by metal wires, a margin of the upper space of the semiconductor chip considering the top height of the metal wire is required to form an encapsulation portion, and a substrate is used to stack the semiconductor chips. Because of this, there is a limit to reducing the overall height of the semiconductor package.

In addition, as the plurality of stacked semiconductor chips are electrically connected to a substrate or a semiconductor chip through metal wires, the size of the semiconductor package is increased due to the bonding space of the metal wires due to the use of a large number of metal wires.

In addition, according to the formation of a plurality of metal wires, electrical shorts, etc. are generated between the metal wires, a wire sweeping phenomenon occurs due to the flow of the molding agent during the molding process for forming the encapsulation portion, and different wires The difference in the signal transmission speed depending on the length is likely to cause a poor electrical signal transmission.

The present invention provides a semiconductor package that can reduce the overall height and improve the electrical characteristics.

The semiconductor package according to the present invention has a lower surface and an upper surface facing the lower surface, a groove formed at an edge of the lower surface and a through hole penetrating through a portion corresponding to the groove, and a plurality of bonding pads are provided on the upper surface. Semiconductor chips; A through electrode disposed in the through hole; And a wire disposed on the upper surface and connected to the through electrode and the bonding pad.

The groove has a shape recessed or grooved in an upper direction of the lower surface.

It further includes an external connection terminal attached to the wiring.

The external connection terminal includes any one of a bump, a solder ball, and a metal pin.

In addition, the semiconductor package according to the present invention may have a lower surface and an upper surface facing the lower surface, a groove formed at an edge of the lower surface, and a through hole penetrating through a portion corresponding to the groove, and first bonding pads may be disposed on the upper surface. A first package unit including a first semiconductor chip provided, a through electrode disposed in the through hole, and a first wiring disposed on the upper surface and connected to the through electrode and the bonding pad; A second semiconductor chip facing the bottom surface of the first semiconductor chip of the first package unit and disposed on one surface of the second semiconductor chip which is connected to the second bonding pad and the second bonding pad and faces the through electrode; A second package unit including a second wiring line; And a connection member disposed in the groove and electrically connecting the through electrode and the second wiring.

The groove of the first package unit has a recessed or grooved shape in an upper direction of the lower surface.

It further comprises a conductive adhesive member disposed on the portion of the first semiconductor chip exposed by the groove.

The connection member includes any one of a bump, a solder ball, and a metal pin.

The apparatus may further include a first external connection terminal provided on the first wiring of the first package unit.

The first external connection terminal includes any one of a bump, a solder ball, and a metal pin.

The semiconductor device may further include an adhesive member interposed between the first semiconductor chip and the second semiconductor chip.

The first package unit is stacked in plurality, and adjacent first package units are electrically connected by the connecting member.

The substrate may further include a substrate on which the first and second package units are disposed.

The semiconductor device further includes an encapsulation unit covering the first and second package units on the substrate.

And a second external connection terminal attached to an upper surface of the substrate.

The present invention can reduce the height of the entire semiconductor package having a stacked form by forming a groove so that the electrical connection member of the upper package unit is arranged and electrically connected to the edge of the lower package unit, and the length of the electrical connection is short. The electrical properties of the sieve package can be improved.

Hereinafter, a semiconductor package according to embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and those skilled in the art will appreciate The semiconductor package according to the present invention may be implemented in various other forms without departing from the spirit of the invention.

The semiconductor package according to the present invention has a lower surface and an upper surface facing the lower surface, a groove formed at an edge of the lower surface and a through hole penetrating through a portion corresponding to the groove, and the first bonding pads are provided on the upper surface. A first package unit including a first semiconductor chip, a through electrode disposed in the through hole, and a first wiring disposed on the upper surface and connected to the through electrode and a bonding pad, and the first semiconductor chip of the first package unit A second package unit including a second semiconductor chip facing the bottom surface and having second bonding pads, and a second wiring connected to the second bonding pad and disposed on one surface of the second semiconductor chip facing the through electrode; And a connection member disposed in the groove and electrically connecting the through electrode and the second wiring.

Hereinafter, a semiconductor package and a method of manufacturing the same according to various embodiments of the present disclosure will be described.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

As shown, the semiconductor package 100 includes a connection member 160 for electrically connecting the first package unit 110 and the second package unit 120 and the first and second package units 110 and 120. ).

The lower package unit 110 includes a first semiconductor chip 130, a through electrode 134, and a first wiring 136.

The first semiconductor chip 130 has, for example, a rectangular parallelepiped shape, has a lower surface 131 and an upper surface 133 facing the lower surface 131, and includes a first bonding pad 132 provided on the upper surface 133. ) The first semiconductor chip 130 includes a groove H formed in an upper direction of the lower surface 131 at an edge of the lower surface of the first semiconductor chip 130 and passes through the portion of the first semiconductor chip 130 corresponding to the groove H. )

The groove H has a recessed shape such that a plurality of portions are spaced apart from each other in an upper direction of the lower surface 131 of the first semiconductor chip 130 or the lower surface 131 of the first semiconductor chip 130. Groove along the periphery of the shape (Groove), that is, has a picture frame shape.

The through electrodes 134 are filled with a metal material in the through-holes V of the first semiconductor chip 130, so that one end thereof is exposed to the groove H portion of the first semiconductor chip 130, and the other end thereof has the first end. It is formed to be exposed to the upper surface 133 of the semiconductor chip 130.

A plurality of first wirings 136 are disposed on the top surface 133 of the first semiconductor chip 130, and the corresponding first bonding pads 132 and the through electrodes 134 of the first semiconductor chip 130 are disposed. It is electrically connected to the other end.

An external connection terminal 140 for electrical connection is disposed on a lower surface of each first wiring 136, and the external connection terminal 140 includes one of bumps, solder balls, and metal pins, for example.

An upper portion of the first package unit 110, that is, the second package unit 120 disposed on the bottom surface 131 of the first semiconductor chip 130 may include the second semiconductor chip 150 and the second wiring 154. It includes.

The second semiconductor chip 150 may have, for example, a rectangular parallelepiped shape and include second bonding pads 132, and the second semiconductor chip 150 may have a lower surface 131 of the first semiconductor chip 130. It is arranged to face each other.

The second wiring 154 is electrically connected to the corresponding second bonding pad 132 of the second semiconductor chip 150 and faces the second electrode chip 134 of the first package unit 110. It is formed on one surface of 150.

The connection member 160 is in the groove H of the first package unit 110, that is, the through electrode 134 and the second wiring 154 so that the first and second package units 110 and 120 are electrically connected to each other. ). The connection member 160 includes, for example, any one of bumps, solder balls, and metal pins.

Between portions of the first and second package units 110 and 120 on the portion 138 of the first semiconductor chip 130 including the through electrode 134 exposed by the groove H of the first package unit 110. Conductive adhesive members 170, such as conductive pastes, are interposed to enhance electrical and physical connections.

First and second package units between the upper surface of the first package unit 110 and the second package unit 120, that is, between the lower surface 131 and the second semiconductor chip 150 of the first semiconductor chip 120. An adhesive member 172 is interposed to reinforce the physical bonding of the 110 and 120.

2 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention.

FIG. 2 includes substantially the same components as the semiconductor package shown and described above in FIG. 1. Therefore, duplicate descriptions of the same components will be omitted, and the same components and the same reference numerals will be given to the same components.

Referring to FIG. 2, in an embodiment of the present invention, a semiconductor package 100 may include a plurality of first package units 110, second package units 120, and first package units 110. Connection members 160 for electrically connecting the first and second package units 110 and 120, respectively.

Among the first package units 110, the first package unit 110 disposed at an upper portion of the first package unit 110 extends to a portion corresponding to the groove H of the first package unit 110 disposed below. do.

3A and 3B are cross-sectional views illustrating semiconductor packages in accordance with still other embodiments of the inventive concept.

The semiconductor package shown in FIGS. 3A and 3B includes substantially the same components as the semiconductor package shown and described above in FIG. 1. Therefore, duplicate descriptions of the same components will be omitted, and the same components and the same reference numerals will be given to the same components.

Referring to FIG. 3A, the first and second package units 110 and 120 are attached to the substrate 180 via an external connection terminal 140.

An encapsulation part 190 is provided on the lower surface of the substrate 180 to cover the first and second package units 110 and 120, and a second external connection for electrical connection to the outside is provided on the upper surface of the substrate 180. Terminal 192 is attached. The second external connection terminal 192 includes one of bumps, solder balls, and metal pins, for example.

Referring to FIG. 3B, the first and second package units 110 and 120 are encapsulated to be electrically connected to the outside via the external connection terminal 140, that is, the external connection terminal 140 is exposed. 190.

Meanwhile, the stack package according to the embodiment of the present invention is formed by the method as shown in FIGS. 4A to 4G.

Referring to FIG. 4A, a plurality of first semiconductor chips 130 having a top surface, a process of manufacturing a semiconductor device, a bottom surface and top surfaces 131 and 133, and a plurality of first bonding pads 132 are provided on the top surface. A plurality of via holes V is formed in each of the first semiconductor chips 130 of the first wafer 130a. The via hole V is formed along the circumference of the first semiconductor chip 130, for example, at an edge portion of the first semiconductor chip 130.

Thereafter, a conductive film is formed on the top surface 133 of each first semiconductor chip 130 to fill the via holes V, thereby forming a plurality of through electrodes 134 in the first semiconductor chip 130. Subsequently, the conductive film on the upper surface of each of the first semiconductor chips 130 is patterned, and the corresponding through electrodes 134 and the first bonding pads of the first semiconductor chips 130 are formed on the upper surfaces of the first semiconductor chips 130. The first wiring 136 is formed to be electrically connected to the 132.

Referring to FIG. 4B, an external surface including any one of bumps, solder balls, and metal pins may be formed on a portion of the first wiring 136 used as a ballland among the first wirings 136 of the upper surface 133 of each of the first semiconductor chips 130. The connection terminal 140 is formed.

Then, a back grinding and dicing process is performed on the upper surface 131 of the first wafer 130a, that is, the upper surface 131 of each of the first semiconductor chips 130 to cover the first connection terminal 140. After attaching the tape 142 to be used, the back grinding process is performed to the bottom surface of the first wafer 130a to reduce the thickness of each first semiconductor chip 130.

Referring to FIG. 4C, after the sawing process is performed on the first wafer on which the backgrinding process is performed, the tape is removed to form the first package unit 110 of the stack package according to the present invention.

The sawing process is performed by a step cut method using blades having different widths, and accordingly, grooves H having a height lower than an inner portion of a lower surface of the lower package unit 110 are formed.

4D, each second semiconductor chip of the second wafer 150a including the plurality of second semiconductor chips 150 having the second bonding pads 152 formed on the surface thereof is completed. A conductive film is formed on one surface of 150.

Next, the second wiring 154 electrically connected to the second bonding pads on one surface of each of the second semiconductor chips 150 corresponding to the through electrode by patterning the conductive film on one surface of the second semiconductor chip 150. To form.

Referring to FIG. 4E, a portion of the second wiring 154 of the second wiring 154 on the bottom surface of each of the second semiconductor chips 150, that is, the through electrode formed at the edge of the first semiconductor chip is shown. A connection member 160 including any one of a bump, a solder ball, and a metal pin is formed in a portion of the second wiring 154 corresponding to the groove.

Then, the back grinding and dicing tape 162 is attached to the other surface of the second wafer 150a, that is, the other surface of each of the second semiconductor chips 150 to cover the connection member 160. In addition, a back grinding process is performed on the other surface of the second wafer 150a to reduce the thickness of each second semiconductor chip 150.

Referring to FIG. 4F, after the sawing process is performed on the second wafer on which the backgrinding process is performed, the tape is removed to form the second package unit 120 according to the present invention.

Referring to FIG. 4G, an electrical connection member 170, preferably on a portion of the first semiconductor chip 130 including a portion of the through electrode 134 exposed by the groove H of the first package unit 110, is preferable. , Conductive paste is applied.

Subsequently, the second package unit 120 is disposed on the first package unit 110 such that the connection member 160 of the second package unit 120 is disposed in the groove H of the first package unit 110. . Thereafter, a reflow process is performed to electrically connect the connecting member 160 of the second package unit 120 and the through electrode 134 of the first package unit 110 to complete the manufacture of the stack package according to the present invention. do.

As described above, the present invention can reduce the height of the entire semiconductor package having a stacked form by forming a groove so that the electrical connection member of the upper package unit is disposed and electrically connected to the edge portion of the lower package unit.

In addition, the electrical connection length is short, it is possible to improve the electrical characteristics of the semiconductor package.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention.

2 is a sectional view showing a semiconductor package according to another embodiment of the present invention.

3A and 3B are cross-sectional views illustrating semiconductor packages in accordance with still other embodiments of the inventive concept.

4A to 4G are cross-sectional views of processes for describing a method of manufacturing a semiconductor package according to an embodiment of the present invention.

Claims (15)

A lower surface and an upper surface opposite to the lower surface, a groove is formed at an edge of the lower surface such that the edge portion has a lower height than an inner portion, and has a through hole penetrating through a portion corresponding to the groove; A semiconductor chip having bonding pads; A through electrode disposed in the through hole; And A semiconductor package disposed on the upper surface and including a wire connected to the through electrode and a bonding pad. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The groove may have a recessed shape such that a plurality of portions are spaced apart from each other in an upper direction of a lower surface of the semiconductor chip, or a photoframe shape grooved along a circumference of the lower surface of the semiconductor chip. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, The semiconductor package further comprises an external connection terminal attached to the wiring. Claim 4 was abandoned when the registration fee was paid. The method of claim 3, wherein The external connection terminal is a semiconductor package comprising any one of a bump, a solder ball and a metal pin. A lower surface and an upper surface facing the lower surface, a groove is formed at an edge of the lower surface such that the edge portion has a lower height than an inner portion, and has a through hole penetrating through a portion corresponding to the groove; A first package unit including a first semiconductor chip having bonding pads, a through electrode disposed in the through hole, and a first wiring disposed on the upper surface and connected to the through electrode and the bonding pad; A second semiconductor chip facing the bottom surface of the first semiconductor chip of the first package unit and disposed on one surface of the second semiconductor chip which is connected to the second bonding pad and the second bonding pad and faces the through electrode; A second package unit including a second wiring line; And And a connection member disposed in a groove of an edge portion having a lower height than the inner portion, and electrically connecting the through electrode and the second wiring. Claim 6 was abandoned when the registration fee was paid. The method of claim 5, The groove of the first package unit may have a recessed shape such that a plurality of portions are spaced apart from each other in an upper direction of the lower surface of the semiconductor chip, or have a photo frame shape that is grooved along a circumference of the lower surface of the semiconductor chip. A semiconductor package characterized by the above-mentioned. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 5, And a conductive adhesive member disposed on the first semiconductor chip portion exposed by the groove. Claim 8 was abandoned when the registration fee was paid. The connecting member includes a bump, a solder ball and a metal pin any one of a semiconductor package. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 5, And a first external connection terminal provided on the first wiring of the first package unit. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 9, The first external connection terminal is a semiconductor package, characterized in that it comprises any one of a bump, a solder ball and a metal pin. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 5, And a bonding member interposed between the first semiconductor chip and the second semiconductor chip. Claim 12 was abandoned upon payment of a registration fee. The method of claim 5, And a plurality of the first package units are stacked, and adjacent first package units are electrically connected to each other by the connection member. Claim 13 was abandoned upon payment of a registration fee. The semiconductor package of claim 1, further comprising a substrate on which the first and second package units are disposed. Claim 14 was abandoned when the registration fee was paid. The method of claim 13, And a sealing part covering the first and second package units on the substrate. Claim 15 was abandoned upon payment of a registration fee. The method of claim 13, And a second external connection terminal attached to an upper surface of the substrate.

Images