KR20060111214A - Thin film transistor panel and method for manufacturing the same - Google Patents

Abstract

A TFT substrate is provided to simplify a fabricating process of a TFT substrate by using only three masks. A semiconductor layer is formed on an insulation substrate, including a source/drain region. A plurality of gate lines(52) are elongated in one direction on the semiconductor layer. A plurality of data line sections are formed on the semiconductor substrate, separated from the plurality of gate lines by a predetermined interval and extended in a direction vertical to the plurality of gate lines. The plurality of data line sections are electrically interconnected by a first bridge(91) extended along each data line section.

Description

Thin film transistor panel and method for manufacturing same

1 is a conceptual diagram of a liquid crystal display device having a thin film transistor substrate according to an exemplary embodiment of the present invention.

2A is a layout view of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along line BB ′ of FIG. 2A.

3 is a cross-sectional view illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

4A is a layout diagram illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment. FIG. 4B is a cross-sectional view taken along line BB ′ of FIG. 4A.

5A is a layout diagram illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment. FIG. 5B is a cross-sectional view taken along line BB ′ of FIG. 5A.

6A is a layout view of a thin film transistor substrate according to another exemplary embodiment. FIG. 6B is a cross-sectional view taken along line BB ′ of FIG. 6A.

(Explanation of symbols for the main parts of the drawing)

1: liquid crystal panel 2: gate driver

3: data driver 4: thin film transistor substrate

10: insulating substrate 11: buffer layer

20: semiconductor layer 21: insulating layer

22: source region 23: drain region

52: gate line 54: gate pad

56 gate electrode 62 data line

64: source electrode 66: drain electrode

68: data pad 80: protective layer

90 pixel electrode 91 first bridge

92: second bridge 93: third bridge

94: auxiliary gate pad 98: auxiliary data pad

The present invention relates to a thin film transistor substrate and a method of manufacturing the same.

A thin film transistor (TFT) substrate is used as a circuit board for driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like. The thin film transistor substrate includes a gate wiring for transmitting a gate signal, a data wiring for transmitting a data signal, a thin film transistor defined in a region where the gate and the data wiring intersect, a pixel electrode connected to the thin film transistor, and the like.

In particular, the thin film transistor includes a semiconductor layer in which a channel is formed by a gate electrode connected to a gate wiring, a source electrode and a drain electrode connected to a data wiring. The thin film transistor is a switch device that transmits or blocks a data signal transmitted through the data line in response to a gate signal transmitted through the gate line.

Such a thin film transistor substrate is generally manufactured through an etching process using four to six masks. Here, a smaller number of masks simplifies the process, thereby increasing productivity and reducing costs.

An object of the present invention is to provide a thin film transistor substrate with a simplified manufacturing process.

Another object of the present invention is to provide a method of manufacturing a thin film transistor substrate with a simplified manufacturing process.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A thin film transistor substrate according to an embodiment of the present invention for achieving the above technical problem is formed on an insulating substrate, an insulating substrate, a semiconductor layer including a source / drain region, a plurality of formed extending in one direction on the semiconductor layer A gate line, a plurality of data line fragments formed on the semiconductor layer spaced apart from the plurality of gate lines by a predetermined distance, and extending in a direction perpendicular to the plurality of gate lines, and a first bridge electrically connecting the plurality of data line fragments to each other; .

According to one or more exemplary embodiments, a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention may include sequentially forming a semiconductor layer, an insulating layer, and a conductive layer on an insulating substrate, and extending in one direction on the insulating substrate. A plurality of gate lines, a plurality of data lines intersecting a predetermined distance from the plurality of gate lines, extending in a direction perpendicular to the plurality of gate lines, and source / drain regions formed on both sidewalls of gate electrodes connected to the plurality of gate lines, respectively. Forming a first bridge to electrically interconnect the plurality of data line segments.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

1 is a conceptual diagram of a liquid crystal display device having a thin film transistor substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display including a thin film transistor substrate according to an exemplary embodiment includes a liquid crystal panel 1, a gate driver 2, and a data driver 3. Here, although the liquid crystal display is exemplified as the display device using the thin film transistor substrate according to the exemplary embodiment, the present invention is not limited thereto.

The liquid crystal panel 1 includes a plurality of gate lines G ₁ to G _n , data lines D ₁ to D _m , and pixel regions in a matrix form defined in regions where they cross. The gate lines G ₁ to G _n extend in the row direction to transfer the gate signals, and the data lines D ₁ to D _m extend in the column direction to transfer the data signals. The pixel region includes a switching element M, a liquid crystal capacitor C _lc , and first and second sustain capacitors C _st1 and C connected to the gate lines G ₁ to G _n and the data lines D ₁ to D _m . _st2 ).

The switching element M is a three-terminal element, the control terminal is connected to the gate lines (G ₁ to G _n ), the input terminal is connected to the data lines (D ₁ to D _m ), the output terminal is a liquid crystal capacitor (C _lc ) and one terminal of the first and second sustain capacitors C _st1 and C _st2 . In addition, the switching element M is implemented as a thin film transistor including amorphous silicon and polysilicon as a channel layer.

The liquid crystal capacitor C _lc is connected to the output terminal of the switching element M and a common voltage Vcom or a reference voltage Vref.

The first and second sustain capacitors C _st1 and C _st2 are connected between the output terminal of the switching element M and the common voltage (independent wiring) or the gate line directly above the output terminal of the switching element M ( G ₁ to G _n ) may be connected (shear gate method). In FIG. 1, the first sustain capacitor C _st1 is connected by an independent wiring method, and the second sustain capacitor C _st2 is connected by a front gate method.

The gate driver 2 sequentially provides a gate signal for activating the switching element M to the plurality of gate lines G ₁ to G _n . The data driver 3 provides the grayscale voltage corresponding to the data signal to the plurality of data lines D ₁ to D _m in accordance with the timing at which the gate signal is applied.

2A is a layout diagram of a thin film transistor substrate according to an exemplary embodiment of the present invention. FIG. 2B is a cross-sectional view taken along the line BB ′ of FIG. 2A.

2A and 2B, a thin film transistor substrate according to an exemplary embodiment of the present invention may include a buffer layer 11, a semiconductor layer 20, an insulating layer 21, gate wirings 52, 54, 56, and data wirings. 62, 64, 66, 68, protective layer 80, pixel electrode 90, first to third bridges 91, 92, 93, auxiliary gate pad 94, auxiliary data pad 98, and the like. It includes.

The buffer layer 11 may be formed on the transparent insulating substrate 10, and may be formed of silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), or the like.

The semiconductor layer 20 may be formed of amorphous silicon, polysilicon, or the like on the buffer layer 11. In addition, the semiconductor layer 20 includes source / drain regions 22 and 23 formed in alignment with both sidewalls of the gate electrode 56.

The insulating layer 21 is mainly formed of a material such as silicon nitride (SiN _x ) on the semiconductor layer 20.

Gate wirings 52, 54, and 56 are formed on the insulating layer 21 and include a gate pad 54, a gate line 52, and a gate electrode 56. The gate pad 54 is connected to the end of the gate line 52 to receive a gate signal from the outside. The gate line 52 is elongated in the row direction to transmit an applied gate signal to the gate electrode 56, and the gate electrode 56 turns on the thin film transistor in response to the gate signal. .

In addition, the gate lines 52, 54, and 56 may be formed in a single layer or a double layer or more. When formed as a single layer, it may be formed of aluminum (Al), aluminum alloy (Al alloy), molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) and the like. When forming more than two layers as shown in FIG. 2B, the lower layers 54a and 56a are preferably made of a material having low resistance, and the upper layers 54b and 56b are made of a material having good contact properties with other materials. . For example, the pair of lower layers 54a and 56a and upper layers 54b and 56b may be chromium (Cr) / aluminum (Al) (or aluminum alloy), aluminum (Al) / molybdenum (Mo), chromium (Cr). ) Or molybdenum-tungsten alloy (MoW) / aluminum (Al).

The data lines 62, 64, 66, and 68 are formed on the insulating layer 21, and include a data pad 68, a data line segment 62, a source electrode 64, and a drain electrode 66. The data pad 68 is connected to the end of the data line segment 62 to receive a gray voltage corresponding to the data signal from the outside. The data line segment 62 is formed to be spaced apart from the gate line 52 by a predetermined distance and extends in the column direction perpendicular to the gate line 52. Since the data line is formed on the same layer as the gate line 52, the data line is formed in a fragment form so as not to be connected to the gate line 52. In addition, the source electrode 64 may be branched to the data line segment 62, and may be formed at one end of the data line segment 62 as shown in FIG. 2A. The drain electrode 66 is positioned opposite the source electrode 64 with respect to the gate electrode 56, and is formed to be spaced apart from the source electrode 64 by a predetermined distance.

In particular, the data lines 62, 64, 66, 68 are formed of the same material on the same layer as the gate lines 52, 54, 56. Therefore, the data lines 62, 64, 66, 68 may be formed in a single layer or more than two layers.

Although not shown in the drawing, a separate storage capacitive electrode may be formed to form the first storage capacitor (see C _st1 of FIG. 1). The separate capacitive electrode may be formed of the same material on the same layer as the gate lines 52, 54, 56 and the data lines 62, 64, 66, and 68. The storage capacitive electrode may be formed of a single layer or a double layer.

The protective layer 80 is formed on the gate lines 52, 54, 56 and the data lines 62, 64, 66, 68, and may be formed of silicon nitride (SiN _x ) or an organic insulating layer. The protective layer 80 includes a first contact hole 81, a source region 22, and a source electrode 64 formed on one end of the data line segment 62 to expose the data line segment 62. The second contact hole 82 exposing a portion of the second contact hole 82, the drain region 23 and the third contact hole 83 exposing a portion of the drain electrode 66, and the fourth contact hole exposing the drain electrode 66 ( 84, a fifth contact hole 85 exposing the gate pad 54 and a sixth contact hole 86 exposing the data pad 68 are formed.

In order to minimize the resistance when the data signal is transmitted, the larger the contact area between the first bridge 91 and the data line segment 62 is, the better. Therefore, the larger the size of the first and sixth contact holes 81 and 86, the better. In an embodiment of the present invention, the contact area is increased by forming a separate connection contact hole 81a such that the first contact hole 81 and the sixth contact hole 86 or the first contact hole 81 are connected to each other. . Here, the width of the connection contact hole 81a may vary depending on the design, for example, may be the same as the width of the first contact hole 81. That is, the contact hole is preferably formed to extend along the data line segment 62 so as to widen the contact area between the data line segment 62 and the first bridge 91.

The pixel electrode 90 is formed of indium tin oxide (ITO) or indium zinc oxide (IZO) on the protective layer 80, and is electrically connected to the drain electrode 66 through the fourth contact hole 84. . In addition, at least a portion overlaps with the gate line 52 of the previous stage to form a second sustain capacitor (see C _{st2 in} FIG. 1).

The first bridge 91 serves to electrically connect adjacent data line segments 62. That is, the first bridge 91 connects the data line fragments 62 through the first contact hole 81. When the data line segments 62 formed to be spaced apart from each other are connected through the first bridge 91 to apply the data signal to the data pad 68, the data lines 62 and the data lines 62 are separated from each other. 64, 66, 68) may be large. Therefore, the first bridge 91 extends along the data line segment 62 and widens the contact area between the data line segment 62 and the first bridge 91 through the connection contact hole 81a to increase the resistance. Can be reduced.

The second bridge 92 electrically connects the source electrode 64 and the source region 22. The third bridge 93 electrically connects the drain electrode 66 and the drain region 23. The source electrode 64 and the source region 22, the drain electrode 66 and the drain region 23 are simultaneously formed to form the source electrode 64 and the source region 22, the drain electrode 66 and the drain region 23. Since the insulating layer 21 is formed in between, such a connection means is calculated | required.

Although not shown in the drawing, the first bridge 91 and the second bridge 92 may be connected to each other, and the third bridge 93 and the pixel electrode 90 may be connected to each other.

The auxiliary gate pad 94 and the auxiliary data pad 98 are electrically connected to the gate pad 54 and the data pad 68 through the fifth contact hole 85 and the sixth contact hole 86, respectively. The auxiliary gate pad 94 and the auxiliary data pad 98 complement the contact with the external circuit device and protect the gate pad 54 and the data pad 68. Here, the auxiliary data pad 98 may be connected to the first bridge 91 as shown in FIG. 2A, but is not limited thereto.

Hereinafter, a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3 to 5B, 2A, and 2B.

Referring to FIG. 3, first, the buffer layer 11, the semiconductor layer 20, the insulating layer 21a, the first conductive layer 40a, and the second conductive layer 40b are sequentially formed on the insulating substrate 10. do. The buffer layer 11, the semiconductor layer 20, and the insulating layer 21a may be formed to have a thickness of about 300 μs to 600 μs, 500 μs to 1500 μs, and 300 μs to 600 μs using chemical vapor deposition (CVD). have. The first and second conductive layers 40a and 40b include chromium (Cr) / aluminum (Al) (or aluminum alloy), aluminum (Al) / molybdenum (Mo), chromium (Cr), or molybdenum-tungsten alloy (MoW). Aluminum (Al) is possible. Such metals may be deposited to a thickness of 1500 kV to 3000 kV using a sputtering method.

Thereafter, photoresist films are formed on the first and second conductive layers 40a and 40b to a thickness of 1 μm to 2 μm and then patterned to form photoresist patterns 112 and 114. In this case, the photoresist patterns 112 and 114 are positioned in the region A1 in which the gate lines 52, 54, and 56 are to be formed, and the region A2 in which the data lines 62, 64, 66, and 68 are to be formed. The first portion 112 is formed thicker than the second portion 114 located in the region B in which the source and drain regions 22 and 23 are to be formed. All the photoresist films of the other portions C are removed. In this case, the ratio of the thicknesses of the first and second portions 112 and 114 may be adjusted differently according to the process conditions in the etching process.

As such, as a method of varying the thickness of the photoresist patterns 112 and 114 according to the position, a slit or a grid-shaped pattern may be formed or a translucent film may be used, but is not limited thereto. Here, the line width of the pattern located between the slits or the spacing between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used during exposure, and in the case of using a translucent film, in order to control the transmittance when fabricating a mask. Thin films having different transmittances or thin films having different thicknesses may be used.

When the light is irradiated onto the photoresist film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the light is not emitted at the part where the slit pattern or the translucent film is formed. The part covered by the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only the portion where the polymer molecules are not decomposed is left, so that the portion irradiated with less light may form a photoresist layer having a thickness thinner than the portion where the light is not irradiated at all. In this case, when the exposure time is extended, all the polymers are decomposed, so it is necessary to appropriately adjust the exposure time.

4A and 4B, the photoresist patterns 112 and 114 are etched as etching masks. That is, the other portion C removes all of the second and first conductive layers 40b and 40a of FIG. 3, the insulating layer 21a of FIG. 3, and the semiconductor layer 20, thereby removing the gate wirings 52, 54, 56, the data line segment 62 is formed, and the region B in which the source and drain regions 22 and 23 are to be formed includes the second and first conductive layers (40b and 40a in FIG. 3) and the insulating layer (as shown in FIG. Remove 21a). Thereafter, n ⁺ ions are implanted to complete the source and drain regions 22 and 23.

5A and 5B, first, the photoresist patterns 112 and 114 are removed using ashing. Thereafter, silicon nitride (SiN _x ) is deposited on the resultant, or an organic insulating film is coated. A portion of the first contact hole 81, the source region 22, and the source electrode 64 are formed on one end of the data line segment 62 to expose the data line segment 62 using a dry etching process. A third contact hole 83 exposing a portion of the second contact hole 82, a drain region 23, and a drain electrode 66, a fourth contact hole 84 exposing the drain electrode 66, and a gate. A fifth contact hole 85 exposing the pad 54 and a sixth contact hole 86 exposing the data pad 68 are formed to complete the protective layer 80. In this case, the contact area may be increased by forming a separate connection contact hole 81a such that the first contact hole 81 and the sixth contact hole 86 or the first contact hole 81 are connected to each other. That is, the contact hole is preferably formed to extend along the data line segment 62 so as to widen the contact area between the data line segment 62 and the first bridge 91.

Referring again to FIGS. 2A and 2B, a transparent conductive material such as an IZO film or an ITO film is deposited on the protective layer 80 to a thickness of 400 kW to 500 kW using a sputtering method. Thereafter, the pixel electrode 90, the first to third bridges 91, 92, and 93, the auxiliary gate pad 94, and the auxiliary data pad 98 are formed using an etching process using a mask. Here, the auxiliary data pad 98 may be connected to the first bridge 91 as shown in FIG. 2A. The first bridge 91 extends along the data line segment 62 and is formed to widen the contact area between the data line segment 62 and the first bridge 91 through the connection contact hole 81a to increase the resistance. Can be reduced.

The pixel electrode 90 is electrically connected to the drain electrode 66 through the fourth contact hole 84. The first bridge 91 electrically connects the adjacent data line segments 62, and the second and third bridges 92 and 93 connect the source electrode 64, the source region 22, and the drain electrode 66, respectively. And drain regions 23 are electrically connected.

6A is a layout diagram of a thin film transistor substrate according to another exemplary embodiment of the present invention. FIG. 6B is a cross-sectional view taken along line BB ′ of FIG. 6A. 2A and 2B, the same reference numerals are used for the same elements, and detailed descriptions of the corresponding elements will be omitted.

Another embodiment of the present invention exposes a portion of the first contact hole 81 and the source region 22 and the source electrode 64 formed at one end of the data line segment 62 to expose the data line segment 62. The second contact hole 82 can be connected using the connection contact hole 82a. In addition, the connection contact hole 83a uses the third contact hole 83 for exposing a part of the drain region 23 and the drain electrode 66 and the fourth contact hole 84 for exposing the drain electrode 66. Can be connected.

The thin film transistor substrate according to the exemplary embodiments of the present invention may be completed using only three masks. That is, gate wiring, data line segments, source and drain regions are formed using the first mask, a protective layer having a plurality of contact holes is formed using the second mask, and a plurality of bridges are formed using the third mask. And a pixel electrode. Thus, since the process can be simplified, productivity can be increased and costs can be reduced.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the thin film transistor substrate and the manufacturing method according to the present invention as described above has the following effects. By forming the thin film transistor substrate using three masks, the process can be simplified. Therefore, productivity is improved and cost is reduced.

Claims (12)

Insulating substrate; A semiconductor layer formed on the insulating substrate and including a source / drain region; A plurality of gate lines extending in one direction on the semiconductor layer; A plurality of data line segments formed on the semiconductor layer spaced apart from the plurality of gate lines by a predetermined distance and extending in a direction perpendicular to the plurality of gate lines; And And a first bridge electrically interconnecting the plurality of data line segments. The method of claim 1, And the first bridge extends along each of the data line segments. The method of claim 2, And a protective layer formed on each of the data line segments and having at least one contact hole, wherein the contact holes extend along each of the data line segments. The method according to any one of claims 1 to 3, The thin film transistor substrate further comprises a source electrode connected to each of the data line segments, and a second bridge connecting the source electrode and the source region. The method of claim 4, wherein The thin film transistor substrate of which the first bridge and the second bridge are electrically connected. The method of claim 4, wherein And a drain electrode formed to be spaced apart from the source region by a predetermined distance, and further comprising a third bridge connecting the drain electrode and the drain region. Sequentially forming a semiconductor layer, an insulating layer, and a conductive layer on the insulating substrate; A plurality of gate lines extending in one direction on the insulating substrate, a plurality of gate lines formed spaced apart from the plurality of gate lines by a predetermined distance, and extending in a direction perpendicular to the plurality of gate lines, respectively; Forming source / drain regions formed in alignment with both sidewalls of the gate electrode; And Forming a first bridge electrically interconnecting the plurality of data line segments. The method of claim 7, wherein And the first bridge extends along each of the data line segments. The method of claim 8, Before forming the first bridge, forming a protective layer having at least one contact hole on each data line segment, wherein the contact hole extends along each data line segment. Method of manufacturing a substrate. The method according to any one of claims 7 to 9, And forming a source electrode connected to each of the data line segments, and forming a second bridge connecting the source electrode and the source region. The method of claim 10, And the first bridge and the second bridge are electrically connected to each other. The method of claim 10, Forming a drain electrode spaced apart from the source region by a predetermined distance, and forming a third bridge connecting the drain electrode and the drain region to each other.

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