KR20080002258A - Method of manufacturing a thin film transistor substrate - Google Patents

Abstract

A method for fabricating a TFT substrate is provided to decrease the number of masks used in fabricating a TFT substrate by using three masks. After a first conductive layer(110) is formed on a substrate(100), a predetermined region of the first conductive layer is patterned to form a gate interconnection in a first mask process. After a gate insulation layer(120), an active layer(130) and a second conductive layer(140) are formed on the resultant structure, a predetermined region of the second conductive layer and the active layer is patterned to form a data interconnection in a second mask process. After a passivation layer(170) is formed on the resultant structure, a predetermined region of the passivation layer is patterned to form a contact hole. After a third conductive layer is formed, a lift-off process is performed to form a pixel electrode in a third mask process. The substrate can include glass, quartz, ceramic or plastic. The gate interconnection can include a gate electrode, a gate line connected to the gate electrode, and a gate pad.

Description

Method of manufacturing a thin film transistor substrate

1 is a plan view of a thin film transistor substrate to which the present invention is applied.

2 (a) to 2 (g) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 substrate 110 first conductive film

120: gate insulating film 130: active layer

140: second conductive film 150: first photosensitive film

160: second mask 170: protective film

180: second photosensitive film 190: third mask

200: third conductive film

The present invention relates to a method for manufacturing a thin film transistor (TFT) substrate, and more particularly, to a method for manufacturing a thin film transistor substrate capable of reducing the number of processes and cost by reducing the number of masks required for the manufacturing process of the thin film transistor substrate. will be.

In general, a thin film transistor substrate is used as a circuit board for independently driving each pixel in a liquid crystal display (LCD) or an organic electroluminescent (EL) display. A gate line (or scan signal line) for transmitting a scan signal and a data line (or image signal line) for transferring an image signal are formed on the thin film transistor substrate. The thin film transistor may include a thin film transistor connected to the gate wiring and a data wiring, a pixel electrode connected to the thin film transistor, a gate insulating film for insulating the gate wiring, and a protective film for insulating the thin film transistor and the data wiring. The thin film transistor includes an active layer used as a gate electrode and a channel as part of a gate wiring, a source electrode and a drain electrode as part of a data wiring, a gate insulating film and a protective film. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

However, a plurality of components constituting the thin film transistor substrate are manufactured by repeating a deposition process, a cleaning process, a photo process using an mask, and an etching process. That is, the gate electrode, the active layer, the source electrode and the drain electrode, the protective layer, and the pixel electrode of the thin film transistor substrate are repeatedly formed by deposition, cleaning, photographing, and etching processes.

However, the photo and etching process is expensive. In the past, six or five masks were used. However, in order to reduce manufacturing costs, a method of manufacturing a thin film transistor substrate using four masks has been developed.

However, despite the manufacture of the thin film transistor substrate using the four masks described above, it is necessary to further reduce the number of masks in order to further reduce the process cost.

On the other hand, the photo and etching process using a mask is a long time complicated process consisting of a series of processes such as photoresist coating, photography, exposure, development, etching, photoresist film removal, cleaning, etc., and occupies most of the processes for manufacturing a liquid crystal display device. . Therefore, most manufacturers seek to improve the productivity of liquid crystal displays by reducing the mask process.

An object of the present invention is to provide a method for manufacturing a thin film transistor substrate that can reduce the number of masks and the process cost and number of processes.

Another object of the present invention is to provide a method of manufacturing a thin film transistor substrate which can reduce the number of masks and the process cost by reducing the number of masks by simultaneously performing protective film patterning and pixel electrode formation using multiple exposure masks.

According to one or more exemplary embodiments, a method of manufacturing a thin film transistor substrate includes: a first mask process of forming a gate wiring by patterning a predetermined region after forming a first conductive film on an upper portion of the substrate; A second mask process of forming a data wiring by forming a gate insulating film, an active layer, and a second conductive film over the entire structure, and then patterning predetermined regions of the second conductive film and the active layer; And a third mask process of forming a contact hole by patterning a predetermined region of the protective film after forming a protective film over the entire structure, forming a third conductive film, and then lifting off to form a pixel electrode.

Preferably, the substrate is an insulating substrate including glass, quartz, ceramic, or plastic, and the gate wiring includes a gate electrode, a gate line connected to the gate electrode, and a gate pad.

The second mask process may include sequentially forming the gate insulating film, the active layer, and the second conductive film on the substrate on which the gate wiring is formed; Forming a photoresist film on the second conductive film and patterning the photoresist film by an exposure and development process using the second mask having at least three regions in which light transmittance is different; And selectively etching the second conductive layer and the active layer using the patterned photoresist as an etch mask to form the data line including a data line, a source electrode, a drain electrode, and a data pad, and simultaneously determine a channel. do.

The second mask includes a first transmission region, a second transmission region that transmits less light than the first transmission region, and a blocking region that completely blocks the light, wherein the photosensitive film exposed by the first transmission region The second conductive film and a predetermined region of the active layer are etched by an etching process using one region of the mask, and the second conductive process is performed by using an region of the photosensitive film exposed by the second transmission region as a mask. A predetermined region of the film is etched, and the second conductive film and the active layer are not etched by one region of the photosensitive film that is not exposed by the blocking region.

The second mask includes a slit mask for adjusting the exposure amount by adjusting the width and spacing of the slit.

The third mask process may include: forming a protective film and a photoresist film on an entire structure, and then patterning the photoresist film in an exposure and development process using the third mask having at least four regions having different amounts of light transmission; Selectively etching the passivation layer and the gate insulating layer using the patterned photoresist as an etch mask to form a contact hole exposing a region of the gate wiring and a region of the data wiring; And forming an auxiliary gate pad and a pixel electrode by removing the photoresist film remaining after the third conductive film is formed over the entire structure and the third conductive film remaining on the photoresist film.

The third mask includes a first transmission region, a second transmission region that transmits less light than the first transmission region, a third transmission region that transmits less light than the second transmission region, and a blocking region that completely blocks the light. And a contact hole for etching a predetermined region of the passivation layer and the gate insulating layer by using an area of the photosensitive layer exposed by the first transmission region as a mask to expose a region of the gate wiring. And a predetermined region of the passivation layer is etched by using an area of the photosensitive film exposed by the second transmission area as a mask to form a contact hole for exposing a region of the data line, and the third transmission. A predetermined region of the passivation layer may be exposed by an etching process using one region of the photosensitive layer exposed by the region as a mask. , But the protective film is not etched by the one region of the photoresist that are not exposed by the cut-off region.

The third mask includes a slit mask for adjusting the exposure amount by adjusting the width and interval of the slit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a thin film transistor substrate to which the present invention is applied.

Referring to FIG. 1, the thin film transistor substrate 10 includes a thin film transistor including a gate electrode 24, an active layer 30, a source electrode 44, and a drain electrode 46, and the pixel electrode 62 includes a matrix ( matrix).

The gate electrode 24 is connected to the gate line 22 formed in the horizontal direction, and a gate pad 26 to which a scan signal is applied from the outside is formed at the end of the gate line 22. The gate line 22, the gate electrode 24, and the gate pad 26 are simultaneously formed of the same material, and all of them are referred to as gate wirings.

The source electrode 44 is connected to the data line 42 formed in the vertical direction, and a data pad 48 to which an image signal is applied from the outside is formed at the end of the data line 42. In addition, a portion of the source electrode 44 is separated to form a drain electrode 46. The data line 42, the source electrode 44, the drain electrode 46, and the data pad 48 are simultaneously formed of the same material, all of which are referred to as data wirings.

The gate wiring and the data wiring are insulated from each other by an insulating film, and a plurality of gate lines 22 and a plurality of data lines 42 are formed to cross each other on the substrate 10 to define a unit pixel.

The pixel electrode 62 is formed in the unit pixel region. In addition, the pixel electrode 62 is electrically connected to the drain electrode 46 through the contact hole 54, and overlaps the gate line 22 to form a capacitor. Therefore, when a scan signal is applied to the gate pad 26 and an image signal is applied to the data pad 48, the thin film transistor formed near the intersection of the gate line 22 and the data line 42 is turned on. As a result, a driving signal is transmitted to the pixel electrode 62, and even if the thin film transistor is turned off, the signal is maintained until the next scan signal is applied.

On the other hand, the pixel electrode 62 is electrically connected to the drain electrode 46 through the second contact hole 54, and the gate pad 26 is formed through the first and third contact holes 52 and 56, respectively. And an auxiliary gate pad 64 and an auxiliary data pad 66 electrically connected to the data pad 48. The pixel electrode 62, the auxiliary gate pad 64, and the auxiliary data pad 66 are preferably formed of ITO or IZO, which is a transparent conductive material.

2 (a) to 2 (g) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, taken along line II ′ of FIG. 1. It is sectional drawing which shows in order of the process of a state.

Referring to FIG. 2A, after the first conductive layer 110 is formed on an insulating substrate 100 made of glass, quartz, ceramic, or plastic, a photo and etching using a first mask (not shown) is performed. The first conductive film 110 is patterned by the process. As a result, a gate wiring including the gate electrode 24, a gate line (not shown) connected thereto, and a gate pad 26 is formed. Here, the first conductive layer 110 for forming the gate wiring may be formed in multiple layers, in order to compensate for the disadvantages of the metal or alloy and to obtain desired physical properties. For example, aluminum (Al) or aluminum alloy (Al alloy) is used as the underlying layer and chromium (Cr), molybdenum (Mo), molybdenum (Mo) -tungsten (W) or molybdenum (Mo)-tungsten nitride (WN) ) May be formed as a double layer using the upper layer. The lower layer uses aluminum or aluminum alloy with low specific resistance to prevent signal resistance due to wiring resistance, and the upper layer is used to compensate for the shortcomings of aluminum or aluminum alloy, which is weak in corrosion resistance by chemicals and easily oxidized to cause disconnection. It is to use chromium, molybdenum, molybdenum-tungsten or molybdenum-tungsten nitride which are highly corrosion resistant to chemicals.

Referring to FIG. 2B, the gate insulating layer 120 and the active layer are formed on the entire structure in which the gate electrode 24, the gate line (not shown), and the gate pad 26 are formed by the first conductive layer 110. 130 and the second conductive film 140 are sequentially formed. The gate insulating layer 120 may be formed using one or more insulating materials including an inorganic insulating material including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ) having excellent adhesion to a metal material and excellent insulating breakdown voltage. have. In addition, the active layer 130 is formed using an amorphous silicon film. The second conductive layer 140 may be formed of a single metal layer, and may be formed of multiple layers to compensate for the disadvantages of the metal or alloy and to obtain desired physical properties. For example, the second conductive layer 140 may be formed of a single layer of chromium (Cr) and may be formed of a triple layer of molybdenum (Mo), aluminum (Al), and molybdenum (Mo).

Referring to FIG. 2C, after forming the first photoresist film 150 on the second conductive film 140, the first photoresist film 150 is patterned by an exposure and development process using the second mask 160. . Here, the second mask 160 includes at least three regions having different transmission amounts, for example, a structure including a completely transmissive region A, an intermediate transmissive region B, and a completely blocked region C. Here, the completely transmissive region A is a region which transmits 100% of light, the completely blocking region C is a region which blocks 100% of light, and the intermediate transmissive region B is a fully transmissive region A. It is an area which can transmit the intermediate light of the complete blocking area C, for example, it is an area which transmits 50% of light. A slit mask or a halftone mask may be used as the second mask 160 in order to configure the second mask 160 to have at least three regions having different transmission amounts. The slit mask is a mask for controlling the amount of light to be transmitted by adjusting the width and spacing of the slit. The narrower and wider the slit transmits more light, and the wider and narrower the slit to transmit less light. Meanwhile, the completely transmissive region A of the second mask 160 corresponds to the region where the second conductive layer 140 and the active layer 130 are completely etched, and the intermediate transmissive region B is the second conductive layer 140. ) Corresponds to the region where the channel to be etched is to be formed, and the complete blocking region C includes the data line 42, the source electrode 44, and the drain electrode where the second conductive layer 140 and the active layer 130 are not etched. Corresponds to 46 and data pad 68. When the first photoresist film 150 is exposed and developed by using the second mask 160 configured as described above, the first photoresist film 150 in the part completely exposed by the completely transmissive region A is completely removed, and the intermediate transmission is performed. The first photoresist film 150 of the portion exposed to the middle portion by the region B remains a certain thickness, and the first photoresist film 150 of the portion not exposed by the completely blocked region C remains completely. That is, the first photosensitive film 150 has a shape having a step according to the exposure amount.

Referring to FIG. 2 (d), when the first photosensitive film 150 patterned to have a step in an exposure and development process using the second mask 160 is etched using an etching mask, preferably an etch back process, As the first photosensitive layer 150 is etched, a portion of the second conductive layer 140 and a portion of the active layer 130 are etched. That is, since the first photosensitive film 150 of the part completely exposed by the completely transmissive region A of the second mask 160 is completely removed, the second conductive film 140 and the active layer 130 of the corresponding part are completely removed. The etch is completely etched to expose the gate insulating layer 120. In addition, since the first photoresist film 150 of the portion partially exposed by the intermediate transmission region B of the second mask 160 remains at a predetermined thickness, only the second conductive film 140 is etched so that the active layer 130 is etched. Exposed. In addition, since the first photosensitive film 150 of the portion not exposed by the complete blocking region C of the second mark 160 remains completely, the second conductive film 140 and the active layer 130 of the corresponding portion are left. Will not be etched. Accordingly, although only the source electrode 44 and the drain electrode 46 are shown in the cross-sectional view of FIG. 2 (d), as shown in FIG. 1, the data line 42, the source electrode 44, the drain electrode 46 and At the same time as the data pad 68 is formed, the channel is established.

Referring to FIG. 2E, after removing the remaining first photoresist film 150, a protective film 170 is formed on the entire structure. After the second photoresist layer 180 is formed on the passivation layer 170, the second photoresist layer 180 is patterned by an exposure and development process using the third mask 190. Here, the third mask 190 includes at least four regions in which the light transmittance is different from each other, and is less than the first transmission region A and the first transmission region A, which are completely transmission regions that transmit 100% of light. Second transmission region B, which is an intermediate transmission region that transmits light, for example 70% of light, and a third transmission region that is an intermediate transmission region that transmits less light than the second transmission region B, for example, 50% of the light ( C) and a fourth transmission region D, which is a complete blocking region that blocks 100% of light. A slit mask, a halftone mask, or the like may be used as the third mask 190 in order to configure the third mask 190 to have at least four regions having different transmittances. The slit mask is a mask for controlling the amount of light transmitted by adjusting the width and spacing of the slit as described above. The narrower and wider the slit transmits more light, and the wider and narrower the slit, the smaller the light. Permeate. Therefore, the width and spacing of the slits can be adjusted to produce a mask having a plurality of transmission regions having different transmittances. Meanwhile, in the first transmission region A of the third mask 190, the protective layer 170 and the gate insulating layer 120 are completely etched to form a first contact hole 52 through which the gate pad 26 is exposed. The second transmission region B corresponds to a region in which only the passivation layer 170 is etched to expose the drain electrode 46. In addition, the third transmission region C corresponds to a region where the auxiliary gate pad 64 and the pixel electrode 62 are to be formed, and the fourth transmission region D may be etched by the passivation layer 170 and the gate insulating layer 120. Corresponds to an area that does not When the second photoresist layer 180 is exposed and developed by using the third mask 190 configured as described above, the second photoresist layer 180 in the part completely exposed by the first transmission region A is completely removed. The second photoresist layer 180 of the portion exposed to the intermediate degree by the second and third transmission regions B and C remains a certain thickness, and the second photoresist layer 180 of the portion not exposed by the fourth transmission region D is maintained. ) Remains completely. That is, the second photosensitive film 180 has a shape having a step according to the exposure amount.

Referring to FIG. 2 (f), an etching process, preferably an etch back process, is performed by using the second photosensitive layer 180 patterned to have a step in an exposure and development process by the third mask 190 as an etching mask. As the second photoresist layer 180 is etched, a portion of the passivation layer 170 and the gate insulating layer 120 are etched. That is, since the second photoresist layer 180 of the portion completely exposed by the first transmission region A of the third mask 190 is completely removed, the passivation layer 170 and the gate insulating layer 120 of the portion corresponding thereto are removed. A first contact hole 52 is formed to be completely etched to expose the first conductive layer 110. In addition, since the second photosensitive layer 180 of the portion exposed by the second transmission region B remains at a predetermined thickness, only the protective layer 170 is etched to form a part of the second conductive layer 140, that is, the drain electrode 46. The second contact hole 54 exposing the gap is formed. In addition, since the second photosensitive layer 180 of the portion exposed by the third transmission region C remains thicker than the portion exposed by the second transmission region B, only the second photosensitive layer 180 is removed during etching. The protective film 170 is exposed. On the other hand, since the second photoresist film 180 of the portion not exposed by the fourth transmission region D of the third marks 190 remains completely, the second photoresist film 180 remains a predetermined thickness. A third conductive film 200 including an ITO film or an IZO film is formed on the entire structure.

Referring to FIG. 2 (g), when the second photosensitive layer 180 is removed using an organic solvent, for example, a solvent solution, a third conductive layer formed on the second photosensitive layer 180 together with the second photosensitive layer 180 ( 200 is also optionally removed. In this way, the auxiliary gate pad 64 and the pixel electrode 62 are formed.

As described above, according to the present invention, a gate wiring is formed using a first mask, a data wiring and a channel portion are formed using a second mask having at least three different transmittances, and a third having at least four transmittances different from each other. The mask and lift-off methods are applied to form gate pads and pixel electrodes. Accordingly, since the thin film transistor substrate can be manufactured using three masks, the number of masks used for manufacturing the thin film transistor substrate can be reduced. Therefore, the number of processes and the process cost can be drastically reduced.

Claims (9)

A first mask process of forming a gate wiring by forming a first region after forming a first conductive film on the substrate; A second mask process of forming a data wiring by forming a gate insulating film, an active layer, and a second conductive film over the entire structure, and then patterning predetermined regions of the second conductive film and the active layer; And And forming a contact hole by patterning a predetermined region of the protective film after forming a protective film over the entire structure, and forming a pixel electrode by forming a third conductive film and then lifting it off to form a pixel electrode. . The method of claim 1, wherein the substrate is an insulating substrate including glass, quartz, ceramic, or plastic. The method of claim 1, wherein the gate line comprises a gate electrode, a gate line connected to the gate electrode, and a gate pad. The method of claim 1, wherein the second mask process, Sequentially forming the gate insulating film, the active layer, and the second conductive film on the substrate on which the gate wiring is formed; Forming a photoresist film on the second conductive film and patterning the photoresist film by an exposure and development process using the second mask having at least three regions in which light transmittance is different; And Selectively etching the second conductive layer and the active layer using the patterned photoresist as an etch mask to form the data line including a data line, a source electrode, a drain electrode, and a data pad, and simultaneously determine a channel; Method of manufacturing a thin film transistor substrate. The method of claim 4, wherein the second mask includes a first transmission region, a second transmission region that transmits less light than the first transmission region, and a blocking region that completely blocks the light. In the etching process using one region of the photosensitive film exposed by the first transmission region as a mask, a predetermined region of the second conductive layer and the active layer is etched. A predetermined region of the second conductive layer is etched by an etching process using one region of the photosensitive layer exposed by the second transmission region as a mask, And the second conductive film and the active layer are not etched by one region of the photosensitive film not exposed by the blocking region. 6. The method of claim 4, wherein the second mask comprises a slit mask for adjusting an exposure amount by adjusting a width and an interval of the slit. The method of claim 1, wherein the third mask process, Forming a protective film and a photoresist film on the entire structure, and then patterning the photoresist film by an exposure and development process using the third mask having at least four regions in which light transmittance is different; Selectively etching the passivation layer and the gate insulating layer using the patterned photoresist as an etch mask to form a contact hole exposing a region of the gate wiring and a region of the data wiring; And Forming an auxiliary gate pad and a pixel electrode by removing the photoresist film remaining after forming the third conductive film over the entire structure and the third conductive film remaining on the photoresist film. 8. The light emitting device of claim 7, wherein the third mask comprises: a first transmission region, a second transmission region that transmits less light than the first transmission region, a third transmission region that transmits less light than the second transmission region, and light Includes a blocking area that completely blocks In the etching process using one region of the photosensitive film exposed by the first transmission region as a mask, a predetermined region of the passivation layer and the gate insulating layer is etched to form a contact hole exposing one region of the gate wiring, In the etching process using one region of the photosensitive film exposed by the second transmission region as a mask, a predetermined region of the protective layer is etched to form a contact hole exposing one region of the data line. A predetermined region of the passivation layer is exposed by an etching process using one region of the photosensitive layer exposed by the third transmission region as a mask, The protective film is not etched by one region of the photosensitive film that is not exposed by the blocking region. 9. The method of claim 7, wherein the third mask comprises a slit mask for adjusting an exposure amount by adjusting a width and an interval of the slit.

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