KR20060108353A - Multi-layer metallic substrate for fabricating electronic device - Google Patents

Abstract

The present invention forms a base plating layer made of a tin-containing alloy on a copper-based alloy base layer and an intermediate plating layer made of a palladium-containing alloy and an outer plated layer made of gold to improve solder wettability, wire bonding and corrosion resistance. A multilayer metal substrate for electronic device manufacturing. In the present invention, by using a tin alloy as the base plating layer, it prevents the diffusion of copper, which is a base metal, and improves weldability when mounting the manufactured semiconductor chip package on a printed circuit board, and does not have magnetic properties due to the characteristics of the tin alloy. ), And also contributes to solving the problem by eliminating the use of Ni in relation to Ni allergy which is excellent in corrosion resistance and is a problem in comparison with the conventional nickel layer.

Multi-layer, Base plated layer, Tin-copper alloy, Substrate, Semiconductor

Description

Multi-layer Metallic Substrate for fabricating Electronic Device

1 is a view showing an example of use of a conventionally used substrate,

2 is a cross-sectional view showing a structure as an example of a conventional use of the substrate shown in FIG.

3 is a cross-sectional view of a substrate for manufacturing a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

1, 11: base metal layer 2, 12: base plating layer

3, 13: middle plating layer 4, 14: outer plating layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for manufacturing an electronic device, and in particular, a base plating layer made of a tin-containing alloy is formed on a copper-based alloy base layer, and an intermediate plating layer made of a palladium-containing alloy and an outer plated layer made of gold are formed thereon for solder wettability and wire. The present invention relates to a multilayer metal substrate for electronic device manufacturing having improved bonding and corrosion resistance.

As is well known, a substrate for manufacturing an electronic device is an intermediary means for electrically connecting an electrical and electronic device such as a semiconductor chip and a printed circuit board. That is, as an example, a leadframe, which is a substrate used in a semiconductor device, is one of core components constituting a semiconductor package together with a semiconductor chip, and leads that connect the inside and the outside of the semiconductor package. ) And a supporting frame supporting the semiconductor chip.

As shown in FIG. 1, the lead frame of the semiconductor includes a die pad part 34 which is basically a semiconductor memory element mounted thereon and maintains a static state, and an inner lead part 31 connected to the chip by wire bonding. And an outer lead portion 32 for connecting to an external circuit, wherein the wire-bonded chip and the wire-bonded inner lead portion are sealed by epoxy molding compound (EMC), which is a resin protective film, to seal the semiconductor package. Configure. The leadframe body 30 of a semiconductor having such a structure is usually manufactured through a stamping process or an etching process.

However, in the semiconductor package assembly process of the above structure, in order to maintain good adhesion between the die chip and the wire bonding between the semiconductor chip and the inner lead of the lead frame, it is common to plate a metal material on the pad and the inner lead. After molding, Sn-Pb solder plating is performed on a predetermined portion of the outer lead portion in order to improve solderability for mounting the substrate.

However, in the solder plating process, since the plating solution generally penetrates to the inner lead region, there is a problem that an additional process must be performed to remove the plating solution.

Proposed in order to solve this problem is a pre-plated frame (pre-plated frame) method, to form a plating layer by pre-plating a material having excellent solder-wettability to the semiconductor substrate before assembling the semiconductor package.

In such a method of forming a plating layer on a semiconductor substrate, a copper-containing alloy or a nickel-containing alloy is used as a substrate for manufacturing a semiconductor device, and various plating layers are formed on the surface of the substrate to prevent oxidation of the surface and improve solderability with electrical and electronic devices. It has been used to form.

Conventionally, as a method for achieving the above object, a tin (Sn) / lead (Pb) alloy is used by plating on the surface of a copper substrate, but various methods for replacing it are regulated as the environment-friendly material of lead. This has been proposed.

An example of such a prior art is Japanese Patent Application Laid-open No. Hei 4-115558. As shown in Fig. 2, Japanese Patent Application Laid-open No. Hei 4-115558 has a base plating layer 12 made of a nickel-containing alloy on a base metal layer 11 made of a copper-containing alloy. ), A palladium-containing alloy layer 13 is formed thereon as an intermediate plating layer, and a gold plating layer 14 is formed thereon.

However, in the conventional method disclosed in the related art, palladium has excellent bonding property and wire bonding property due to the characteristics of palladium, but palladium is oxidized during the high temperature semiconductor assembly process, so that the plating layer is stiffened and the melting point is increased, thereby lowering the solderability.

The present invention is made to solve the problems of the prior art as described above, to prevent the oxidation of the copper-based substrate, to increase the bonding bonding during the wire bonding process and to enhance the bonding strength with the molding compound to improve the reliability of the semiconductor chip package It is an object of the present invention to provide a multilayer metal substrate for manufacturing electronic devices.

To this end, the present invention is a base metal layer made of a copper-containing alloy;

An underlying plating layer made of a tin alloy formed on at least one side of the base metal layer;

An intermediate plating layer made of a palladium-containing alloy formed on the underlying plating layer; And,

Technical problem is achieved by providing a multilayer metal substrate for electronic device manufacturing, including an outermost plating layer made of gold formed on the intermediate plating layer.

The above and other objects and advantages of the present invention, and the effects of the present invention will become apparent from the following detailed description of the present invention made in connection with the preferred embodiments.

Hereinafter, the present invention will be described in detail with reference to the preferred embodiments.

The substrate for semiconductor manufacture of the present invention includes a base metal layer (1) made of a copper-containing alloy as shown in FIG. A base plating layer (2) made of a tin alloy formed on at least one side of the base metal layer; An intermediate plating layer (3) made of a palladium-containing alloy formed on the underlying plating layer; And an outermost plating layer 4 made of gold formed on the intermediate plating layer.

The present invention improves weldability when mounting a manufactured semiconductor chip package on a printed circuit board while preventing diffusion of copper, which is a base metal, and is not affected by RF (Radio Frequency) because it has no magnetic properties due to the characteristics of tin alloy. In addition, the base metal layer 2 is composed of a tin alloy layer which is excellent in corrosion resistance compared to the conventional nickel layer and contributes to solving the problem by eliminating the use of Ni in relation to Ni allergy which is becoming a problem recently. There is this.

In the present invention, the base plating layer 2 made of the tin-containing alloy preferably has a thickness of 10 to 100 µ ", and the intermediate plating layer 3 made of a palladium-containing alloy is 1 to 4 µ", and the gold plating layer formed on the intermediate plating layer ( 4) is 0.5 to 4 탆 thick.

In the present invention, the copper-containing base alloy includes a case made of only copper, and the case of a palladium-containing alloy also includes a case made of only palladium.

In the present invention, electroplating or electroless plating can be used as the plating method. In general, although an electroless plating method is used for the purpose of obtaining a uniform plating layer, the present invention can of course adopt both an electroplating method or an electroless plating method.

Meanwhile, in the present invention, the tin alloy layer constituting the base plating layer may be formed of tin and a binary alloy made of a kind of metal selected from the group consisting of Cu, Ag, Bi, Sb, and Fe.

Further, in the present invention, the tin alloy layer may be a ternary alloy made of Sn and Cu and one metal selected from the group consisting of Sb, Ti, Se, Au, Pd, and Zn.

Furthermore, in the present invention, the tin alloy layer is preferably composed of 20% by weight to 80% by weight of Sn and 80% by weight to 20% by weight of Cu, and most preferably by 50% by weight. If the content of tin in the tin alloy layer is less than 20% by weight, the corrosion resistance and crack resistance is lowered, and if more than 80% by weight, the wire bonding resistance is poor, so the range composition.

In more detail, a tin alloy layer is plated as a base plating layer 2 on a base metal layer 1 made of a copper-containing alloy that is a base metal of a substrate such as a lead frame for manufacturing a semiconductor device. It is fused to support the soldered body and to maintain adhesion of the top plating layer and the base metal while maintaining the smoothness of the top plating layer. It improves the weldability when mounting on the substrate, and has no advantage of being affected by RF (Radio Frequency) because it is not magnetic due to the characteristics of the tin alloy.

In addition, it is excellent in corrosion resistance compared with the conventional nickel layer and can contribute to solving the problem by eliminating the use of Ni in relation to Ni allergy which is a problem recently. Such a tin-containing alloy layer as the base metal layer 2 is formed to a thickness of 10 ~ 100μ ", it is difficult to perform the role as a base metal layer below 10μ" and thicker than 100μ "when forming the forming process according to the assembly process Cracks may occur.

In the present invention, the intermediate plating layer 3 made of a palladium-containing alloy formed on the base plating layer 2 is chemically stable, has good solderability and wire bonding property, is dense in structure, and has no migration phenomenon. Since the intermediate plating layer 3 has good adhesion between the base metal layer 2 and the outer metal layer 4, the plating is easy, plating is easy, and diffusion and oxidation of the base metal and the base metal layer in the thermal environment are prevented and the outer plating layer is formed. Serves to help maintain its unique quality characteristics. As a suitable thickness for this purpose, the plating is formed to a thickness of 1 to 4 μ "(0.025 to 0.1 μm). If the thickness is smaller than 1 μ", the plate may not sufficiently cover the underlying plated layer and thus may not function properly as an intermediate plated layer. As the thickness increases, the effect of quality improvement is insignificant, but the price of the product rises and the solder wettability decreases.

On the other hand, the gold plating layer constituting the outermost plating layer 4 acts as a protective layer of the intermediate plating layer 3 made of a palladium (Pd) -containing alloy and can prevent deterioration due to oxidation of the intermediate plating layer 3, It is possible to maintain the original solderability of the plating layer, thereby shortening the solder wetting time and improving the workability can be expected. The gold plating layer 4 formed on the intermediate plating layer has a thickness of 0.5 to 44 μ ″ (0.0125 to 0.1 μm). By forming in such a thickness range, proper corrosion resistance, wire bonding property, mold adhesion property and solderability can be maintained well. .

Hereinafter, the present invention will be described in more detail with reference to the preferred embodiments.

Examples 1-5

Table 1 below shows Examples 1 to 5 of the present invention, but it is not intended to limit the present invention. In this embodiment, experiments were conducted under different conditions in order to derive the composition of the most preferable alloy layer of each plating layer. The specific method of the experiment for evaluating the physical properties is as follows. That is, the gold (Au) wire bonding test was carried out using a bonding pull tester after the wire bonding the sample using a wire bonding equipment.

Solderability The sample is heat-treated at 175 ° C for 7 hours and 30 minutes, and then forcedly aged for 8 hours at 95 ° C and 95% relative humidity. The weldability was then tested according to the MIL-STD-883D method.

On the other hand, the adhesion between the molding compound and the sample was subjected to molding for 90 seconds at a molding temperature of 170 ° C., followed by heat treatment at 175 ° C. for 6 hours, and then carried out an adhesion test between the epoxy molding compound and a substrate for manufacturing a semiconductor device. SAT (Scanning Acoustic Tomograph) test was performed after the test.

The corrosion resistance test was carried out by the KS M 8012 neutral salt spray test method, the concentration of sodium chloride is 40g / ℓ, the compressed air pressure is 1.2kg / ㎠, spraying amount is 1.51ml / 80cm / h, air The saturator temperature was 47 degreeC, the brine tank temperature was 35 degreeC, and the test tank temperature was 35 degreeC. Crack resistance was measured as cracks after thermal shock. The cracks were evaluated after 1000 or more heating cycles (-65 ° C. to 150 ° C.) were treated at 100% RH of 121 ° C. and 2 atm.

division Example 1 Example 2 Example 3 Example 4 Example 5 Remarks  Plated layer Outer plating layer Au (1 μ ") Au (1 μ ") Au (1 μ ") Au (1 μ ") Au (1 μ ")   Substrate Base Metal: Cu Middle plating layer Pd (4 μ ") Pd (4 μ ") Pd (4 μ ") Pd (4 μ ") Pd (4 μ ") Base plated layer (wt%) Sn (20)-Cu (80) (25μ ") Sn (40)-Cu (60) (25μ ") Sn (50)-Cu (50) (25μ ") Sn (60)-Cu (40) (25μ ") Sn (80)-Cu (20) (25μ ") Wire bonding ○ ⊙ ⊙ ○ △ Solderability ○ ○ ⊙ ⊙ ⊙ Molding Bond ⊙ ⊙ ⊙ ⊙ ⊙ Corrosion resistance ○ ○ ⊙ ⊙ ⊙ Crack resistance ○ ○ ⊙ ⊙ ⊙

⊙: Excellent ○: Good △: Normal ×: Poor

Comparative Examples 1 to 5

Meanwhile, for comparison, a substrate for manufacturing a semiconductor device having a conventional structure was manufactured according to a conventional method, and the physical properties thereof were evaluated in the same manner as in Example, and the results are shown in Table 2 below.

division Comparative Example 1 Comparative Example 2 Comparative Example 3 Comparative Example 4 Comparative Example 5 Remarks   Plated layer Outer plating layer - - - - Au (1 μ ")   Substrate Base Metal: Cu Intermediate Plating Layer (wt%) Ag (4 μ ") Pd (4 μ ") Pd (20) -Ag (80) Alloy (4μ ") Pd (4 μ ") Pd (4 μ ") Base plate Ni (25 μ ") Ni (25 μ ") Ni (25 μ ") Sn-Cu Alloy (25μ ") Ni (25 μ ") Wire bonding △ 0 0 0 ⊙ Solderability △  ○ 0 ⊙ ⊙ Molding Bond △ ⊙ ⊙ ⊙ ⊙ Corrosion resistance △ ⊙ ⊙ ⊙ ⊙ Crack resistance 0 ⊙ ⊙ ⊙ ⊙

⊙: Excellent ○: Good △: Normal ×: Poor

Examining the embodiments and comparative examples of the present invention with reference to Table 1, the present examples were excellent in molding bonding under all conditions. However, it can be seen that the bonding properties, solderability, and corrosion resistance to crack resistance change according to the composition ratio of the base plating layer 2 composed of tin alloy. Example 3 As the ratio of tin is increased more than 50% by weight of tin-50% by weight of copper (Examples 4 and 5), the corrosion resistance and crack resistance are improved and the relative proportion of Sn is smaller (Examples 1 and 2). Corrosion resistance and crack resistance decreased. However, as the ratio of Sn is higher than the appropriate level, the solderability is improved, but the bonding property is decreased. This occurs due to the influence of hardness (Hardness) in the nature of tin can be seen as an important variable in the process.

Meanwhile, referring to Table 2, in Comparative Example 1 in which the silver plating layer was formed on the base plating layer composed of nickel or nickel alloy or Comparative Example 2 in which the palladium plating layer was formed, excellent results were not obtained in bonding properties and solderability. In Comparative Example 3 having the palladium-silver alloy layer as the outermost layer, good results were obtained in molding bondability, corrosion resistance, and crack resistance, but bonding and solderability did not reach the excellent level of the present embodiment. In the case of Comparative Example 4 in which the Sn-Cu alloy was formed as the base plating layer instead of the nickel layer and the Pd plating layer was formed thereon, excellent results were obtained in all solderability, molding bondability, corrosion resistance, and crack resistance, but the bonding resistance was deteriorated. Able to know. In Comparative Example 5, the bonding property as described above can be solved to obtain excellent bonding property. However, when the nickel layer is used as the underlying plating layer, the Sn-Cu alloy layer is affected by RF, which is a problem of the aforementioned nickel layer. It is not preferable because of relatively weak corrosion resistance, human hazards due to nickel allergy, relative difficulty of wastewater treatment, and high cost compared with tin alloy.

Although the present invention has been described with reference to the embodiment taking a lead frame as a substrate for manufacturing a semiconductor device as an example, the present invention is not limited thereto, such as a chip on film (PCF), a PCB, a connector (Connector) Of course, the same can be applied to the substrate used in the electronic device.

As described above, according to the substrate for manufacturing an electronic device of the present invention, by using a tin alloy as a base plating layer, it is possible to prevent diffusion of copper, which is a base metal, and to improve weldability when the manufactured semiconductor chip package is mounted on a printed circuit board. Since the tin alloy is not magnetic in nature, it is advantageous in that it is not affected by RF (Radio Frequency).

In addition, it is excellent in corrosion resistance compared with the conventional nickel layer and can contribute to solving the problem by eliminating the use of Ni in connection with Ni allergy which has become a problem recently.

In addition, the use of Sn alloys in the base plated layer allows for easier wastewater treatment than Ni alloys, thus providing an environmentally friendly semiconductor package. The reduction effect can be aimed at.

According to the present invention, since the gold plating layer acts as a protective layer of the palladium intermediate layer in addition to the above effects, the palladium intermediate layer is prevented from being deteriorated by oxidation, thereby maintaining the original solderability of both plating layers and shortening the soldering wetting time. The working time can be improved.

Claims (6)

A base metal layer 1 made of a copper alloy; A base plating layer (2) made of a tin alloy formed on at least one side of the base metal layer; An intermediate plating layer (3) made of a palladium-containing alloy formed on the underlying plating layer; And, And an outer plating layer (4) made of gold formed on the intermediate plating layer. The multilayer metal substrate of claim 1, wherein the tin alloy layer comprises 20 to 80 wt% Sn and 80 to 20 wt% Cu. The multilayer metal substrate of claim 1, wherein the tin alloy layer has a thickness of 10 to 100 μ ″. The multilayer metal substrate of claim 1, wherein the tin alloy layer is a binary alloy made of tin and a metal selected from the group consisting of Cu, Ag, Bi, Sb, and Fe. The multilayer of claim 1, wherein the tin alloy layer is a ternary alloy made of Sn—Cu and one metal selected from the group consisting of Sb, Ti, Se, Au, Pd, and Zn. Metal substrate. The multilayer metal substrate according to claim 1 or 2, which is used in a lead frame, a COF, a PCB, or a connector for semiconductor manufacturing.

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