KR20060102955A - Timing controller - Google Patents

Abstract

The present invention relates to a timing controller in which the ground pin exposed to the outside by partially exposing the copper foil on the back of the mold frame is omitted and the size is reduced. The timing controller of the present invention is a timing controller connected to a PCB. A semiconductor chip for generating a signal, a ground wiring connected to the semiconductor chip to transmit a ground signal, an input / output wiring connected to the semiconductor chip except for the ground wiring, and transmitting an input / output signal, and predetermined of the ground wiring A mold frame in which the semiconductor chip, the ground wiring, and the input / output wiring are embedded, and the solder is provided in the PCB portion and the input / output wiring corresponding to the exposed portion of the ground wiring, and the mold is exposed. Including a plurality of pins formed out of the frame It characterized by true.

Timing Controllers, Copper Foil, Printed Circuit Board (PCB), Pins, Ground

Description

Timing Controller

1 is a block diagram showing a driving circuit of a conventional liquid crystal display device.

Figure 2 is a plan view showing a conventional timing controller and its pins

Figure 3 is a plan view showing the correspondence of the conventional timing controller and the PCB

4 is a plan view showing the correspondence between the timing controller and the PCB of the present invention.

5 is a cross-sectional view of FIG.

* Description of symbols on the main parts of the drawings *

100: timing controller 106: solder

107: pin 110: mold frame

113: copper foil layer 115: semiconductor chip

120: PCB

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display, and more particularly, to a timing controller in which a size of a copper foil on a rear surface of a mold frame is partially exposed, thereby eliminating a ground pin exposed to the outside and reducing the size.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as the substitute for CRT (Cathode Ray Tube) for mobile image display device because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention has been developed in various ways such as a television and a computer monitor for receiving and displaying broadcast signals.

In order to use such a liquid crystal display as a general screen display device in various parts, it is a matter of how high quality images such as high definition, high brightness and large area can be realized while maintaining the characteristics of light weight, thinness and low power consumption. Can be.

A general liquid crystal display device may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel includes first and second glass substrates bonded to each other with a predetermined space; It consists of a liquid crystal layer injected between the said 1st, 2nd glass substrate.

Here, the first glass substrate (TFT array substrate) has a plurality of gate lines arranged in one direction at regular intervals, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing a gate line and a data line, and a plurality of thin film transistors switched by signals of the gate line to transfer the signal of the data line to each pixel electrode. Is formed.

The second glass substrate (color filter substrate) includes a light shielding layer for blocking light in portions other than the pixel region, an R, G, and B color filter layers for expressing color colors, and a common electrode for implementing an image. Is formed.

The driving principle of the general liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the arrangement of molecules can be controlled by artificially applying an electric field to the liquid crystal.

Currently, an active matrix LCD, in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner, is attracting the most attention due to its excellent resolution and ability to implement video.

Hereinafter, a conventional liquid crystal display and a timing controller thereof will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a driving circuit of a conventional liquid crystal display.

As shown in FIG. 1, a driving circuit of a conventional liquid crystal display includes a timing controller 10, a data driver 20, a gate driver 30, and an LCD panel 40.

The timing controller 10 receives the synchronization signal (Hsync, Vsync) and the clock signal (DE, MCLK) for displaying the RGB image signal together with the RGB image signal from an external graphic controller (not shown), etc. While outputting the corrected image signals R ', G', and B 'to the data driver 20, a digital signal for driving the data driver 20 and the gate driver 30, i.e., a timing signal, is generated. Output to the drivers 20, 30.

More specifically, the timing controller 10 is a horizontal clock signal (HCLK) and data for the data shift (shift) in the data driver 20 is converted to analog in the data driver 20, the converted analog value LCD The horizontal synchronization start signal STH for instructing the panel 40 to be applied and the load signal LOAD or TP for instructing the loading of the data signals to the data driver 20 are output to the data driver 20, respectively.

In addition, the timing controller 10 may include a gate clock signal for setting the period of the gate-on signal applied to the gate line, a vertical synchronization start signal STV for commanding the start of the gate-on signal, and the gate driver ( An output enable signal (OE; Out Enable) for enabling the output of 30 is output to the gate driver 30.

The data driver 20 receives R, G, and B digital data (R [0: N], G [0: N], and B [0: N]) from the timing controller 10 and stores the received digital data. When a load signal LOAD for commanding the panel 40 to be applied is applied, a voltage corresponding to each digital data is selected and the data signals V1, V2, V3, ..., Vn are applied to the LCD panel 40. (Not shown).

In addition, the data driver 20 outputs data voltages V1, V2, V3,..., And Vn so that the polarities of the pixels arranged on the liquid crystal panel 40 are inverted with each other in each frame. To the data line. At this time, it is necessary to invert the polarity of the pixel every frame, as is already known, in order to prevent the deterioration of the operation because the liquid crystal remains a certain polarity.

The gate driver 30 receives a gate clock signal Gate clk and a vertical line start signal STV from the timing controller 10, including a shift register, a level shifter and a buffer, and a gate driving voltage generator (not shown). Voltages Von, Voff, and Vcom (not shown) are supplied from the timing controller 10 to turn on and off the respective thin film transistors on the liquid crystal panel 40 to apply pixel voltages to the pixels. Block it.

The liquid crystal panel 40 is formed in n data lines, m gate lines arranged orthogonal to the data lines, and formed in a predetermined region arranged in a lattice arrangement between the data lines and the gate lines, and one end thereof is connected to the gate lines. The other end is composed of a thin film transistor and a pixel electrode connected to the data line, and the other end is connected to the pixel electrode, and the gate voltages G1, G2, ..., Gn provided from the gate driver 30 ( As the thin film transistor of the pixel column is turned on as the pixel column is applied to the pixel column, the data voltages D1, D2,..., Dm (not shown) provided from the data driver 20 are applied to the pixel electrode. .

2 is a plan view showing a conventional timing controller and its pins, and FIG. 3 is a plan view showing the correspondence between a conventional timing controller and a PCB.

As shown in FIG. 2, the conventional timing controller 10 includes a plurality of ground pins (G) 55 to provide a plurality of pins 55 and 57 for input from a system and output to a gate driver and a data driver. Equipped. The conventional timing controller 10 includes a mold frame made of a plastic material and a plurality of pins 55 and 57 which come out of the mold frame. Is done.

As shown in FIG. 3, the conventional timing controller 10 is connected to a printed circuit board (PCB) 15 and disposed, and the PCB 15 has an electrical connection between wirings by a gate driver, a data driver, and a TCP film. Connected.

Here, the ground terminal 55 of the timing controller 10 may include both a ground connection of the timing controller 10 and a ground connection of a gate driver, a data driver, and the like.

However, the conventional timing controller as described above has the following problems.

Conventional timing controllers having a plurality of ground terminals externally connected to the PCB have a smaller terminal spacing as the size of the timing controller is integrated, so that defects may occur when connecting to the PCB, and if the terminal spacing is maintained to prevent this, The integration of the timing controller is limited and cannot be reduced beyond a certain level.

An object of the present invention is to provide a timing controller which reduces the size by omitting the ground pin exposed to the outside by partially exposing the copper foil on the back of the mold frame to solve the above problems.

In the timing controller of the present invention for achieving the above object is a timing controller connected to the PCB, a semiconductor chip for generating a ground signal and an input and output signal, a ground wiring connected to the semiconductor chip to transfer the ground signal; An input / output wiring connected to the semiconductor chip to transmit an input / output signal except for the ground wiring, a predetermined frame exposing a predetermined portion of the ground wiring on the rear surface thereof, and a mold frame having the semiconductor chip, the ground wiring and the input / output wiring embedded therein; And a plurality of pins formed outside the mold frame by being connected to the solder and the input / output wires provided in the PCB to correspond to the exposed portions of the ground lines.

The mold frame has a predetermined hole in a portion where the ground wiring is exposed to the outside of the mold frame, and has a predetermined terminal shape of the ground wiring.

The exposed portions of the solder and the ground wiring are hardened by being connected to each other by heat treatment.

Hereinafter, a timing controller of the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view showing the correspondence between the timing controller and the PCB of the present invention, and FIG. 5 is a cross-sectional view of FIG.

4 and 5, the timing controller 100 of the present invention includes a mold frame 110 in which semiconductor chips, internal wirings, and the like are largely embedded, and a plurality of pins coming out of the mold frame 110. 107). In this case, the mold frame 110 may include a semiconductor chip 115, a ground wiring 105 connected to the semiconductor chip 115, and the semiconductor chip 115 for input / output except for the ground wiring 105. A plurality of connected wires 113 are built in. Here, the semiconductor chip 115, the ground wiring 105, and a plurality of wirings 113 for input and output except for the ground wiring 105 are formed on an insulating layer (not shown). The plurality of wirings 113 for input and output except for the ground wiring 105 and the ground wiring 105 may be formed of a copper foil layer made of lead, copper, or gold.

In addition, the ground wiring 105 is partially exposed from the lower rear surface of the mold frame 110, and the exposed portion of the ground wiring 105 is soldered to the PCB 120 outside the timing controller 100. connected via a solder 106. In this case, soldering is performed on a portion of the PCB 120 corresponding to a portion exposed through the mold frame 110 of the ground wiring 105, and the timing controller 100 is mounted on the PCB 120. In the connecting process, heat treatment is performed so that the exposed portion of the ground wiring 105 and the solder 106 on the PCB 120 are partially melted and connected to each other. In this case, the exposed portions of the ground wiring 105 are melted and connected to each other by heat treatment of the solder 106 on the PCB 120, and then hardened in a state of being connected at room temperature.

Here, a portion of the ground wiring 105 partially exposed to the outside of the mold frame 110 may be larger than the ground wiring 105 in a shape similar to that of the terminal in some cases, as shown in FIG. 4. It can be formed in size (relatively large area). In this case, the exposed portion of the ground wiring 105

In addition, the plurality of wires 113 connected to the semiconductor chip 115 except for the ground wires are connected to an external pin 107. In this case, the external pins 107 may be made of the same material as the plurality of wires 113 or a material externally coated to correspond to the plurality of wires 113 in the mold frame 110, respectively. It is formed to be thicker than the plurality of wirings 113 inside. In addition, in the process of connecting the timing controller 100 on the PCB 120, the external pins 107 connect the solder 106 to the exposed portions of the ground wiring 105 as shown in FIG. 4. In addition, by forming a solder (not shown) corresponding to the external pin 107, the PCB 120 and the timing controller 100 are easily connected.

In this case, the terminal corresponding to the ground wiring 105 is not formed outside the mold frame 110 in the shape of a pin, but is partially exposed to the lower portion of the mold frame 110, and has the same size as compared with the related art. For the mold frame 110, the spacing of the plurality of pins 107 may be increased due to the decrease in the number of pins corresponding to the ground wiring 105, or the plurality of pins 107 may be larger than in the related art. If formed with the same line width, it is possible to reduce the area of the mold frame 110, it is possible to reduce the overall size of the timing controller (100).

Here, the mold frame 107 is made of an insulating plastic material, the semiconductor chip 115, a plurality of ground wiring 105, a plurality of wiring 113 except for the ground wiring 105 and An insulating layer (not shown) to which these are mounted is mounted to form a rectangular parallelepiped case.

The timing controller of the present invention as described above has the following effects.

First, as the ground pin is embedded in the mold frame, the total number of pins is reduced, which increases the margin of the pin spacing, thereby reducing the size of the timing controller.

Second, the copper foil layer connected to the ground related wiring may be exposed on the lower surface of the mold frame to facilitate connection between the timing controller and the PCB by solder. That is, the ground-related wiring is partially exposed on the lower surface of the mold frame, and the input / output-related wiring except the ground protrudes out of the mold frame, thereby increasing the contact area with the PCB connected thereto. PCB connections with all wiring can be stabilized without affecting adjacent pins.

Claims (3)

In the timing controller connected to the PCB, A semiconductor chip generating a ground signal and an input / output signal; A ground wire connected to the semiconductor chip to transfer a ground signal; Input and output wiring connected to the semiconductor chip except for the ground wiring to transmit an input / output signal; A mold frame exposing a predetermined portion of the ground wiring on its rear surface and having the semiconductor chip, ground wiring and input / output wiring embedded therein; A solder provided on the PCB corresponding to the exposed portion of the ground wiring; And And a plurality of pins connected to the input / output wires and formed outside the mold frame. The method of claim 1, And the mold frame has a predetermined hole in a portion where the ground wiring is exposed to the outside of the mold frame, and has a predetermined terminal shape of the ground wiring. The method of claim 1, And the exposed portions of the solder and the ground wiring are hardened by being connected to each other by heat treatment.

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