KR20060106322A - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device which prevents block dim at a boundary between gate drive ICs by modifying a signal line structure between gate drive ICs in a LOG type driver configuration. And a rectangular liquid crystal panel having a data pad part, a plurality of gate pad wires formed on the gate pad part, a plurality of data pad wires formed on the data pad part, and one side of which is connected to the gate pad wires. A data PCB including first to mth gate drivers, first to nth data drivers on one side of which are connected to the data pad wires, another side of the data drivers, and a gate high voltage generator; The first data driver is connected to the gate high voltage generator of the PCB. And a wiring resistance connected to the gate high voltage applying line and the gate high voltage applying line to apply a gate high voltage signal to the first to m-th gate drivers, respectively, and a wiring resistance sensed on each gate driver. And the same first to m-th log lines.

Gate Drive IC, Data Printed Circuit Board (PCB), Line On Glass (LOG), VGH Signal, LOG Wiring Resistance

Description

Liquid crystal display device

1 is a plan view showing a conventional liquid crystal display and a driving unit arrangement thereof

2 is a plan view showing the arrangement of the driving unit of the LOG A system

3 is a plan view showing the arrangement of the drive unit of the LOG B method

Figure 4 is a plan view showing a gate high voltage signal application of the LOG B method

FIG. 5 is a graph illustrating output waveforms corresponding to first and last stages of each gate drive IC of FIG.

FIG. 6 is a plan view illustrating a liquid crystal display of the present invention and a driving unit thereof;

7 is a plan view illustrating a gate high voltage signal application of FIG. 6;

8 is a plan view illustrating in detail a LOG wiring connection between a data driver and each gate driver according to another exemplary embodiment of the liquid crystal display of the present invention.

* Description of symbols on the main parts of the drawings *

100: first substrate 110a, 110b, 110c: gate drive IC

115a, 115b, 115c, 115d, 115e, 115f: TCP wiring

116a, 116b, 116c: first LOG wiring

117a, 117b: 2nd LOG wiring 118: 3rd LOG wiring

120a, 120b, 120c, 120d, 120e: data drive ic

135: fourth LOG wiring 136: gate high voltage application line

140: second substrate 150: data pad wiring

151, 152, 153: gate pad wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device that prevents block dim at a boundary between gate drive ICs by modifying a signal line structure between gate drive ICs in a LOG (Line On Glass) driving unit configuration. It is about.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as the substitute for CRT (Cathode Ray Tube) for mobile image display device because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention has been developed in various ways such as a television and a computer monitor for receiving and displaying broadcast signals.

In order to use such a liquid crystal display as a general screen display device in various parts, it is a matter of how high quality images such as high definition, high brightness and large area can be realized while maintaining the characteristics of light weight, thinness and low power consumption. can do.

A general liquid crystal display device may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel includes first and second glass substrates bonded to each other with a predetermined space; It consists of a liquid crystal layer injected between the said 1st, 2nd glass substrate.

The first glass substrate (TFT array substrate) may include a plurality of gate wires arranged in one direction at a predetermined interval, a plurality of data wires arranged at regular intervals in a direction perpendicular to the respective gate wires, A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing gate lines and data lines, and a plurality of thin film transistors switched by signals of the gate lines to transfer signals of the data lines to each pixel electrode. Is formed.

The second glass substrate (color filter substrate) includes a light shielding layer for blocking light in portions other than the pixel region, an R, G, and B color filter layers for expressing color colors, and a common electrode for implementing an image. Is formed.

The driving principle of the general liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the arrangement of molecules can be controlled by artificially applying an electric field to the liquid crystal.

Such a liquid crystal display includes a process of manufacturing a lower array substrate on which thin film transistors and pixel electrodes are arranged, a process of manufacturing an upper color filter substrate including a color filter and a common electrode, an arrangement of the two substrates manufactured, and a liquid crystal material It is formed by a liquid crystal cell process consisting of injection, encapsulation, and polarizer attachment.

Hereinafter, a driving unit of a conventional liquid crystal display device will be described with reference to the drawings.

1 is a plan view illustrating a conventional liquid crystal display and a driving unit arrangement thereof.

As shown in FIG. 1, a conventional liquid crystal display device includes a first substrate 20 on which a thin film transistor array is largely formed, a second substrate 10 on which a color filter array is formed, and a first substrate 20 and a second substrate. It includes a liquid crystal panel consisting of a liquid crystal layer (not shown) filled between the substrate 10, the driving unit is disposed in the pad portion of the liquid crystal panel. The driver includes gate drivers 21a, 21b, and 21c for driving gate lines (not shown, formed in the horizontal direction on the first substrate 20), and data lines (not shown, on the first substrate 20). The data drivers 23a, 23b, 23c, 23d, 23e, the gate drivers 21a, 21b, 21c, and the data drivers 23a, 23b, 23c, 23d, 23e for driving them in a direction perpendicular to the A timing controller (not shown) for controlling and a power supply unit (not shown) for supplying various driving voltages used in the liquid crystal display device are provided. The timing controller (not shown) controls driving timings of the gate drivers 21a, 21b, 21c and the data drivers 23a, 23b, 23c, 23d, and 23e, and the data drivers 23a, 23b, 23c, and 23d. , 23e) is supplied with the pixel data signal. The power supply unit generates driving voltages such as a common voltage VCOM, a gate high voltage VGH, and a gate low voltage VGL required by the liquid crystal display using the input power. The gate drivers 21a, 21b, and 21c sequentially supply scanning signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data drivers 23a, 23b, 23c, 23d, and 23e supply a pixel voltage signal to each of the data lines whenever a scanning signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Among them, the data drivers 23a, 23b, 23c, 23d and 23e and the gate drivers 21a, 21b and 21c which are directly connected to the liquid crystal panel are integrated into a plurality of integrated circuits (ICs). Each of the integrated data drive IC and the gate drive IC is mounted on a tape carrier package (TCP) and connected to a liquid crystal panel by a tape automated bonding (TAB) method.

Here, each gate driver 21a, 21b, 21c and data drivers 23a, 23b, 23c, 23d, and 23e having one side connected to the liquid crystal panel through the TAB method through the lower film surface TCP have a drive IC therein. Is connected to the gate PCB 22 and the data PCB 24 on the other side of the TCP. Each of the drive ICs is connected to and received from control signals and DC voltages input from the outside through signal lines mounted on each printed circuit board (PCB) 22 and 24 connected to TCP. Specifically, data drive ICs inside the data drivers 23a, 23b, 23c, 23d, and 23e are connected through signal lines mounted on the data PCB 24, and control signals and pixels from the timing controller. The driving voltages are commonly supplied from the data signal and the power supply. Gate drive ICs in the gate drivers 21a, 21b, and 21c are connected in series through signal lines mounted on the gate PCB 22, and control signals from the timing controller and drive voltages from the power supply unit are common. Will be supplied.

In addition, the gate PCB 22 and the data PCB 24 are connected through an external signal line 30 to apply the corresponding signals to the corresponding driver in synchronization with each other.

On the other hand, in recent years, efforts have been made to simplify the configuration of the driving unit. As one method, an external signal line or a signal line for transmitting signals between the drive ICs without omitting the gate PCB side is transferred to a liquid crystal panel, that is, a lower portion. There is a line on glass (LOG) method that is mounted on the glass.

The LOG method includes a LOG A method in which an external signal line between the gate PCB and the data PCB enters the liquid crystal panel, and a LOG B method in which a signal line between the gate drivers is provided on the liquid crystal panel so as to omit the gate PCB and connect the gate drivers. .

Hereinafter, the LOG method will be described with reference to the drawings.

2 is a plan view showing the arrangement of the driving unit of the LOG A system.

As shown in FIG. 2, the LOG A type liquid crystal display includes a first substrate 50 in which a thin film transistor array is largely formed, a second substrate 40 in which a color filter array is formed to face the first substrate 50, and the first substrate 50. And a liquid crystal panel made up of a liquid crystal layer (not shown) filled between the second substrate 40 and the driving unit. The driver includes gate drivers 51a, 51b, and 51c for driving gate lines (not shown, formed in the horizontal direction on the first substrate 50) and data lines (not shown, on the first substrate 50). Data drivers 53a, 53b, 53c, 53d, 53e, gate drivers 51a, 51b, 51c, and data drivers 53a, 53b, 53c A timing controller (not shown) for controlling the 53d and 53e and a power supply unit (not shown) for supplying various driving voltages used in the liquid crystal display device are provided. In addition, the gate PCB 52 is controlled by receiving a signal through the data PCB 54, at which time, the application of the control signal and the uppermost gate driver 51a on the first substrate (50) The signal line 60 is connected between the leftmost data driver 53a. Signals applied to the signal line 60 include gate control signals GSC, GSP, and GOE, and Vcc, GND, VGH, and VGL.

In this LOG A method, a timing controller is included on the data PCB 54 to further include a power supply unit for supplying driving voltages such as various gate high voltages VGH.

Although only a single signal line 60 is shown in FIG. 2, the uppermost gate driver 51a and the leftmost data driver 53a are equal to the number of signals transmitted from the data PCB 54 to the gate PCB 52. The signal line 60 may be formed in between.

3 is a plan view showing the arrangement of the driving unit of the LOG B system.

As shown in FIG. 3, the liquid crystal display of the LOG system includes a first substrate 80 having a thin film transistor array, a second substrate 70 and a first substrate 80 having a color filter array opposed thereto. It includes a liquid crystal panel consisting of a liquid crystal layer (not shown) filled between the second substrate 70, the driving unit is disposed in the pad portion of the liquid crystal panel. The driver includes gate drivers 81a, 81b, and 81c for driving gate lines (not shown, formed in the horizontal direction on the first substrate 80), and data lines (not shown, on the first substrate 80). Data drivers 83a, 83b, 83c, 83d, 83e, gate drivers 81a, 81b, 81c, and data drivers 83a, 83b, 83c, A timing controller (not shown) for controlling the 83d and 83e and a power supply unit (not shown) for supplying various driving voltages used in the liquid crystal display device are provided.

In the LOG B scheme, the gate PCB is omitted, and the gate drivers 81a, 81b, and 81c are controlled by receiving a signal through the data PCB 84. In this case, the control signal is applied by connecting the first signal line 85 between the uppermost gate driver 81a and the leftmost data driver 83a on the first substrate 80. Also, the second signal line and the third signal line 86a and 86b are connected between the gate drivers 81a, 81b, and 81c by the absence of a gate PCB, so that the control signals generated in the data PCB 84 are each gate driver. To be delivered to the (81a, 81b, 81c) side.

In the LOG B method, a timing controller is included on the data PCB 83 to further include a power supply unit for supplying driving voltages such as various gate high voltages VGH.

4 is a plan view illustrating gate high voltage signal application using a LOG B method.

As shown in FIG. 4, the application of the gate high voltage signal VGH of the LOG B method is performed by including the VGH power generator 90 in the data PCB 83. In order to transfer the gate high voltage signal output from the VGH power generation unit 90, a gate high voltage signal connected to the VGH power generation unit 90 is applied to a TCP rear surface of the leftmost data driver 82a. A wiring 84 is provided, and a first LOG wiring 85 is provided on the first substrate 80 between the leftmost first data driver 82a and the uppermost first gate driver 81a. The second LOG wiring 86a and the third LOG wiring 86b are provided on the first substrate 80 between the adjacent gate drivers 81a, 81b, and 81c.

Each of the gate drivers 81a, 81b, 81c and the data drivers 82a, ... includes a tape carrier package (TCP) and drive ICs 93a, 93b, 93c, 92a formed on the TCP. Is done. Here, a first pattern 93a is formed on the rear surface of the first gate driver 81a between the first LOG wiring 85 and the second LOG wiring 86a via the first drive IC 91a. A second pattern 93b is formed on the rear surface of the second gate driver 81b between the second LOG wiring 86a and the third LOG wiring 86b via the second drive IC 91b. A third pattern 93c is formed in the third gate drive 81c via the third gate IC 91c to connect each other. In this case, the gate high voltage application wiring 84 formed in the first data driver 82a is connected to the corresponding data pad wiring (not shown) of the first substrate 80 to be connected on the first substrate 80. do.

In the conventional LOG application structure (LOG A type, LOG B type), the gate high voltage signal VGH generated by the VGH power generation unit 90 of the data PCB 83 has the gate drivers 81a, 81b, 81c. ) Is supplied in series.

Due to the relatively high line resistance of the LOG B type, a different delay may be present in the gate high voltage signal VGH supplied to the gate drivers 81a, 81b, and 81c. That is, when the resistances applied to the first to third LOG lines 85, 86a, and 86b are aΩ, bΩ, and cΩ, respectively, the resistance applied to the gate high voltage signal VGH of the first gate driver 81a is aΩ. The resistance of the gate high voltage signal VGH of the second gate driver 81b is (a + b) Ω, and the resistance of the gate high voltage signal VGH of the third gate driver 81c is (a). + b + c) Ω. This is because the wiring resistance on the TCP of each gate driver 81a, 81b, 81b on which the gate drive ICs 93a, 93b, 93c are formed is close to 0?, And the resistance on the wiring formed on the liquid crystal panel is generated mainly. This resistance value is calculated.

As described above, when the gate high voltage signals VGH applied to the gate drivers 81a, 81b, and 81c are different, delays between the gate high voltage signals VGH input to the gate drivers 81a, 81b and 81c occur. do. Due to the input of the delayed gate high voltage signal, there is a delay in the gate high voltage signal VGH supplied from each gate driver 81a, 81b, 81c to the gate lines on the first substrate 80, in particular at the boundary between the gate drivers. To cause a screen quality defect that looks like a block dim on the screen. Or, it is not a block, but may appear as a defect in which a line exists only at a boundary.

FIG. 5 is a graph illustrating output waveforms corresponding to first and last stages of each gate driver of FIG. 4.

As can be seen in FIG. 5, the difference between the first output value of the second gate driver and the first output value of the third gate driver is large. You can see the difference. Here, it is observed that the difference between the first output value of the second gate driver and the last output value of the second gate driver shows a difference in output between adjacent gate driver boundaries, which corresponds to the second gate driver corresponding to the gate lines. The difference between the first and last of hundreds of output stages in the second gate driver is one hundredth of the resistance between adjacent output terminals in the second gate driver. Thus, the problem is the difference in resistance between the last end of the previous gate driver and the first end of the next gate driver among the adjacent gate drivers.

The luminance difference occurs due to the output delay between each gate driver, in particular, the difference in the on current at the boundary between the gate drivers. Occurs.

The conventional liquid crystal display as described above has the following problems.

The gate PCB is omitted, and a line on glass (LOG) method is used to form a wiring for applying a driving signal on the liquid crystal panel. In this case, the LOG wiring is formed on the liquid crystal panel for electrical connection between adjacent drivers. Therefore, there is a problem that the resistance increases.

In particular, since the gate high voltage signal supplied from the data PCB is supplied to each of the gate drivers in series, the resistance of the gate high voltage signal that is gradually detected as the gate driver located below is larger, and thus the delay application of the signal is increased. Occurs. Therefore, the lower the gate driver located below, the lower the on current of the output gate signal is generated, and the difference between the output delay between each gate driver and the on current at the boundary between the gate drivers is reduced. As a result, a luminance difference between blocks corresponding to the gate driver is generated, and for this reason, a screen defect in the form of a block or a line occurs at the gate driver interval on the screen.

The present invention has been made to solve the above problems, and provides a liquid crystal display device which prevents block dim at the boundary between gate drive ICs by modifying the signal line structure between gate drive ICs in a LOG type driver configuration. There is a purpose.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a rectangular liquid crystal panel having a gate pad portion and a data pad portion at two adjacent sides, a plurality of gate pad wirings formed on the gate pad portion, A plurality of data pad wires formed on the data pad part, first to m gate drivers connected at one side to the gate pad wires, and first to nth data drivers connected at one side to the data pad wires; A data PCB connected to the other side of the data drivers, the data PCB including a gate high voltage generator, a gate high voltage application line connected to a gate high voltage generator of the data PCB, and formed in the first data driver; Connected to a high voltage applying line to each of the first to mth gate drivers It is formed on the liquid crystal panel to apply each gate high voltage signal, and the wiring resistance sensed on each gate driver includes the same first to m-th LOG wiring.

The gate high voltage application line is formed on the rear surface of the first data driver.

The thickness becomes thinner gradually from the first LOG wiring to the m LOG wiring.

The length becomes gradually shorter from the first LOG wiring to the mth LOG wiring.

The gate drivers and the data drivers each have a TCP film surface, and a plurality of signal lines formed on the TCP film surface corresponding to the plurality of input / output signals from the drive IC and the drive IC in the center thereof.

In addition to the gate high voltage signal, a plurality of control signals and driving signals are applied from the data PCB to the first to m th gate drivers via the first data driver.

Signal lines for transmitting the plurality of control signals and driving signals to each gate driver are formed on the liquid crystal panel.

Hereinafter, the liquid crystal display of the present invention will be described in detail with reference to the accompanying drawings.

6 is a plan view illustrating a liquid crystal display of the present invention and a driving unit arrangement thereof.

As shown in FIG. 6, the liquid crystal display of the present invention includes a first substrate 100 on which a thin film transistor array is largely formed, a second substrate 140 on which a color filter array is formed, and a first substrate 100 and a first substrate 100. The liquid crystal panel includes a liquid crystal layer (not shown) filled between the two substrates 140, and a driving unit is disposed in a pad unit, which is an edge of the liquid crystal panel. The driver includes gate drivers 110a, 110b, and 110c for driving gate lines (not shown, formed in the horizontal direction on the first substrate 100), and data lines (not shown, on the first substrate 100). Data drivers 120a, 120b, 120c, 120d, and 120e for driving the plurality of data drivers 130a, 120b, 120c, 120d, and 120e, and data PCBs 130 connected to the data drivers 120a, 120b, 120c, 120d, and 120e. Is done.

In the data PCB 130, a timing controller (not shown) for controlling the gate drivers 110a, 110b and 110c, the data drivers 120a, 120b, 120c, 120d and 120e, and a liquid crystal display device. A power supply (not shown) for supplying various driving voltages used is provided. The data PCB 130 is formed by being connected to the data drivers 120a, 120b, 120c, 120d and 120e, and the gate drivers 110a, 110b and 110c provided in the first data driver 120a. The signal is transmitted and received through the fourth LOG wiring 135 formed on the first substrate 100 via a wiring (not shown).

In this case, the timing controller (not shown) in the data PCB 130 controls driving timings of the gate drivers 110a, 110b, and 110c and the data drivers 120a, 120b, 120c, 120d, and 120e. The pixel data signal is supplied to the data drivers 120a, 120b, 120c, 120d, and 120e. In addition, the power supply unit (not shown) generates driving voltages such as the common voltage VCOM, the gate high voltage VGH, and the gate low voltage VGL required by the liquid crystal display using the input power. The gate drivers 110a, 110b, and 110c sequentially supply scanning signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data drivers 120a, 120b, 120c, 120d, and 120e supply a pixel voltage signal to each of the data lines whenever a scanning signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Among them, the data drivers 120a, 120b, 120c, 120d and 120e and the gate drivers 110a, 110b and 110c, which are directly connected to the liquid crystal panel, are integrated into a plurality of integrated circuits (ICs). Each of the integrated data drive IC and the gate drive IC is mounted on a tape carrier package (TCP) and connected to a liquid crystal panel by a tape automated bonding (TAB) method.

Here, each of the data drivers 120a, 120b, 120c, 120d, and 120e, in which one side is connected to the liquid crystal panel through a TAB method through the lower film surface, has a drive IC therein, and the data PCB 130 on the other side of the TCP. ). Each of the drive ICs is connected to and receives control signals and DC voltages input from the outside through signal lines (not shown) mounted on the data printed circuit board (130) connected to TCP.

7 is a plan view illustrating signal line connections between the gate drive ICs of FIG. 6.

6 and 7, the VGH power generation of the data PCB 130 is generated between the first data driver (the data driver 120a located at the leftmost of the data drivers) and the gate drivers 110a, 110b, and 110c. In order to apply the gate high voltage signal VGH generated by the unit 131, the third LOG wiring 118, the second LOG wiring 117, and the first LOG wiring 116 are sequentially formed. In this case, the wiring resistances of the corresponding LOG lines detected by the gate drivers 110a, 110b, and 110c are the same. That is, when the resistance of the third LOG wiring 118 is a ', the resistance of the second LOG wiring 117 is b', and c 'of the resistance of the third LOG wiring 116, a' = b Each wiring is configured with '= c'. In this case, the gate driver located at the lower side has a longer path from the first data driver 120a. Therefore, in order to match the same resistance level between the LOG lines, the LOG wiring corresponding to the gate driver located at the lower side becomes thicker. The thinner the LOG wiring corresponding to the gate driver located above the gate driver, the thinner the wiring. Alternatively, the gate driver located at an upper side has a length longer than the physical distance difference of each gate driver of the first data driver 120a in the first data driver 120a. 7), the same effect can be obtained.

That is, in the liquid crystal display device of the present invention, the configuration of the driving circuit is omitted, like the LOG B method, and the liquid crystal panel (first substrate) between the first data driver 120a and the first gate driver 110a is omitted. By forming the fourth LOG wiring 135 in the drive signal and the control signal generated in the data PCB 130 to be transmitted to each gate driver. In addition, the gate high voltage signal applied to each gate driver is not sequentially applied to each gate driver, and each gate driver is simultaneously applied through a corresponding line (LOG wiring and TCP wiring of each gate driver) in parallel. By keeping the resistance of the LOG wiring applied to the same, the deviation of the gate high voltage signal (VGH) detected by each gate driver hardly occurs.

The first data driver 120a includes a gate high voltage signal generated on the back of the TCP film formed on the rear side of the drive IC 121a in which the gate high voltage signal generated from the VGH power generation unit 131 of the data PCB 130 is located. It is transferred to the gate drivers 110a, 110b, and 110c through the application line 136. In this case, the wiring between the first data driver 120a and the gate drivers 110a, 110b, and 110c may have resistances of TCP wirings of the gate driver in addition to the actual LOG wiring. However, since the resistance of the LOG wiring formed on the first substrate 100, which is relatively vulnerable to static electricity, is large, the TCP wirings 115a, 115b, and 115c formed in the corresponding gate drivers 110a, 110b, and 110c. , 115d, 115e, and 115f) have a resistance near zero. Therefore, the resistance value between the first data driver 120a and the gate drivers 110a, 110b, and 110c depends on the resistance values of the LOG lines.

The gate high voltage signal application lines 136 included in the first data driver 120a are provided in the number corresponding to each of the gate drivers 110a, 110b, and 110c so as to correspond to each gate driver one by one. Therefore, the gate high voltage signal application path applied from the first data driver 120a to the first gate driver 110a becomes the third LOG wiring 118 and the third TCP wiring 115c and the first data. The gate high voltage signal application path applied from the driver 120a to the second gate driver 110b includes the second LOG wiring first pattern 117a, the second TCP wiring 115b, and the second LOG wiring second pattern 117b. ) And the fifth TCP wiring 115e, and the gate high voltage signal applying path applied to the third gate driver 110c includes the first LOG wiring first pattern 116a, the first TCP wiring 115a, and the first TCP wiring 115e. It becomes the LOG wiring 2nd pattern 116b, the 4th TCP wiring 115d, the 1st LOG wiring 3rd pattern 116c, and the 6th TCP wiring 115f. At this time, the wiring resistance of the TCP lines 115a to 115f is negligible. Therefore, in this case, the wiring resistance applied to the gate high voltage applied to each gate driver will correspond to the sum of the pattern resistances of the corresponding LOG wiring.

In this case, if the gate driver located at the lower side of the structure as shown in FIG. 7 shows that the sum of the patterns of the LOG wirings is longer than that of the upper gate driver, the patterns of the corresponding LOG wirings corresponding to the gate drivers have a sum of lengths. By making the same for each LOG wiring, the wiring resistance applied to the gate high voltage between each gate driver can be set to the same level. That is, when the third LOG wiring 118 corresponding to the first gate driver 110a looks relatively shorter than the first LOG wiring 116: 116a + 116b + 116c, the third LOG wiring 118 ) May be increased in a zigzag shape to be equal to the length of the first LOG wire 116. In addition, the second LOG wiring 117 may be matched with the length of the first LOG wiring 116 by reducing the zigzag width rather than the third LOG wiring 118. At this time, it is assumed that the thickness of each LOG wiring is the same.

8 is a plan view illustrating in detail a LOG wiring connection between a data driver and each gate driver according to another exemplary embodiment of the liquid crystal display of the present invention.

As shown in FIG. 8, the liquid crystal display according to another exemplary embodiment of the present invention connects a first data driver (not shown) and each gate driver, so that the gate driver located at a lower side having a longer path has a corresponding LOG line. The thicker the gate driver, the thinner the corresponding LOG wiring. That is, as shown in FIG. 8, the first LOG wirings 116a, 116b, and 116c corresponding to the third gate driver 110c are formed to be thickest and correspond to the second gate driver 110b. The second LOG wires 117a and 117b are formed to have a smaller thickness, and the third LOG wire 118 corresponding to the first gate driver 110a is formed to be the thinnest. As in the above-described embodiment, the structure is designed to have the same resistance level for each LOG wiring.

At this time, the first LOG wiring first pattern 116a, the second LOG wiring first pattern 117a, and the third LOG wiring 118 are located at positions corresponding to the first data driver (not shown). The data pad wiring 150 is connected between the gate pad wiring 151 corresponding to the first gate driver 110a. In addition, the first LOG wiring second pattern 116b and the second LOG wiring first pattern 117b may include a gate pad wiring 151 and a second gate at positions corresponding to the first gate driver 110. It is connected to the gate pad wiring 152 corresponding to the driver 110b. In addition, the first LOG wiring third pattern 116c is formed adjacent to the corresponding gate pad wirings 152 and 153 of the second gate driver 110b and the third gate driver 110c.

As described above, the liquid crystal display device of the present invention adopts the LOG B method, and forms and supplies the LOG high voltage signal VGH supplied from the data PCB by forming the LOG wiring for each gate driver in the liquid crystal panel. The resistance between the wires can be maintained at the same level to minimize the variation of the gate high voltage supplied between adjacent gate drivers. Therefore, the block dim phenomenon caused by the difference in the gate high voltage between the gate drivers can be prevented and the luminance difference can be improved.

The liquid crystal display of the present invention as described above has the following effects.

It adopts the LOG B method and supplies the gate high voltage signal (VGH) supplied from the data PCB by forming the LOG wiring for each gate driver in the liquid crystal panel. The variation of the gate high voltage supplied between the gate drivers can be minimized.

Accordingly, it is expected to be effective in improving the weak block dim at normal temperature but operating at environmental conditions, high temperature (60 ℃) and high temperature and high humidity (60 ℃ / 50%).

Claims (7)

A rectangular liquid crystal panel having a gate pad portion and a data pad portion at two adjacent sides; A plurality of gate pad wires formed on the gate pad part; A plurality of data pad wires formed on the data pad portion; First to m-th gate drivers having one side connected to the gate pad wires; First to nth data drivers having one side connected to the data pad wires; A data PCB connected to the other side of the data drivers and having a gate high voltage generator; A gate high voltage applying line connected to the gate high voltage generator of the data PCB and formed in the first data driver; A first to m LOG connected to the gate high voltage applying line and formed on the liquid crystal panel to apply a gate high voltage signal to the first to m th gate drivers, respectively, and having the same wiring resistance sensed on each of the gate drivers. Liquid crystal display comprising a wiring. The method of claim 1, And the gate high voltage applying line is formed on a rear surface of the first data driver. The method of claim 1, And the thickness becomes thinner gradually from the first LOG wiring to the m-th LOG wiring. The method of claim 1, And the length is gradually shortened from the first LOG wiring to the m-th LOG wiring. The method of claim 1, The gate drivers and the data drivers each have a TCP film surface and a plurality of signal lines formed on the TCP film surface corresponding to a plurality of input / output signals from the drive IC and the drive IC in the center thereof. Device. The method of claim 1, And a plurality of control signals and driving signals in addition to the gate high voltage signal are applied from the data PCB to the first to mth gate drivers through the first data driver. The method of claim 6, And a signal line for transmitting the plurality of control signals and driving signals to each gate driver is formed on a liquid crystal panel.

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