KR20060102919A - Page buffer circuit of flash memory device for reducing program time - Google Patents

Abstract

The present invention relates to a page buffer circuit of a flash memory device for reducing a program time, wherein the page buffer circuit according to the present invention is characterized in that it is determined by first read data from memory cells connected to a first bit line during a read operation. A first page buffer configured to store first sensing data corresponding to a voltage of a first sensing node and to store first program data to be programmed in memory cells connected to the first bit line during a program operation; And second sensing data corresponding to a voltage of a second sensing node determined by second read data from memory cells connected to a second bit line in a read operation, and memory cells connected to the second bit line in a program operation. And a second page buffer for storing second program data to be programmed in. Preferably, the first page buffer and the second page buffer share a Y-gate circuit. In the present invention, by providing independently controllable bit line bias voltages for the bit lines, the total program time can be reduced by reducing the time required for the bit line precharge process.

Bit Line Bias Voltage, Sensing Node, and Resistor Circuit

Description

Page buffer circuit of flash memory device for reducing program time

1 is a diagram illustrating a page buffer circuit of a conventional flash memory device.

FIG. 2 is a timing diagram of signals related to the operation of the page buffer circuit shown in FIG. 1.

3 is a diagram illustrating a page buffer circuit of a flash memory device according to an exemplary embodiment of the present invention.

FIG. 4 is a timing diagram of signals related to the operation of the page buffer circuit shown in FIG. 3.

<Explanation of symbols for main parts of drawing>

100: page buffer circuit 110: first page buffer

120: second page buffer 111, 121: bit line selection circuit

112, 122: register circuit 113, 123: data input circuit

114, 124: sensing circuit 115, 125: latch circuit

The present invention relates to a flash memory device, and more particularly, to a page buffer circuit of a flash memory device.

Generally, flash memory devices include a page buffer to program or read large amounts of data for a short time. Therefore, the program operation or the read operation of the flash memory device is executed by the page buffer in units of pages. 1 is a diagram illustrating a page buffer circuit of a conventional flash memory device. The page buffer circuit 10 includes a bit line selector 11, a precharge circuit P1, a main register circuit 12, a cache register circuit 13, and NMOS transistors N11 to N15. The bit line selector 11 includes NMOS transistors N1 to N4. The main register circuit 12 includes a sensing circuit 14 and a main latch circuit 15, and the cache register circuit 13 includes a cache latch circuit 16 and a sensing circuit 17.

Referring to FIG. 2, the program operation of the page buffer circuit 10 will be briefly described as follows. First, the cache register circuit 13 stores program data Q1b or Q1, and when the NMOS transistor N13 is turned on, the program data Q1b or Q1 stored in the cache register circuit 13 is sensed. Output to node SO. The main register circuit 13 stores sensing data Q2b corresponding to the program data Q1b or Q1 received through the sensing node SO.

Meanwhile, in order to program the sensing data Q2b stored in the main register circuit 13 to a memory cell connected to the bit line BLe or BLo, a bit line for changing the bit line BLe or BLo to a set voltage. The setup process is executed. In the bit line setup process, first, as referenced in FIG. 2, the bit line bias voltage VIRPWR is brought to the voltage VCC level. In addition, the voltages VCC + Vt and Vt at which the control signals DISCHe and DISCHo are set at the same time become the threshold voltages of the NMOS transistors N1 and N2. At this time, the control signal DISCHe is disabled to a low level after the set time T1, and the control signal DISCHo is continuously maintained at the voltage VCC + Vt level. As a result, the NMOS transistors N1 and N2 are simultaneously turned on to supply the bit line bias voltage VIRPWR to each of the bit lines BLe and BLo. After the set time T1, the NMOS transistor N1 is turned off to stop the supply of the bit line bias voltage VIRPWR to the bit line BLe. The NMOS transistor N2 continuously supplies the bit line bias voltage VIRPWR to the bit line BLo. Here, the set time T1 is a bit line precharge time.

After the set time T1, the program control signal PGM and the bit line select signal BSLe are changed to the voltage VCC level, and the bit line select signal BSLo is kept low. In response to the program control signal PGM, the NMOS transistor N14 is turned on to connect the output of the main register circuit 12 to the sensing node SO. As a result, the data Q2 stored in the main register circuit 12 is transferred to the sensing node SO. In addition, in response to the bit line selection signal BSLe, the NMOS transistor N3 is turned on to connect the bit line BLe to the sensing node SO. The NMOS transistor N4 separates the bit line BLo from the sensing node SO in response to the bit line select signal BSLo. As a result, the data Q2 transferred to the sensing node SO is input to the bit line BLe.

For example, when the logic value of the data Q2 is '0', the voltage of the bit line BLe is gradually decreased from the voltage VCC to 0V. At this time, in order to prevent the memory cells connected to the bit line BLo from being programmed, the voltage of the bit line BLo must be maintained at the voltage VCC level. However, due to the coupling capacitance component between the bit lines BLe and BLo, the voltage of the bit line BLo is temporarily changed as shown by F in FIG. 2. At this time, since the bit line bias voltage VIRPWR of the voltage VCC level is continuously supplied to the bit line BLo by the NMOS transistor N2, the bit line BLo is set at a set time ( Is restored to the voltage VCC level during T2). Here, the set time T2 is a bit line voltage restore time. As a result, for the bit line setup process, time T3 (ie, bit line setup time), which is the sum of the bit line precharge time T1 and the bit line voltage recovery time T2, is required.

On the other hand, the bit line setup time is an important factor in determining the program time of the flash memory device. Therefore, if the bit line setup time is increased, the total program time of the flash memory device is also increased. This problem may become more serious as the flash memory device is highly integrated. This is because the higher the integration of the flash memory device, the more the coupling capacitance component between the bit lines increases, thereby increasing the bit line setup time. Therefore, in order to shorten the program time of the flash memory device, the bit line setup time needs to be reduced.

Accordingly, a technical problem of the present invention is to provide bit line bias voltages that are independently controllable for bit lines, thereby reducing the time required for the bit line precharge process, thereby reducing the overall program time. It is to provide a page buffer circuit of the device.

A page buffer circuit of a flash memory device according to the present invention for achieving the above technical problem corresponds to a voltage of a first sensing node determined by first read data from memory cells connected to a first bit line during a read operation. A first page buffer configured to store first sensing data, and to store first program data to be programmed in memory cells connected to the first bit line during a program operation; And second sensing data corresponding to a voltage of a second sensing node determined by second read data from memory cells connected to a second bit line in a read operation, and memory cells connected to the second bit line in a program operation. And a second page buffer for storing second program data to be programmed in. Preferably, the first page buffer and the second page buffer share a Y-gate circuit, and the Y-gate circuit stores the first page buffer or the second page buffer in response to an input / output control signal during a read operation or a program operation. It is connected to the input / output line.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

3 is a diagram illustrating a page buffer circuit of a flash memory device according to an exemplary embodiment of the present invention. Referring to FIG. 3, the page buffer circuit 100 includes a first page buffer 110 and a second page buffer 120. The first page buffer 110 may include a bit line selection circuit 111, a precharge circuit P11, a register circuit 112, a data input circuit 113, a first switch N13, and a second switch N16. ). The bit line selection circuit 111 includes NMOS transistors N11 and N12. The NMOS transistor N11 is turned on or off in response to the bit line control signal DISCHe, and when turned on, supplies the bit line bias voltage VIRPWRe to the bit line BLe. The NMOS transistor N12 connects the bit line BLe to the first sensing node SOe in response to a bit line select signal BSLe. The precharge circuit P11 precharges the first sensing node SOe to the voltage VCC level in response to the precharge control signal PRCHbe. The register circuit 112 includes a sensing circuit 114, a latch circuit 115, and a reset circuit N19. The sensing circuit 114 includes NMOS transistors N17 and N18. In the read operation, the sensing circuit 114 generates first sensing data SQ1b corresponding to the voltage level of the first sensing node SOe in response to the latch control signal LATCHe. The latch circuit 115 includes inverters IV1 and IV2 and latches the first sensing data SQ1b or latches the first program data PQ1b or PQ1. The reset circuit N19 initializes the latch circuit 115 in response to a reset control signal RSTe.

The data input circuit 113 includes NMOS transistors N14 and N15. The NMOS transistor N14 is turned on or off in response to an input control signal DIe, and when turned on, the first program data received from the data input / output line DIOL through the Y-gate circuit 200. PQ1b) is output to the latch circuit 115. The NMOS transistor N15 is turned on or off in response to an input control signal nDIe, and when turned on, the first program received from the data input / output line DIOL through the Y-gate circuit 200. Data PQ1 is output to the latch circuit 115. Preferably, when the data value to be programmed is '1', the NMOS transistor N14 is turned on and the NMOS transistor N15 is turned off. In addition, when the value of data to be programmed is '0', the NMOS transistor N15 is turned on and the NMOS transistor N14 is turned off. In addition, when one of the NMOS transistors N14 and N15 is turned on, the data input / output line DIOL becomes a ground voltage level.

The first switch N13 may receive the first program data PQ1b or PQ1 received from the latch circuit 115 of the register circuit 112 in response to a program control signal PGMe. The bit line BLe is output to the bit line BLe through SOe. In response to the read control signal PBDOe, the second switch N16 converts the inverted data SQ1 of the first sensing data SQ1b received from the latch circuit 115 to the Y-gate circuit 200. Outputs to the data input / output line DIOL.

The second page buffer 120 includes a bit line selection circuit 121, a precharge circuit P21, a register circuit 122, a data input circuit 123, a first switch N23, and a second switch N26. ). The bit line selection circuit 121 includes NMOS transistors N21 and N22. The NMOS transistor N21 is turned on or off in response to the bit line control signal DISCHo and, when turned on, supplies the bit line bias voltage VIRPWRo to the bit line BLo. The NMOS transistor N22 connects the bit line BLo to the second sensing node SOo in response to a bit line select signal BSLo. The precharge circuit P21 precharges the second sensing node SOo to the voltage VCC level in response to the precharge control signal PRCHbo. The register circuit 122 includes a sensing circuit 124, a latch circuit 125, and a reset circuit N29. The sensing circuit 124 includes NMOS transistors N27 and N28. During the read operation, the sensing circuit 124 generates second sensing data SQ2b corresponding to the voltage level of the second sensing node SOo in response to the latch control signal LATCHo. The latch circuit 125 includes inverters IV3 and IV4 and latches the second sensing data SQ2b or latches the second program data PQ2b or PQ2. The reset circuit N29 initializes the latch circuit 125 in response to a reset control signal RSTo.

The data input circuit 123 includes NMOS transistors N24 and N25. The NMOS transistor N24 is turned on or off in response to an input control signal DIo, and when turned on, the second program received from the data input / output line DIOL through the Y-gate circuit 200. Data PQ2b is output to the latch circuit 125. The NMOS transistor N25 is turned on or off in response to an input control signal nDIo, and when turned on, the second program received from the data input / output line DIOL through the Y-gate circuit 200. Data PQ2 is output to the latch circuit 125. Preferably, when the data value to be programmed is '1', the NMOS transistor N24 is turned on and the NMOS transistor N25 is turned off. In addition, when the value of data to be programmed is '0', the NMOS transistor N25 is turned on and the NMOS transistor N24 is turned off. In addition, when one of the NMOS transistors N24 and N25 is turned on, the data input / output line DIOL becomes the ground voltage level.

The first switch N23 may receive the second program data PQ2b or PQ2 received from the latch circuit 125 of the register circuit 122 in response to a program control signal PGMo. Output to the bit line BLo via SOo. In response to the read control signal PBDOo, the second switch N26 converts the inverted data SQ2 of the second sensing data SQ2b received from the latch circuit 125 to the Y-gate circuit 200. Outputs to the data input / output line DIOL.

Next, a program operation process by the page buffer circuit 100 will be described in detail with reference to FIG. 4. FIG. 4 is a timing diagram of signals related to the operation of the page buffer circuit shown in FIG. 3. When the memory cell connected to the bit line BLe is programmed and the memory cell connected to the bit line BLO is not programmed, an operation of the page buffer circuit 100 will be described by way of example. First, the first program data PQ1 having a value of '0' is latched in the latch circuit 115 of the register circuit 112. Here, the process of latching the first program data PQ1 to the latch circuit 115 can be understood by those skilled in the art, so a detailed description thereof will be omitted. Thereafter, the bit line bias voltage VIRPWRo is at the voltage VCC level, and the voltage VCC + Vt at which the bit line control signal DISCHo is set is set at the level of the threshold voltage of the NMOS transistor N22. do. As a result, the NMOS transistor N21 is turned on to supply the bit line bias voltage VIRPWRo having the voltage VCC level to the bit line BLo. The bit line bias voltage VIRPWRe and the bit line control signal DISCHe are maintained at a low level. As a result, the NMOS transistor N11 is turned off, and the bit line bias voltage VIRPWRe is not supplied to the bit line BLe. Here, since the bit line bias voltage VIRPWRo is supplied only to the bit line BLO, the influence of the bit line BLe (for example, the bit line according to the power consumption of the bit line BLe) Bias voltage VIRPWRo).

Thereafter, the bit line selection signal BSLe and the program control signal PGMe are enabled. As a result, the NMOS transistor N12 is turned on, the bit line BLe is connected to the first sensing node SOe, and the first switch N13 is turned on, so that the latch circuit 115 is turned on. And outputs the first program data PQ1 received from the first sensing node SOe. As a result, the first program data PQ1 is transferred to the bit line BLe. At this time, since the value of the first program data PQ1 is '0', the voltage level of the bit line BLe is gradually decreased. In addition, the bit line selection signal BSLo and the program control signal PGMo are maintained in a disabled state. As a result, the NMOS transistor N22 and the first switch N23 are turned off, and the bit line BLo is separated from the second sensing node SOo. Therefore, the voltage of the bit line BLo becomes the bit line bias voltage VIRPWRo level during the time Ts. At this time, the time Ts is a bit line recovery time. Meanwhile, due to the coupling capacitance component between the bit lines BLe and BLo, the voltage of the bit line BLe is temporarily changed as shown by the portion H. As shown in FIG. However, since the first program data PQ1 having a value of '0' is supplied to the bit line BLe, the voltage level of the bit line BLe becomes 0V.

As described above, since the bit line bias voltages VIRPWRe and VIRPWRo may be independently supplied to the bit lines BLe and BLo in the page buffer circuit 100, it is necessary without a bit line precharge process. none. Thus, the bit line setup time can be reduced, and the overall program time can also be reduced. In addition, since the bit line bias voltages VIRPWRe and VIRPWRo are supplied to the bit lines BLe and BLo, respectively, the bit lines connected to the memory cells to be programmed inhibited are connected by bit lines connected to the memory cells to be programmed. Since the voltage of the line can be prevented from dropping, the bit line recovery time can also be shortened.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the total program time can be reduced by providing bit line bias voltages that can be independently controlled for the bit lines, thereby reducing the time required for the bit line precharge process.

Claims (5)

Stores first sensing data corresponding to a voltage of a first sensing node determined by first read data from memory cells connected to a first bit line in a read operation, and memory cells connected to the first bit line in a program operation. A first page buffer for storing first program data to be programmed into the first page buffer; And Store second sensing data corresponding to a voltage of a second sensing node determined by second read data from memory cells connected to the second bit line in the read operation, and store the second sensing data in the second bit line in the program operation. A second page buffer for storing second program data to be programmed in the connected memory cells, The first page buffer and the second page buffer share a Y-gate circuit, and the Y-gate circuit responds to an input / output control signal during the read operation or the program operation, so that the first page buffer or the second page buffer may be used. Page buffer circuit in a flash memory device that connects a page buffer to data input / output lines. The method of claim 1, wherein the first page buffer, A bit line selection circuit connecting the first bit line to the first sensing node in response to a bit line selection signal and supplying a bit line bias voltage to the first bit line in response to a bit line control signal; A precharge circuit for precharging the first sensing node to a set voltage level in response to a precharge control signal; In the read operation, in response to a latch control signal, the first sensing data corresponding to the first read data is generated to store the first sensing data, and in the program operation, the first program data is stored. A register circuit; A data input circuit outputting the first program data received from the data input / output line through the Y-gate circuit to the register circuit in response to input control signals; A first switch configured to output the first program data received from the register circuit to the first bit line through the first sensing node in response to a program control signal; And And a second switch configured to output the first sensed data received from the register circuit to the data input / output line through the Y-gate circuit in response to a read control signal. The method of claim 2, wherein the register circuit, A sensing circuit configured to generate the first sensing data according to a voltage level of the first sensing node in response to a latch control signal during the read operation; A latch circuit for latching the first sensing data or the first program data; And And a reset circuit for initializing the latch circuit in response to a reset control signal. The method of claim 1, wherein the second page buffer, A bit line selection circuit connecting the second bit line to the second sensing node in response to a bit line selection signal, and supplying a bit line bias voltage to the second bit line in response to a bit line control signal; A precharge circuit for precharging the second sensing node to a set voltage level in response to a precharge control signal; In the read operation, in response to a latch control signal, the second sensing data corresponding to the second read data is generated to store the second sensing data, and in the program operation, the second program data is stored. A register circuit; A data input circuit outputting the second program data received from the data input / output line through the Y-gate circuit to the register circuit in response to input control signals; A first switch outputting the second program data received from the register circuit to the second bit line through the second sensing node in response to a program control signal; And And a second switch configured to output the second sensed data received from the register circuit to the data input / output line through the Y-gate circuit in response to a read control signal. The method of claim 4, wherein the register circuit, A sensing circuit configured to generate the second sensing data according to a voltage level of the second sensing node in response to a latch control signal during the read operation; A latch circuit for latching the second sensing data or the second program data; And And a reset circuit for initializing the latch circuit in response to a reset control signal.

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