KR20080030276A - Page buffer of flash memory device and reading method the same - Google Patents

Abstract

A page buffer of a flash memory device and a reading method using the same are provided to simplify the configuration of the page buffer by reading data of the flash memory device without constituting a read transistor, by outputting data stored in a register by connecting a data input part to an input/output port during read operation. A bit line selection part(110) selects one of a pair of bit lines connected to a number of memory cells, and then connects the selected bit line to a sensing node. A precharge part(120) precharges the sensing node to a constant level. A register(130,140) stores data of the selected memory cell received through the sensing node, and outputs the received data to an input/output port through a data input/output part. The data input/output part receives data from the input/output port during program operation, and outputs output data to the input/output port during read operation.

Description

Page Buffer of Flash memory device and reading method the same}

1 is a circuit diagram of a page buffer of a general NAND type flash memory device.

2 is a page buffer circuit diagram of a flash memory device according to an embodiment of the present invention.

3 is a timing diagram of signals for explaining an operation of FIG. 2.

Description of the main parts of the drawing

110: bit line selection unit 120: precharge unit

130: main register 140: cache register

LAT1, 2: latch

The present invention relates to a page buffer of a flash memory device and a method of reading the same, and to a page buffer of a flash memory device and a method of reading the same, which can reduce a line loading time by using a data input / output unit during a data read operation.

Recently, there is an increasing demand for semiconductor memory devices that can be electrically programmed and erased and that do not require a refresh function to rewrite data at regular intervals. In order to develop a large-capacity memory device capable of storing more data, a technology for high integration of memory devices has been studied. Accordingly, researches on flash memory have been actively conducted. Flash memory is generally classified into NAND flash memory and NOR flash memory. NOR-type flash memory has a structure in which memory cells are independently connected to bit lines and word lines, and thus have excellent random access time characteristics. On the other hand, the NAND type flash memory has excellent characteristics in terms of integration since a plurality of memory cells are connected in series and only one contact is required per cell string. Therefore, a NAND type structure is mainly used for the highly integrated flash memory.

NAND-type flash memory devices use a page buffer to program and read large amounts of information in a short time.

1 is a circuit diagram of a page buffer of a general NAND type flash memory device. The read operation of the flash memory device is performed using only one register. A brief description of a read operation of a flash memory device using a conventional page buffer is as follows.

For example, the case in which the bit line to be read is an even bit line BLe will be described.

First step: ①

First, the reset signal RESET_L is applied at a high level for a predetermined time and the NMOS transistor N9 is turned on. Thus, node QA is initialized to a low level. Thereafter, the precharge signal PRECHARGE is applied at a low level to turn on the PMOS transistor P1. Thus, the sensing node SO is precharged to a high level.

The discharge signal DISCHe is applied at a low level to block the bias voltage VIRPWR applied to the even bit line BLe by turning on the NMOS transistor N1. Thereafter, the bit line selection signal BSLe is applied at a high level to turn on the NMOS transistor N3. Therefore, the sensing node SO is connected to the even bit line BLe. The potential of the sensing node SO changes due to the charge sharing operation according to the program state of the read memory cell connected to the even bit line BLe.

Second step: ②

The NMOS transistor N5 is turned on or off according to the potential of the sensing node SO. At this time, the high level read signal READ_L is applied to the NMOS transistor N6 to turn on the NMOS transistor N6. Therefore, when the NMOS transistors N5 and N6 are turned on at the same time, the node QAb changes to a low level, and when the NMOS transistor N5 is turned off, the node QAb maintains a high level.

The potential signal of the node QAb is inverted and output by the inverter I3.

Third step: ③

The high level page buffer read signal PBDO_L is applied to the NMOS transistor N10 to turn on the NMOS transistor N10. Therefore, the data inverted and output by the inverter I3 is output to the outside through the input / output terminal YA.

As described above, the data read operation using the page buffer according to the prior art is output through the inverter I3 and the NMOS transistor N10 to output the data stored in the register to the input / output terminal. This increases the line loading according to the inversion operation, resulting in inefficiency of the read operation.

The technical problem to be achieved by the present invention is to connect the data input unit used in programming with an input / output terminal during a read operation to output data stored in a register, thereby simplifying the configuration of the page buffer by reading data of a flash memory device without configuring a read transistor. A page buffer of a flash memory device and a read method using the same are provided.

A page buffer of a flash memory device according to an embodiment of the present invention may include a bit line selector configured to select one bit line among a pair of bit lines to which a plurality of memory cells are connected, and to connect the sensing node to a predetermined level. A precharge unit for precharging, and a register for storing data of the selected memory cell received through the sensing node, and outputting the received data to an input / output terminal through a data input / output unit, wherein the data input / output unit is used during a program operation. Data is transmitted from the input / output terminal, and output data is output to the input / output terminal during a read operation.

According to an embodiment of the present disclosure, a method of reading a flash memory device using a page buffer may include transmitting cell data to the sensing node through selected bit lines of the pair of bit lines, and transmitting the cell data to the sensing node. Sensing and storing the cell data in the register, and outputting the cell data stored in the register to the input / output terminal through the data input / output unit.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

2 is a page buffer circuit diagram of a flash memory device according to an embodiment of the present invention.

Referring to FIG. 2, the page buffer 100 according to an embodiment of the present invention may be connected to the bit line selection unit 110 and the sensing node SO connected between the bit lines (even and odds) and the sensing node SO. And a main register 130 and a cache register 140 connected in parallel between the connected precharge unit 120, the sensing node SO, and the input / output terminal YA.

The bit line selector 110 selects the even bit line BLe or the odd bit line BLO during the program and read operation according to the selection signal, and connects the bit line selector 110 to the sensing node SO.

The bit line selector includes a plurality of NMOS transistors NM1 to NM4. The NMOS transistor NM3 is connected between the even bit line BLe and the sensing node SO, and is turned on in response to the even bit line select signal BSLe. Therefore, the even bit line BLe and the sensing node SO are connected. The NMOS transistor NM4 is connected between the odd bit line BLo and the sensing node SO, and is turned on in response to the odd bit line select signal BSLo. Therefore, the odd bit line BLo is connected to the sensing node SO. The NMOS transistors NM1 and NM2 are connected in series between the even bit line BLe and the odd bit line BLo so that the NMOS transistor NM1 is turned on in response to the even discharge signal DISe, and the NMOS transistor NM2 Is turned on in response to the odd discharge signal DISo. Accordingly, the bias voltage VIRPWR is applied to the even bit in BLe and the odd bit in BLo.

The precharge unit 120 precharges the sensing node SO to a predetermined potential during a program and read operation.

The precharge unit 120 includes a PMOS transistor PM1 connected between the power supply voltage Vdd and the sensing node SO. The PMOS transistor PM1 is turned on in response to the low level precharge signal PRECHARGE_L to apply the voltage Vdd to the sensing node SO.

The main register 130 includes a data sensing circuit 131, a data input / output unit 132, a latch LAT1, a program unit 133, and an initialization circuit NM9.

The latch LAT1 is composed of two inverters IV1 and IV2 connected in reverse parallel between the node QAb and the node QA.

The data sensing circuit 131 includes NMOS transistors NM5 and NM6. The NMOS transistors NM5 and NM6 are connected in series between the node QAb and the ground power supply, and latch the data transmitted to the sensing node SO in response to the potential of the sensing node SO and the read signal READ_L, respectively. LAT1).

The data input / output unit 132 includes NMOS transistors NM7 and NM8. The NMOS transistor NM7 is connected between the input / output terminal YA and the node QAb and turned on in response to the data input signal DI_L signal. The NMOS transistor NM8 is connected between the input / output terminal YA and the node QA and turned on in response to the data input signal nDI_L signal or the data read signal DO.

The initialization circuit NM9 is connected between the ground power supply and the node QA and turned on in response to the initialization signal RESET_L signal.

The program unit 133 includes an inverter IV3 and an NMOS transistor N10. The inverter IV3 is connected to the node QAb and inverts and outputs the potential signal of the node QAb. The NMOS transistor N10 is connected between the sensing node SO and the output terminal of the inverter IV3 and turned on in response to the program signal PROGRAM_L.

 Since the cache register 140 is configured similarly to the main register 130, a description thereof will be omitted.

3 is a waveform diagram illustrating signals for explaining a read operation using a page buffer according to an embodiment of the present invention.

Referring to Figures 2 and 3 will be described in detail the read operation according to an embodiment of the present invention.

In an embodiment of the present invention, a method of reading data of an even bit line BLe will be described as an example.

1) First step T1

The initialization signal RESET_L transitions to a high level for a predetermined time and the NMOS transistor NM9 of the register 130 is turned on. Therefore, the node QA is connected to the ground power source Vss and discharged to a low level to initialize the node QA.

The low-level discharge signals DISCHe and DISCHo transition to a high level so that the NMOS transistors NM1 and NM2 of the bit line selector 110 are turned on. Therefore, the bias voltage VIRPWR is applied to the bit lines BLe and BLo. At this time, the bias voltage VIRPWR is 0V.

2) second stage (T2)

A low level is applied to the with line of the selected memory cell connected to the even bit line BLe, and a passing voltage is applied to the word lines of the remaining unselected memory cells. In addition, the drain select signal DSL is applied at a high level.

The high level precharge signal PRECHb transitions to the low level and a power supply voltage is applied to the sensing node SO.

The discharge signal DISCHe applied to the high level transitions to the low level, and the NMOS transistor NM1 is turned off. Therefore, the bias voltage VIRPWR applied to the bit line BLe is cut off.

The high level bit line selection signal BSLe is applied to the NMOS transistor NM3 of the bit line selection unit 110 to connect the bit line BLe and the sensing node SO. Accordingly, the even bit line BLe is precharged to a high level according to the potential of the sensing node SO.

3) Third Step (T3)

The NMOS transistor NM3 is turned on because the high level bit line selection signal BSLe transitions to the low level. Therefore, the sensing node SO and the even bit line BLe are blocked. In this case, if the selected memory cell is a program cell, the even bit line BLe maintains a high level, and in the case of an erase cell, the even bit line BLe is discharged to a low level.

4) Fourth Step (T4)

The NMOS transistor NM13 is turned on because the bit line select signal BSLe transitions to a high level. Therefore, the sensing node SO is connected to the even bit line BLe. Accordingly, the potential of the sensing node SO precharged to the high level is maintained at the high level or discharged to the low level by the charge sharing operation.

The NMOS transistor NM5 of the main register 130 is turned on or off according to the potential of the sensing node SO. At this time, the high level read signal READ_L is applied to turn on the NMOS transistor NM6. Therefore, when the sensing node SO is at the high level, the NMOS transistors NM5 and NM6 are turned on at the same time so that the node QAb is at the low level. On the contrary, when the sensing node SO is at the low level, the NMOS transistor NM5 is turned off, so that the node QAb is maintained in the initialization state, that is, the high level state even when the NMOS transistor NM6 is turned on. Thereafter, the data read signal DO is applied to the NMOS transistor NM8 of the data input / output circuit 132 so that the node QA and the input / output terminal YA are connected to each other so that the data stored in the latch LAT1 is input / output terminal YA. Is output via

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to an embodiment of the present invention, a page buffer of a flash memory device and a read method using the same are provided. The data input unit used in programming is connected to an input / output terminal during a read operation to output data stored in a register, The configuration of the page buffer can be simplified by reading data of a flash memory device without configuration.

Claims (5)

A bit line selector configured to select one bit line from among a pair of bit lines to which a plurality of memory cells are connected, and to connect the bit line to a sensing node; A precharge unit configured to precharge the detection node to a predetermined level; A register for storing data of the selected memory cell received through the sensing node and outputting the received data to an input / output terminal through a data input / output unit, And the data input / output unit receives data from the input / output terminal during a program operation and outputs output data to the input / output terminal during a read operation. The method of claim 1, The register includes a latch for storing the output data; An initialization circuit for initializing the latch in response to an initialization signal; A data sensing circuit transferring data of the selected memory cell to the latch in response to a potential of the sense node and a read signal; And And a data input / output circuit coupled between the latch and the input / output terminal, the data input / output circuit transferring program data to the latch or transmitting the output data stored in the latch to the input / output terminal in response to a data input signal or a data read signal. Page buffer of the memory device. The method of claim 2, The data input / output circuit may include a first NMOS transistor connected to a first terminal of the latch and turned on in response to the data input signal; And And a second NMOS transistor connected to the second terminal of the latch and turned on in response to the data input signal or the data read signal. A bit line selector configured to select one bit line among a pair of bit lines connected with a plurality of memory cells and to connect the sensing node, a precharge unit precharged the sensing node to a predetermined level, and the transmission node received through the sensing node A page buffer of a flash memory device, the register storing data of a selected memory cell and outputting the received data to an input / output terminal through a data input / output unit. Transmitting cell data to the sensing node via a selected bitline of the pair of bitlines; Sensing the cell data transmitted to the sensing node and storing the cell data in the register; And outputting the cell data stored in the register to the input / output terminal through the data input / output unit. The method of claim 4, wherein And outputting the data to the input / output terminal through the data input / output unit directly outputs the cell data to the input / output terminal without inverting the cell data.

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