KR20060099934A - Method for preventing leakage current in programming non-volatile memory device - Google Patents

Abstract

According to the present invention, a bias voltage equal to the boosted channel voltage of memory cells of an unselected string is applied to a common source line of a NAND flash memory device, thereby providing a voltage between the channel voltage of the memory cell of the unselected string and the voltage of the common source line. By reducing the difference, the present invention relates to a method of suppressing leakage current flowing to a common source line.

Common Source Line, Channel Boosting

Description

Method for preventing leakage current in programming non-volatile memory device

1 is a circuit diagram illustrating a conventional NAND flash memory device.

2 is a circuit diagram illustrating a NAND flash memory device according to a preferred embodiment of the present invention.

3 is a diagram illustrating a program bias condition of the NAND flash memory device of FIG. 2.

4 is a cross-sectional view of the NAND flash memory device of FIG. 2.

<Description of Symbols for Main Parts of Drawings>

10, 100: memory cell array

10a, 10b, 100a, 100b: string

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for preventing leakage current during a program operation of a nonvolatile memory device, and more particularly, to prevent leakage current from occurring in a common selection line of an unselected string during a program operation of a NAND flash memory device. Will on the way.

Recently, there is an increasing demand for flash memory devices that can be electrically programmed and erased and that data can be stored without being erased even when power is not supplied.

In general, a flash memory device includes a memory cell array including a plurality of memory cells connected between a word line and a bit line, and a plurality of peripheral circuits for storing or reading data in each memory cell of the memory cell array.

The memory cell array is divided into a plurality of blocks, and is divided into a NOR type and a NAND type according to a memory cell connection type. In the NOR type memory cell array, memory cells between word lines and bit lines are connected in a matrix manner. A NAND type memory cell array is shown in FIG. 1, where a plurality of memory cells MC are connected in series between the drain select transistor DST and the source select transistor SST to form one string 10a. .

The channel of the memory cells MC0-MC31 of the unselected string 10a shown in FIG. 1 is boosted to about 8V by the power supply voltage VCC applied to the unselected bit line BLe. In this case, the voltage difference between the channel voltage (approximately 8V) of the memory cells MC0-MC31 and the voltage VCC of the common source line CSL is large, and a leakage current flows through the common source line CSL. Therefore, there is a problem that the boosted channel voltage is dropped.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and applies a bias voltage equal to the boosted channel voltage of memory cells of an unselected string to a common source line of a NAND flash memory device to prevent leakage current flowing to the common source line. It aims to suppress.

According to a preferred embodiment of the present invention for achieving the above object, it is disposed in the cross region of the bit lines and word lines, and is connected to a first source transistor and a common source line connected to each of the bit lines. A method of preventing leakage current during a program operation of a nonvolatile memory device including a plurality of cell strings having memory cells connected in series between second selection transistors may be connected to an unselected bit line among the bit lines during a program operation. Applying a program voltage to selected word lines of the word lines and a program inhibit voltage to unselected word lines to boost a channel of the first group of memory cells to a first voltage; And applying a bias voltage equal to the boosted first voltage to the common source line.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates a NAND flash memory device according to a preferred embodiment of the present invention.

Referring to FIG. 2, the memory cell array 100 includes a string 100a including memory cells MC0-MC31 connected in series between a drain select transistor DST and a source select transistor SST, and a drain select transistor. A string 100b is formed of memory cells MC0'-MC31 'connected in series between the DST' and the source select transistor SST '. N such strings exist in the memory cell array 100.

The top memory cells MC31 and MC31 'of the memory cell MC are connected to the bit lines BLe and BLo through the drain select transistors DST and DST', respectively, and the bottommost memory cells MC0 and MC0 'are the source. It is connected to the common source line CSL through the selection transistors SST and SST '. Gates of the drain select transistors DST and DST 'are connected to the drain select line DSL, and gates of the source select transistors SST and SST' are connected to the source select line SSL.

3 illustrates a program bias condition of the NAND flash memory device of FIG. 2. Hereinafter, the program bias condition of the NAND flash memory device according to the present invention will be described with reference to FIG. 3.

In the program operation, a voltage of 0 V is applied to the selected bit line BLO and a power supply voltage Vcc is applied to the unselected bit line BLe. The reason why the power supply voltage Vcc is applied to the unselected bit line BLe is to block a program by boosting a channel of the memory cell MC. A program voltage Vpgm of 15 to 20 V is applied to the selected word line WL, and a program prohibition voltage Vpass of 8 to 10 V is applied to the unselected word line WL. The power supply voltage Vcc is applied to the gate of the drain select transistor DST through the drain select line DSL, and the voltage of OV is applied to the gate of the source select transistor SST through the source select line SSL. Although the power source voltage VCC is conventionally applied to the common source line CSL, the boosted channel voltage Vch of the memory cells MC0-MC31 in the unselected string 100a is applied to the common source line CSL. The boosted channel voltage Vch of the memory cells MC0-MC31 may vary depending on the voltage levels of the program voltage Vpgm and the program inhibit voltage Vpp.

4 is a cross-sectional view of the NAND flash memory device of FIG. 2, hereinafter, with reference to FIG. 4, the boosted channel voltage and the voltage of the common source line CSL of the memory cells MC0-MC31 in the unselected string 100a. The method of reducing the leakage current to the common source line by reducing the difference will be described in more detail.

The memory cell MC is a MOSFET having a stacked gate structure in which the floating gate FG and the control gate CG are stacked. The control gate CG of the memory cell MC is connected to the word line WL.

0 V is applied to the selected bit line BLO to program, but a power supply voltage VCC is applied to the unselected bit line BLe to prevent programming. At this time, when the drain select transistor DST is turned on, voltage shift occurs by Vcc-Vt (Vt is the threshold voltage of DST.) Toward the channels of the memory cells MC0-MC31, and thus the memory cells MC0-MC31. The channel voltage of becomes Vcc-Vt. At this point, the drain select transistor DST is turned off without forming a channel.

Here, the tunnel oxide capacitance Cox and the oxide Nitride Oxide (ONO) capacitance Cono exist between the channel of the memory cells MC0-MC31 and the control gate CG, and between the channel and the bulk substrate Si-Sub. There is a depletion capacitance (Cch). Accordingly, the channel voltages Vch0-Vch31 of the memory cells MC0-MC31 are boosted to about 8V by coupling of three capacitances Cono, Cox, and Cch. At this time, in order to boost the channel voltages Vch0-Vch31, 0V is applied to the source select line SSL, and the channel voltage Vchs of the source select transistor SST becomes 0V.

In order to reduce the voltage difference between the boosted channel voltage Vch0-Vch31 and the voltage of the common source line CSL, the common source line CSL is biased by the boosted channel voltage Vch0 to Vch31 = approximately 8V. Voltage is applied.

In this case, the voltage difference between the channel voltages Vch0-Vch31 of the memory cells MC0-MC31 and the voltage of the common source line CSL is eliminated, so that a leakage current does not occur in the common source line CSL.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, it is possible to eliminate leakage current that may be generated between the boosted channel of the unselected string and the common source line during the program operation of the NAND flash memory device.

As a result, the boosted channel voltage can be prevented from being dropped, thereby reducing the failure due to the disturbance occurring during the program operation.

In addition, since the program disturb can be prevented, the characteristics of the NAND flash memory device can be improved, and thus yield improvement can be expected.

Claims (4)

A cell having memory cells disposed in a cross region of bit lines and word lines, and connected in series between a first select transistor connected to each of the bit lines and a second select transistor connected to a common source line. A method of preventing leakage current during a program operation of a nonvolatile memory device including a plurality of strings, the method comprising: In a program operation, in order to boost a channel of a first group of memory cells connected to an unselected bit line among the bit lines with a first voltage, a program voltage is applied to a selected word line among the word lines, and a non-selected word line is selected. Applying a program inhibit voltage to the controller; And And applying a bias voltage equal to the boosted first voltage to the common source line. The method of claim 1, The bias voltage applying step may include applying the bias voltage to the common source line to reduce a voltage difference between channel voltages of the first group of memory cells and a bias voltage of the common source line. How to prevent leakage current of devices. The method of claim 1, A power supply voltage is applied to a gate of the first selection transistor, and a ground voltage is applied to a gate of the second transistor. The method of claim 1, A ground voltage is applied to a selected bit line among the bit lines, and a power supply voltage is applied to an unselected bit line among the bit lines to prohibit the program. Prevention method.

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