KR20060085288A - Apparatus of testing display device - Google Patents

Abstract

The present invention relates to an inspection device for a display device, in particular an array test inspection device for a display device.

A test device of a display device connected to each other and generating a test signal and applying a test signal to a gate line, respectively, comprising: first to fifth signal pads and at least one of the first to fifth signal pads; And a plurality of transistors connected to one, wherein the second and third signal pads are connected to each other and the remaining pads are separated from each other.

In this manner, by separating the other signal pads except the clock signal pads and sequentially applying high voltage and low voltage at a time difference, the detection power can be improved by distinguishing between the normal screen and the bad screen of the test screen.

Display, Inspection, Array, Stage, Gate Driver, Transistor, Diode

Description

Inspection device for display device {APPARATUS OF TESTING DISPLAY DEVICE}

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a gate driver according to an exemplary embodiment of the present invention.

FIG. 4 is an example of a circuit diagram of the j-th stage of the shift register for gate driver shown in FIG.

5 is a signal waveform diagram of the gate driver illustrated in FIG. 3.

6 is an example of a circuit diagram of a test apparatus for a display device according to an exemplary embodiment of the present invention.

FIG. 7 is a signal waveform diagram applied to the signal pad shown in FIG. 6.

The present invention relates to an inspection apparatus of a display device.

Recently, organic light emitting display (OLED), plasma display panel (PDP), and liquid crystal display (LCD) are substituted for heavy and large cathode ray tube (CRT). Flat panel display devices such as are being actively developed.

PDP is a device that displays characters or images using plasma generated by gas discharge, and OLED displays characters or images by using electroluminescence of specific organic materials or polymers. The liquid crystal display device applies an electric field to a liquid crystal layer interposed between two display panels, and adjusts the intensity of the electric field to adjust a transmittance of light passing through the liquid crystal layer to obtain a desired image.

Among such flat panel display devices, for example, a liquid crystal display and an organic EL display device may turn on / off a switching element of a pixel by emitting a gate signal to a pixel including a switching element, a display panel provided with a display signal line, and a gate line among the display signal lines. A gate driver to turn off, i.e., a shift register.

The shift register includes a plurality of stages connected to each other, each stage including a plurality of transistors, and outputting an output based on the output of the front and rear stages and in synchronization with any one of the plurality of clock signals.

On the other hand, if there is a disconnection such as a display signal line in the process of manufacturing the flat panel display device, these are filtered out in advance through a predetermined inspection. These types of inspections include array tests, visual inspection (VI) tests, gross tests, and module tests.

The array test is a test that applies a constant voltage before separating into individual cells and checks whether the display signal line is disconnected through the presence or absence of an output voltage. The VI test separates into individual cells and then applies a constant voltage. It is a test to check whether the signal line is disconnected while looking at the human eye. The gross test is a test that checks the quality and disconnection of the display signal line through the display state of the screen by combining the upper panel and the lower panel and applying the same voltage as the actual driving voltage before mounting the driving circuit. Finally, the test is to find out whether the driving circuit works properly.

At this time, the array test and the VI test except for the gross test performed in a situation similar to the actual driving condition and the module test performed in the same situation as the actual driving situation are generally used to test the display signal lines in a group. In the array test and the VI test, a test wire crossing the display signal line is provided separately, and a wide end pad is connected to the test wire to apply a signal to the pad.

However, when a signal is applied through the pad, the driving circuit corresponds to an integrated circuit, and when the signal is not an integrated circuit, the inspection method must be different.

For example, when the shift register is formed in the same process as the switching element of the pixel and integrated in the display panel, it is possible to determine whether the gate line is disconnected by applying a test signal to the gate line through the shift register.

In this case, the signal pads for driving the shift registers are bundled together and a single signal is applied to check whether the gate lines are disconnected. This method has a problem in that the detection power is inferior. For example, array tests use photo sensors to calculate the amount of transmitted light to check for disconnections or short circuits. However, there is a problem in that the detection screen is inferior because the inspection screen is almost the same as the screen appearing at the time of short circuit or disconnection.

Accordingly, an object of the present invention is to provide an inspection apparatus for a display device that can solve the problems of the prior art.

According to an embodiment of the present invention for achieving the above technical problem, an inspection apparatus of a display device including a plurality of stages connected to each other and generating a test signal and applying to a gate line, respectively, A fifth signal pad and a plurality of transistors connected to at least one of the first to fifth signal pads, wherein the second and third signal pads are connected to each other and the remaining pads are separated from each other.

In this case, the stage may include a first transistor having an input terminal connected to the second and third signal pads, an output terminal connected to the gate line, and a control terminal connected to a predetermined contact point, and the first transistor. The second transistor may include an input terminal connected to the signal pad, an output terminal connected to the contact point, and a control terminal connected to the fourth signal pad.

In particular, the last stage of the stage preferably includes the first and second transistors, and a diode connected between the gate line and the fourth signal pad.

The diode may be a transistor having an input terminal and a control terminal commonly connected to an output terminal of the first transistor, and an output terminal connected to the fourth signal pad.

The stage may further include a third transistor having an input terminal connected to the fifth signal pad, an output terminal connected to the gate line, and a control terminal connected to a gate line connected to a rear stage.

In this case, the stage may be integrated in the display device, and the first to third transistors may include a semiconductor layer made of amorphous silicon.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A display device according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.                     

1 is a block diagram of a display device according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the display device according to an exemplary embodiment of the present invention includes a display panel 300, a gate driver 400 connected thereto, a data driver 500, and a gray voltage generator connected to the data driver 500. 800, and a signal controller 600 for controlling them.

The display panel unit 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels Px connected to the plurality of display signal lines G ₁ -G _n and D ₁ -D _m in an equivalent circuit.

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n transmitting gate signals (also called scan signals) and data lines D ₁ transferring data signals. includes -D _m). gate lines (G ₁ -G _n) extend in a substantially row direction and are substantially parallel to the data lines (D ₁ -D _m) to each other and extending substantially in a column direction are substantially parallel to each other .

Each pixel includes a switching element Q connected to the display signal lines G ₁ -G _n , D ₁ -D _m , and a pixel circuit Px connected thereto.

The switching element Q is a three-terminal element whose control terminal and input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively, and the output terminal is the pixel circuit Px. Is connected to. In addition, the switching element Q is preferably a thin film transistor, and particularly preferably comprises amorphous silicon.

In the case of a liquid crystal display device which is a representative example of a flat panel display device, as shown in FIG. 2, the display panel unit 300 includes a lower panel 100, an upper panel 200, and a liquid crystal layer 3 therebetween. The display signal lines G ₁ -G _n , D ₁ -D _m and the switching elements Q are provided on the lower display panel 100. The pixel circuit Px of the liquid crystal display includes a liquid crystal capacitor C _LC and a storage capacitor C _ST connected in parallel to the switching element Q. The holding capacitor C _ST can be omitted as necessary.

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel should be able to display color, which is a color filter 230 of three primary colors, for example, red, green, or blue, in a region corresponding to the pixel electrode 190. It is possible by providing. In FIG. 2, the color filter 230 is formed on the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

Polarizers (not shown) for polarizing light are attached to outer surfaces of at least one of the two display panels 100 and 200 of the display panel unit 300 of the liquid crystal display device.

The gray voltage generator 800 generates one or two gray voltages related to the luminance of the pixel. If there are two sets, one of the sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is integrated in the display panel unit 300 and is connected to the gate lines G ₁ -G _n to turn on the switching element Q and the gate on voltage V _on and the switching element Q. to be applied to turn the gate signal which is a combination of a gate-off voltage (V _off) which can be turned off the gate lines (G ₁ -G _n).

The data driver 500 is connected to the data lines D ₁ -D _m of the display panel 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

The display operation of such a display device will now be described in more detail.

The signal controller 600 may control the input image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal and the input image signals R, G, and B, and generates the image signals R, G, and B. After appropriately processing the display panel 300 according to the operating conditions, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transferred to the data driver 500. Export.

The gate control signal (CONT1) is the gate-on scanning start instructing the start of output of a voltage (V _on) signal (STV), a gate-on voltage (V _on) on-voltage gate clock signal (CPV), and a gate for controlling the output timing of the An output enable signal OE or the like that defines the duration of V _on .

The data control signal CONT2 is a load signal LOAD and a data clock signal for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data DAT and the data lines D ₁ -D _m . (HCLK). In the case of the liquid crystal display shown in FIG. 2, an inverted signal (RVS) inverting the polarity of the data voltage with respect to the common voltage V _com (hereinafter, referred to as the polarity of the data voltage by reducing the polarity of the data voltage with respect to the common voltage). ) May also be included.

The data driver 500 sequentially receives the image data DAT corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and among the gray voltages from the gray voltage generator 800. By selecting the gray scale voltage corresponding to each image data DAT, the image data DAT is converted into a corresponding data voltage and applied to the data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to. The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

In the case of the liquid crystal display shown in FIG. 2, the difference between the data voltage applied to the pixel and the common voltage V _com is represented as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage. As a result, the polarization of light passing through the liquid crystal layer 3 changes. This change in polarization is represented by a change in transmittance of light by polarizers attached to the display panels 100 and 200.

After one horizontal period (or 1H ″) (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 may move to the next row. In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply the data voltages to all the pixels. In the case of the liquid crystal display shown in Fig. 2, in particular, when one frame ends, the next frame is started and the data driver 500 is applied to the data driver 500 such that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame. The state of the inverted signal RVS being controlled is controlled ("frame inversion"), in which the polarity of the data voltage flowing through one data line is changed ("line inversion") according to the characteristics of the inversion signal RVS within one frame. ), One pixel row The polarity of the data voltage to be applied may also be different from one another ( "dot inversion").

Next, the gate driver of the display device according to an exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 3 to 5.

3 is a block diagram of a gate driver according to an exemplary embodiment of the present invention. FIG. 4 is an example of a circuit diagram of the j-th stage of the shift register for gate driver shown in FIG. 3, and FIG. 5 is a signal waveform diagram of the gate driver shown in FIG.

The gate driver 400 shown in FIG. 3 is a shift register including a plurality of stages 410 arranged in a line and connected to the gate lines G ₁ -G _n , respectively, and include a scan start signal STV, The initialization signal INT, the plurality of clock signals CLK1 and CLK2 and the gate off voltage V _off are input. An NMOS transistor T14 is connected to the end of each gate line G ₁ -G _n , and a gate off voltage V _off is input.

Each stage 410 includes a set terminal S, a gate voltage terminal GV, a pair of clock terminals CK1 and CK2, a reset terminal R, a frame reset terminal FR, and a gate output terminal ( OUT1) and carry output terminal OUT2. However, the dummy dummy stage does not have the reset terminal R and the frame reset terminal FR.

Each stage, for example, the j-th stage (ST _j) the set terminal (S), the carry output of the front end stage (ST _j-1), i.e. shear carry output [Cout (j-1)] is a reset terminal ( The gate output of the rear stage ST _{j + 1} , that is, the rear gate output Gout (j + 1) is input to R, and the clock signals CLK1 and CLK2 are input to the clock terminals CK1 and CK2. The gate off voltage V _off is input to the gate voltage terminal GV. The gate output terminal OUT1 outputs the gate output Gout (j) and the carry output terminal OUT2 outputs the carry output Cout (j).

However, the scan start signal STV is input to the first stage of the shift register 400 instead of the front carry output. Further, when the clock signal CLK1 is input to the clock terminal CK1 of the j-th stage ST _j and the clock signal CLK2 is input to the clock terminal CK2, the (j-1) th and (j) adjacent thereto are The clock signal CLK2 is input to the clock terminal CK1 of the ₊ 1th stage ST _j-1 and ST _{j + 1} , and the clock signal CLK1 is input to the clock terminal CK2.

Each clock signal CLK1 and CLK2 is equal to the gate-on voltage V _on when the voltage level is high and the gate-off voltage V _off when the voltage level is high so as to drive the switching element Q of the pixel. It is preferable. As shown in FIG. 5, each clock signal CLK1 and CLK2 may have a duty ratio of 50%, and a phase difference between the two clock signals CLK1 and CLK2 may be 180 °.

Referring to FIG. 4, each stage of the gate driver 400 according to an embodiment of the present invention, for example, the j-th stage, includes an input unit 420 and a pull-up driver 430 as shown in FIG. 4. , A pull-down driver 440 and an output unit 450. These include at least one NMOS transistor T1-T15, and the pull-up driver 430 and the output unit 450 further include capacitors C1-C3. However, PMOS transistors may be used instead of NMOS transistors. In addition, the capacitors C1-C3 may actually be parasitic capacitances between the gate and the drain / source formed during the process.

The input unit 420 includes three transistors T11, T10, and T5 connected in series to the set terminal S and the gate voltage terminal GV. Gates of the transistors T11 and T5 are connected to the clock terminal CK2, and gates of the transistor T5 are connected to the clock terminal CK1. The contact between the transistor T11 and the transistor T10 is connected to the contact J1, and the contact between the transistor T10 and the transistor T11 is connected to the contact J2.

The pull-up driving unit 430 includes a transistor T4 connected between the set terminal S and the contact J1, a transistor T12 connected between the clock terminal CK1 and the contact J3, and a clock terminal ( And transistor T7 connected between CK1 and contact J4. The gate and the drain of the transistor T4 are commonly connected to the set terminal S, the source is connected to the contact J1, and the gate and the drain of the transistor T12 are commonly connected to the clock terminal CK1. And the source is connected to contact J3. The gate of the transistor T7 is connected to the contact J3 and at the same time connected to the clock terminal CK1 through the capacitor C1, the drain is connected to the clock terminal CK1, the source is connected to the contact J4. , Capacitor C2 is connected between contact J3 and contact J4.

The pull-down driver 440 receives the gate-off voltage V _off through a source and outputs a plurality of transistors T6, T9, T13, T8, T3, and T2 through a drain to the contacts J1, J2, J3, and J4. ). The gate of the transistor T6 is connected to the frame reset terminal FR, the drain is connected to the contact J1, the gate of the transistor T9 is connected to the reset terminal R, and the drain is connected to the contact J1. The gates of the transistors T13 and T8 are commonly connected to the contact J2, and the drains are connected to the contacts J3 and J4, respectively. The gate of the transistor T3 is connected to the contact J4, the gate of the transistor T2 is connected to the reset terminal R, and the drains of the two transistors T3 and T2 are connected to the contact J2.

The output unit 450 includes a pair of transistors T1 and T15 having a drain and a source connected between the clock terminal CK1 and the output terminals OUT1 and OUT2 and a gate connected to the contact J1, respectively. And a capacitor C3 connected between the gate and the drain of T1, that is, between the contact J1 and the contact J2. The source of transistor T1 is also connected to contact J2.

The operation of such a stage will now be described.

For convenience of explanation, the voltage corresponding to the high level of the clock signals CLK1 and CLK2 is referred to as a high voltage, and the magnitude of the voltage corresponding to the low level of the clock signals CLK1 and CLK2 is equal to the gate off voltage V _off . This is called low voltage.

First, when the clock signal CLK2 and the front carry output Cout (j-1) become high, the transistors T11 and T5 and the transistor T4 are turned on. Then, the two transistors T11 and T4 transfer a high voltage to the contact J1, and the transistor T5 transfers a low voltage to the contact J2. As a result, the transistors T1 and T15 are turned on so that the clock signal CLK1 is output to the output terminals OUT1 and OUT2. At this time, since the voltage of the contact J2 and the clock signal CLK1 are both low voltages, the output voltage [ Gout (j) and Cout (j)] become low voltage. At the same time, the capacitor C3 charges a voltage having a magnitude corresponding to the difference between the high voltage and the low voltage.

At this time, since the clock signal CLK1 and the rear gate output Gout (j + 1) are low and the contact J2 is also low, the transistors T10, T9, T12, T13, T8, and T2 connected to the gate are connected. ) Are all off.

Subsequently, when the clock signal CLK2 becomes low, the transistors T11 and T5 are turned off. At the same time, when the clock signal CLK1 becomes high, the output voltage of the transistor T1 and the voltage of the contact J2 become high. do. At this time, a high voltage is applied to the gate of the transistor T10, but since the potential of the source connected to the contact J2 is also the same high voltage, the potential difference between the gate sources becomes zero, so that the transistor T10 remains turned off. . Accordingly, the contact J1 is in a floating state, whereby the potential is further increased by the high voltage by the capacitor C3.

On the other hand, since the potentials of the clock signal CLK1 and the contact J2 are high voltage, the transistors T12, T13, and T8 are turned on. In this state, the transistor T12 and the transistor T13 are connected in series between the high voltage and the low voltage, so that the potential of the contact J3 is divided by the resistance value of the resistance state at the turn-on of the two transistors T12 and T13. Voltage value. However, assuming that the resistance value of the resistance state at the turn-on of the two transistors T13 is set to be very large compared to the resistance value of the resistance state at the turn-on of the transistor T12, for example, about 10,000 times, the voltage of the contact J3 is a high voltage. Is almost the same as Accordingly, the transistor T7 is turned on and connected in series with the transistor T8, so that the potential of the contact J4 is divided by the resistance value of the resistance state at the turn-on of the two transistors T7 and T8. Have At this time, if the resistance values of the resistance states of the two transistors T7 and T8 are set to be almost the same, the potential of the contact J4 has an intermediate value between the high voltage and the low voltage, whereby the transistor T3 is turned off. Keep it. At this time, since the rear gate output Gout (j + 1) is still low, the transistors T9 and T2 also remain turned off. Therefore, the output terminals OUT1 and OUT2 are connected only to the clock signal CLK1 and cut off from the low voltage to emit a high voltage.

On the other hand, the capacitor C1 and the capacitor C2 charge voltages corresponding to the potential difference between both ends, respectively, and the voltage of the contact J3 is lower than the voltage of the contact J5.

Subsequently, when the rear gate output Gout (j + 1) and the clock signal CLK2 go high and the clock signal CLK1 goes low, the transistors T9 and T2 are turned on to low voltage to the contacts J1 and J2. To pass. At this time, the voltage of the contact J1 falls to the low voltage while the capacitor C3 discharges, but it takes some time to completely lower to the low voltage due to the discharge time of the capacitor C3. Accordingly, the two transistors T1 and T15 remain turned on for a while even after the rear gate output Gout (j + 1) becomes high, whereby the output terminals OUT1 and OUT2 are connected to the clock signal CLK1. To emit low voltage. Subsequently, when the capacitor C3 is completely discharged and the potential of the contact J1 reaches a low voltage, the transistor T15 is turned off and the output terminal OUT2 is cut off from the clock signal CLK1, so that the carry output Cout (j) is performed. Becomes floating and maintains low voltage. At the same time, the output terminal OUT1 is continuously connected to the low voltage through the transistor T2 even when the transistor T1 is turned off, thereby continuously outputting the low voltage. At this time, the gate output Gout (j + 1) of the rear stage ST _{j + 1} is applied to the transistor T14 connected to the front gate line G _j so that the transistor T14 is turned on, thereby turning off the gate. The voltage V _off is output to the gate line G _j . The gate line G _j is then fixed once more with a low voltage.

On the other hand, since the transistors T12 and T13 are turned off, the contact J3 is in a floating state. In addition, the voltage of the contact J5 is lower than the voltage of the contact J4. The transistor T7 is turned off because the voltage of the contact J3 is kept lower than the voltage of the contact J5 by the capacitor C1. . At the same time, since the transistor T8 is also turned off, the voltage at the contact J4 is lowered by that amount, so that the transistor T3 also remains turned off. In addition, the transistor T10 maintains the turn-off state because the gate is connected to the low voltage of the clock signal CLK1 and the voltage of the contact J2 is low.

Next, when the clock signal CLK1 becomes high, the transistors T12 and T7 turn on, the voltage of the contact J4 rises, turns on the transistor T3, and transfers a low voltage to the contact J2. ) Continues to emit low voltage. That is, even if the rear gate output [Gout (j + 1)] is low, the voltage of the contact J2 can be made low.

Meanwhile, since the gate of the transistor T10 is connected to the high voltage of the clock signal CLK1 and the voltage of the contact J2 is a low voltage, the gate of the transistor T10 is turned on to transfer the low voltage of the contact J2 to the contact J1. On the other hand, the clock terminal CK1 is connected to the drains of the two transistors T1 and T15 so that the clock signal CLK1 is continuously applied. In particular, the transistor T1 is made relatively larger than the rest of the transistors, so that the parasitic capacitance between gate drains is large, so that the voltage change of the drain may affect the gate voltage. Therefore, when the clock signal CLK1 becomes high, the gate voltage may increase due to the parasitic capacitance between the gate and drain gates, thereby turning on the transistor T1. Therefore, the low voltage of the contact J2 is transferred to the contact J1 to maintain the gate voltage of the transistor T1 at a low voltage, thereby preventing the transistor T1 from turning on.

Thereafter, the voltage at the contact J1 maintains a low voltage until the front carry output Cout (j-1) becomes high, and the voltage at the contact J2 has the clock signal CLK1 high and the clock signal CLK2. Is low, the low voltage is maintained through the transistor T3, and vice versa, the low voltage is maintained through the transistor T5.

On the other hand, the transistor T6 receives the initialization signal INT generated at the last dummy stage ST _{n + 1} and transfers the gate-off voltage V _off to the contact J1 to transfer the voltage of the contact J1 once. Set it to a lower voltage.

In this manner, the stage 410 is based on the front carry signal Cout (j-1) and the back gate signal Gout (j + 1) and is synchronized with the clock signals CLK1 and CLK2 to carry the carry signal Cout ( j)] and the gate signal Gout (j).

On the other hand, the gate driver 400 is integrated on one edge of the display panel 300, and the inspection of the display device will be described in detail with reference to FIGS. 6 and 7.

6 is a schematic circuit diagram of a gate driver according to an exemplary embodiment of the present invention, and FIG. 7 is a signal waveform diagram of the gate driver illustrated in FIG. 6.

Here, FIG. 6 schematically shows only those necessary for driving in the circuit diagram shown in FIG. 4, and FIG. 7 shows the high voltage and the low voltage applied to the signal pad shown in FIG. 6.

As described above, in the array test for checking whether the display signal line, in particular, the gate line is disconnected, when the gate driver 400 is integrated, the gate driver 400 is driven to apply the test signal to the gate line.

6 and 7, gate-off voltage pads Voff, clock signal pads CLK1 and CLK2, scan start signal pads STV, and initialization signal pads NT are formed, respectively, and clock signal pads CLK1. , CLK2) are grouped together.

In particular, FIG. 6 is a circuit diagram of the n-th stage ST _n and the last dummy stage ST _{n + 1} and some transistors T1, T4, and T6 connected to the contact J1 in the circuit diagram shown in FIG. 4. Transistor T14 connected to the gate line G _n is shown.

Here, the gate-off voltage pad, the clock signal pad, the scan start signal pad, and the initialization signal pad and the signal lines connected thereto use the same reference numerals as Voff, CLK1, CLK2, STV, and INT.

At this time, one more transistor T16 is connected between the output terminal of the transistor T1 included in the dummy stage ST _{n + 1} and the initialization signal line INT. The transistor T16 has an input terminal and a control terminal connected to each other, substantially acting as a diode.

First, a high voltage is applied to the left and right gate-off voltage pads V _off , and then a high voltage is applied through the initialization signal pad INT. Then, the transistor T6 is turned on to transfer the high voltage to the contact J1 to turn on the transistor T1. At this time, the high voltage applied through the initialization signal pad INT is not input to the dummy gate line G _{n + 1} due to the transistor T16.

Subsequently, when a high voltage is applied through the clock signal pads CLK1 and CLK2, a high voltage is output to the gate lines G _n and G _{n + 1} through the turned-on transistor T1. At this time, since the transistor T14 is also turned on, the high voltage is output to the gate line G _n once more.

Next, when a low voltage is applied through the clock signal pads CLK1 and CLK2, a low voltage is output to the gate lines G _n and G _{n + 1} through the turned-on transistor T1, and the dummy gate line G _{n + 1} is applied. The transistor T14 connected to is turned off to block the high voltage applied from the gate-off voltage terminal V _off .

As such, by applying a high voltage, that is, a gate on voltage and a low voltage, that is, a gate-off voltage, to all the gate lines G ₁ -G _n , whether the gate lines are disconnected can be checked at once.

In addition, by separating the signal pads other than the clock signal pads and sequentially applying high voltage and low voltage at a time difference, the detection power may be improved by distinguishing the normal screen from the bad screen and the bad screen.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of right.

Claims (7)

An inspection apparatus of a display device, which includes a plurality of stages connected to each other and generating respective inspection signals to be applied to a gate line. First to fifth signal pads, and A plurality of transistors connected to at least one of the first to fifth signal pads Including, The second and third signal pads are connected to each other and the remaining pads are separated from each other. Inspection device of the display device. In claim 1, The stage is A first transistor having an input terminal connected to the second and third signal pads, an output terminal connected to the gate line, and a control terminal connected to a predetermined contact point, and A second transistor having an input terminal connected to the first signal pad, an output terminal connected to the contact point, and a control terminal connected to the fourth signal pad Inspection device of the display device including a. In claim 2, The last stage of the stage The first and second transistors, and A diode connected between the gate line and the fourth signal pad Containing Inspection device of the display device. In claim 3, And the diode is a transistor having an input terminal and a control terminal commonly connected to an output terminal of the first transistor, and an output terminal connected to the fourth signal pad. In claim 4, The stage further includes a third transistor having an input terminal connected to the fifth signal pad, an output terminal connected to the gate line, and a control terminal connected to a gate line connected to a rear stage. Inspection device. In claim 5, And the stage is integrated into the display device. In claim 6, And the first to third transistors include a semiconductor layer made of amorphous silicon.

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